Add support for v850E2 and v850E2V3
This commit is contained in:
Nick Clifton
parent
8fd447e6d3
commit
1cd986c585
32 changed files with 3931 additions and 1316 deletions
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@ -1,3 +1,41 @@
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2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
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Ina Pandit <ina.pandit@kpitcummins.com>
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* archures.c (DESCRIPTION): Define bfd_mach_v850e2 and
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bfd_mach_v850e2v3.
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* reloc.c (bfd_architecture): Define bfd_mach_v850e2 and
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bfd_mach_v850e2v3.
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(BFD_RELOC_V850_16_PCREL, BFD_RELOC_V850_17_PCREL,
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BFD_RELOC_V850_22_PCREL, BFD_RELOC_V850_23,
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BFD_RELOC_V850_32_PCREL, BFD_RELOC_V850_32_ABS,
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BFD_RELOC_V850_16_SPLIT_OFFSET, BFD_RELOC_V850_16_S1,
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BFD_RELOC_V850_LO16_SPLIT_OFFSET, BFD_RELOC_V850_SDA_15_16_OFFSET,
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BFD_RELOC_V850_ZDA_16_16_OFFSET, BFD_RELOC_V850_CALLT_15_16_OFFSET,
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BFD_RELOC_V850_32_GOTPCREL, BFD_RELOC_V850_16_GOT,
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BFD_RELOC_V850_32_GOT, BFD_RELOC_V850_22_PLT_PCREL,
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BFD_RELOC_V850_32_PLT_PCREL, BFD_RELOC_V850_COPY,
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BFD_RELOC_V850_GLOB_DAT, BFD_RELOC_V850_JMP_SLOT,
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BFD_RELOC_V850_RELATIVE, BFD_RELOC_V850_16_GOTOFF,
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BFD_RELOC_V850_32_GOTOFF, BFD_RELOC_V850_CODE,
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BFD_RELOC_V850_DATA): New relocations for V850 target.
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* config.bfd: Match all v850 targets.
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* cpu-v850.c (arch_info_struct): Define V850e2 and V850e2v3.
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* elf32-v850.c (v850_elf_check_relocs): Check the newly added
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relocations.
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(v850_elf_perform_relocation ): Update the newly added
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relocations.
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(v850_elf_howto_t): Update the specifications of added
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relocations.
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(v850_elf_reloc_map): Update the relocation mappings.
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(v850_elf_final_link_relocate): Maps added relocation into the
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appropriate howto structure.
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(v850_elf_object_p): Add support for V850E2 and V850E2V3.
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(v850_elf_final_write_processing): Likewise.
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(v850_elf_merge_private_bfd_data): Likewise.
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(v850_elf_print_private_bfd_data): Likewise.
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* libbfd.h: Regenerate.
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* bfd-in2.h: Regenerate.
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2010-07-23 Alan Modra <amodra@gmail.com>
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* archive.c (_bfd_archive_bsd44_construct_extended_name_table):
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@ -310,7 +310,9 @@ DESCRIPTION
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. bfd_arch_v850, {* NEC V850 *}
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.#define bfd_mach_v850 1
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.#define bfd_mach_v850e 'E'
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.#define bfd_mach_v850e1 '1'
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.#define bfd_mach_v850e1 '1'
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.#define bfd_mach_v850e2 0x4532
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.#define bfd_mach_v850e2v3 0x45325633
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. bfd_arch_arc, {* ARC Cores *}
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.#define bfd_mach_arc_5 5
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.#define bfd_mach_arc_6 6
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@ -1977,6 +1977,8 @@ enum bfd_architecture
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#define bfd_mach_v850 1
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#define bfd_mach_v850e 'E'
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#define bfd_mach_v850e1 '1'
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#define bfd_mach_v850e2 0x4532 /* ('E'<<8|'2') */
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#define bfd_mach_v850e2v3 0x45325633 /* ('E'<<24|'2'<<16|'V'<<8|'3') */
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bfd_arch_arc, /* ARC Cores */
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#define bfd_mach_arc_5 5
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#define bfd_mach_arc_6 6
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@ -3605,6 +3607,72 @@ bits placed non-contiguously in the instruction. */
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instructions. */
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BFD_RELOC_V850_LO16_SPLIT_OFFSET,
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/* This is a 16-bit reloc. */
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BFD_RELOC_V850_16_PCREL,
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/* This is a 17-bit reloc. */
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BFD_RELOC_V850_17_PCREL,
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/* This is a 23-bit reloc. */
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BFD_RELOC_V850_23,
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/* This is a 32-bit reloc. */
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BFD_RELOC_V850_32_PCREL,
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/* This is a 32-bit reloc. */
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BFD_RELOC_V850_32_ABS,
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/* This is a 16-bit reloc. */
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BFD_RELOC_V850_16_SPLIT_OFFSET,
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/* This is a 16-bit reloc. */
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BFD_RELOC_V850_16_S1,
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/* Low 16 bits. 16 bit shifted by 1. */
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BFD_RELOC_V850_LO16_S1,
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/* This is a 16 bit offset from the call table base pointer. */
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BFD_RELOC_V850_CALLT_15_16_OFFSET,
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/* DSO relocations. */
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BFD_RELOC_V850_32_GOTPCREL,
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/* DSO relocations. */
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BFD_RELOC_V850_16_GOT,
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/* DSO relocations. */
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BFD_RELOC_V850_32_GOT,
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/* DSO relocations. */
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BFD_RELOC_V850_22_PLT_PCREL,
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/* DSO relocations. */
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BFD_RELOC_V850_32_PLT_PCREL,
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/* DSO relocations. */
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BFD_RELOC_V850_COPY,
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/* DSO relocations. */
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BFD_RELOC_V850_GLOB_DAT,
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/* DSO relocations. */
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BFD_RELOC_V850_JMP_SLOT,
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/* DSO relocations. */
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BFD_RELOC_V850_RELATIVE,
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/* DSO relocations. */
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BFD_RELOC_V850_16_GOTOFF,
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/* DSO relocations. */
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BFD_RELOC_V850_32_GOTOFF,
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/* start code. */
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BFD_RELOC_V850_CODE,
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/* start data in text. */
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BFD_RELOC_V850_DATA,
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/* This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
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instruction. */
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BFD_RELOC_MN10300_32_PCREL,
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@ -1468,13 +1468,7 @@ case "${targ}" in
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targ_underscore=yes
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;;
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v850-*-*)
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targ_defvec=bfd_elf32_v850_vec
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;;
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v850e-*-*)
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targ_defvec=bfd_elf32_v850_vec
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;;
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v850ea-*-*)
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v850*-*-*)
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targ_defvec=bfd_elf32_v850_vec
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;;
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@ -1,6 +1,6 @@
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/* BFD support for the NEC V850 processor
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Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007
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Free Software Foundation, Inc.
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Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007,
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2010 Free Software Foundation, Inc.
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This file is part of BFD, the Binary File Descriptor library.
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@ -32,8 +32,10 @@
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static const bfd_arch_info_type arch_info_struct[] =
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{
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N (bfd_mach_v850e1, "v850e1", FALSE, & arch_info_struct[1]),
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N (bfd_mach_v850e, "v850e", FALSE, NULL)
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N (bfd_mach_v850e2v3, "v850e2v3", FALSE, & arch_info_struct[1]),
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N (bfd_mach_v850e2, "v850e2", FALSE, & arch_info_struct[2]),
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N (bfd_mach_v850e1, "v850e1", FALSE, & arch_info_struct[3]),
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N (bfd_mach_v850e, "v850e", FALSE, NULL)
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};
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#undef NEXT
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768
bfd/elf32-v850.c
768
bfd/elf32-v850.c
File diff suppressed because it is too large
Load diff
22
bfd/libbfd.h
22
bfd/libbfd.h
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@ -1636,6 +1636,28 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
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"BFD_RELOC_V850_LONGJUMP",
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"BFD_RELOC_V850_ALIGN",
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"BFD_RELOC_V850_LO16_SPLIT_OFFSET",
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"BFD_RELOC_V850_16_PCREL",
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"BFD_RELOC_V850_17_PCREL",
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"BFD_RELOC_V850_23",
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"BFD_RELOC_V850_32_PCREL",
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"BFD_RELOC_V850_32_ABS",
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"BFD_RELOC_V850_16_SPLIT_OFFSET",
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"BFD_RELOC_V850_16_S1",
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"BFD_RELOC_V850_LO16_S1",
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"BFD_RELOC_V850_CALLT_15_16_OFFSET",
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"BFD_RELOC_V850_32_GOTPCREL",
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"BFD_RELOC_V850_16_GOT",
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"BFD_RELOC_V850_32_GOT",
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"BFD_RELOC_V850_22_PLT_PCREL",
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"BFD_RELOC_V850_32_PLT_PCREL",
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"BFD_RELOC_V850_COPY",
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"BFD_RELOC_V850_GLOB_DAT",
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"BFD_RELOC_V850_JMP_SLOT",
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"BFD_RELOC_V850_RELATIVE",
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"BFD_RELOC_V850_16_GOTOFF",
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"BFD_RELOC_V850_32_GOTOFF",
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"BFD_RELOC_V850_CODE",
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"BFD_RELOC_V850_DATA",
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"BFD_RELOC_MN10300_32_PCREL",
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"BFD_RELOC_MN10300_16_PCREL",
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"BFD_RELOC_TIC30_LDP",
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88
bfd/reloc.c
88
bfd/reloc.c
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@ -3722,6 +3722,94 @@ ENUM
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ENUMDOC
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This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
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instructions.
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ENUM
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BFD_RELOC_V850_16_PCREL
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ENUMDOC
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This is a 16-bit reloc.
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ENUM
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BFD_RELOC_V850_17_PCREL
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ENUMDOC
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This is a 17-bit reloc.
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ENUM
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BFD_RELOC_V850_23
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ENUMDOC
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This is a 23-bit reloc.
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ENUM
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BFD_RELOC_V850_32_PCREL
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ENUMDOC
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This is a 32-bit reloc.
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ENUM
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BFD_RELOC_V850_32_ABS
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ENUMDOC
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This is a 32-bit reloc.
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ENUM
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BFD_RELOC_V850_16_SPLIT_OFFSET
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ENUMDOC
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This is a 16-bit reloc.
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ENUM
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BFD_RELOC_V850_16_S1
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ENUMDOC
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This is a 16-bit reloc.
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ENUM
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BFD_RELOC_V850_LO16_S1
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ENUMDOC
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Low 16 bits. 16 bit shifted by 1.
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ENUM
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BFD_RELOC_V850_CALLT_15_16_OFFSET
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ENUMDOC
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This is a 16 bit offset from the call table base pointer.
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ENUM
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BFD_RELOC_V850_32_GOTPCREL
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ENUMDOC
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DSO relocations.
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ENUM
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BFD_RELOC_V850_16_GOT
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ENUMDOC
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DSO relocations.
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ENUM
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BFD_RELOC_V850_32_GOT
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ENUMDOC
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DSO relocations.
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ENUM
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BFD_RELOC_V850_22_PLT_PCREL
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ENUMDOC
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DSO relocations.
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ENUM
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BFD_RELOC_V850_32_PLT_PCREL
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ENUMDOC
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DSO relocations.
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ENUM
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BFD_RELOC_V850_COPY
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ENUMDOC
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DSO relocations.
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ENUM
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BFD_RELOC_V850_GLOB_DAT
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ENUMDOC
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DSO relocations.
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ENUM
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BFD_RELOC_V850_JMP_SLOT
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ENUMDOC
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DSO relocations.
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ENUM
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BFD_RELOC_V850_RELATIVE
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ENUMDOC
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DSO relocations.
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ENUM
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BFD_RELOC_V850_16_GOTOFF
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ENUMDOC
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DSO relocations.
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ENUM
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BFD_RELOC_V850_32_GOTOFF
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ENUMDOC
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DSO relocations.
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ENUM
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BFD_RELOC_V850_CODE
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ENUMDOC
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start code.
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ENUM
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BFD_RELOC_V850_DATA
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ENUMDOC
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start data in text.
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ENUM
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BFD_RELOC_MN10300_32_PCREL
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ENUMDOC
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@ -1,3 +1,8 @@
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2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
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Ina Pandit <ina.pandit@kpitcummins.com>
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* binutils/readelf.c: Add support for V850E2 and V850E2V3.
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2010-07-22 Alan Modra <amodra@gmail.com>
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* readelf.c: Add Moxie support.
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@ -2352,8 +2352,14 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
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case EM_CYGNUS_V850:
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switch (e_flags & EF_V850_ARCH)
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{
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case E_V850E1_ARCH:
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strcat (buf, ", v850e1");
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case E_V850E2V3_ARCH:
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strcat (buf, ", v850e2v3");
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break;
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case E_V850E2_ARCH:
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strcat (buf, ", v850e2");
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break;
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case E_V850E1_ARCH:
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strcat (buf, ", v850e1");
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break;
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case E_V850E_ARCH:
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strcat (buf, ", v850e");
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10
configure
vendored
10
configure
vendored
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@ -3730,14 +3730,8 @@ case "${target}" in
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v810-*-*)
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noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
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;;
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v850-*-*)
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noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
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;;
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v850e-*-*)
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noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
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;;
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v850ea-*-*)
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noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
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v850*-*-*)
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noconfigdirs="$noconfigdirs ${libgcj}"
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;;
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vax-*-vms)
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noconfigdirs="$noconfigdirs bfd binutils gdb ld target-newlib opcodes target-libgloss ${libgcj}"
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10
configure.ac
10
configure.ac
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@ -967,14 +967,8 @@ case "${target}" in
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v810-*-*)
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noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
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;;
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v850-*-*)
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noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
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;;
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v850e-*-*)
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noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
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;;
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v850ea-*-*)
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noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
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v850*-*-*)
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noconfigdirs="$noconfigdirs ${libgcj}"
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;;
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vax-*-vms)
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noconfigdirs="$noconfigdirs bfd binutils gdb ld target-newlib opcodes target-libgloss ${libgcj}"
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@ -1,3 +1,50 @@
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2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
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Ina Pandit <ina.pandit@kpitcummins.com>
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* config/tc-v850.c: Update processor_mask.
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(reg_name): Update the structure to use processors field.
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(md_relax_table): Define SUBYPTE_COND_9_22, SUBYPTE_SA_9_22,
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SUBYPTE_UNCOND_9_22, SUBYPTE_COND_9_22_32, SUBYPTE_SA_9_22_32,
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SUBYPTE_UNCOND_9_22_32, SUBYPTE_COND_9_17_22,
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SUBYPTE_SA_9_17_22, SUBYPTE_COND_9_17_22_32 and
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SUBYPTE_SA_9_17_22_32.
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(set_machine): Add support for V850E2 and V850E2V3.
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(md_pseudo_table): Likewise.
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(pre_defined_registers): Update pre defined registers suitable
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for each family of registers.
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(system_registers): Likewise.
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(cc_names): Update the condition code.
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(float_cc_names): Update the condition code for float.
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(reg_name_search): Update based on current modifications.
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(register_name): Likewise.
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(system_register_name): Update to support new system registers
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and supported families.
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(cc_name): Update to support new condition codes.
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(float_cc_name): New function to support float condition codes.
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(parse_register_list): Update to support newly added registers.
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(md_show_usage): Define support for V850E2 and V850E2V3 targets.
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Also support added for disp-size-default-22, disp-size-default-32,
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mextension, mno-bcond17 and mno-stld23.
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(md_parse_option): Implement the support for above options defined
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in md_show-usage.
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(md_convert_frag): Implement support for subtypes defined in
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md_relax_table to support branch operations.
|
||||
(md_begin): Add support for V850E2 and V850E2V3.
|
||||
(handle_hi016, handle_hi16): new relocation handling functions
|
||||
(handle_lo16, handle_ctoff, handle_sdaoff, handle_zdaoff,
|
||||
handle_tdaoff): Updated relocation handling functions for newly
|
||||
added relocations.
|
||||
(v850_reloc_prefix): Update the relocation handling functions.
|
||||
(v850_insert_operand): Updated the functions with error message
|
||||
parameter and modified the function to use it.
|
||||
(md_assemble): Update according to the latest modifications.
|
||||
(md_apply_fix): Updated the functions with error message parameter
|
||||
and modified the function to use it.
|
||||
(v850_force_relocation): Update with newly added relocations.
|
||||
* configure.tgt: Match all v850 targets.
|
||||
* doc/c-v850.texi: Document the newly added targets.
|
||||
* NEWS: Likewise.
|
||||
|
||||
2010-07-23 Alan Modra <amodra@gmail.com>
|
||||
|
||||
PR gas/11834
|
||||
|
|
|
|||
2
gas/NEWS
2
gas/NEWS
|
|
@ -16,6 +16,8 @@
|
|||
|
||||
Changes in 2.20:
|
||||
|
||||
* Added support for v850e2 and v850e2v3.
|
||||
|
||||
* GNU/Linux targets now supports "gnu_unique_object" as a value in the .type
|
||||
pseudo op. It marks the symbol as being globally unique in the entire
|
||||
process.
|
||||
|
|
|
|||
1952
gas/config/tc-v850.c
1952
gas/config/tc-v850.c
File diff suppressed because it is too large
Load diff
|
|
@ -400,9 +400,7 @@ case ${generic_target} in
|
|||
tic54x-*-* | c54x*-*-*) fmt=coff bfd_gas=yes need_libm=yes;;
|
||||
tic6x-*-*) fmt=elf ;;
|
||||
|
||||
v850-*-*) fmt=elf ;;
|
||||
v850e-*-*) fmt=elf ;;
|
||||
v850ea-*-*) fmt=elf ;;
|
||||
v850*-*-*) fmt=elf ;;
|
||||
|
||||
vax-*-netbsdelf*) fmt=elf em=nbsd ;;
|
||||
vax-*-linux-*) fmt=elf em=linux ;;
|
||||
|
|
|
|||
|
|
@ -68,6 +68,18 @@ routines used by the code produced by GCC for all versions of the v850
|
|||
architecture, together with support routines only used by the V850E
|
||||
architecture.
|
||||
|
||||
@cindex @code{-mv850e2} command line option, V850
|
||||
@item -mv850e2
|
||||
Specifies that the assembled code should be marked as being targeted at
|
||||
the V850E2 processor. This allows the linker to detect attempts to link
|
||||
such code with code assembled for other processors.
|
||||
|
||||
@cindex @code{-mv850e2v3} command line option, V850
|
||||
@item -mv850e2v3
|
||||
Specifies that the assembled code should be marked as being targeted at
|
||||
the V850E2V3 processor. This allows the linker to detect attempts to link
|
||||
such code with code assembled for other processors.
|
||||
|
||||
@cindex @code{-mrelax} command line option, V850
|
||||
@item -mrelax
|
||||
Enables relaxation. This allows the .longcall and .longjump pseudo
|
||||
|
|
@ -245,6 +257,18 @@ Specifies that the assembled code should be marked as being targeted at
|
|||
the V850E1 processor. This allows the linker to detect attempts to link
|
||||
such code with code assembled for other processors.
|
||||
|
||||
@cindex @code{.v850e2} directive, V850
|
||||
@item .v850e2
|
||||
Specifies that the assembled code should be marked as being targeted at
|
||||
the V850E2 processor. This allows the linker to detect attempts to link
|
||||
such code with code assembled for other processors.
|
||||
|
||||
@cindex @code{.v850e2v3} directive, V850
|
||||
@item .v850e2v3
|
||||
Specifies that the assembled code should be marked as being targeted at
|
||||
the V850E2V3 processor. This allows the linker to detect attempts to link
|
||||
such code with code assembled for other processors.
|
||||
|
||||
@end table
|
||||
|
||||
@node V850 Opcodes
|
||||
|
|
|
|||
|
|
@ -1,3 +1,10 @@
|
|||
2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
|
||||
Ina Pandit <ina.pandit@kpitcummins.com>
|
||||
|
||||
* gas/v850/split-lo16.d: Update the "ld" instructions with a space
|
||||
for second operand.
|
||||
* gas/v850/v850e1.d: Likewise.
|
||||
|
||||
2010-07-22 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* gas/arm/mapdir.s: Don't specify attr/type for .fini_array.
|
||||
|
|
|
|||
|
|
@ -1,2 +1,5 @@
|
|||
#name: bad byte directive
|
||||
#error-output: byte.l
|
||||
# The RX target allows quoted ASCII strings inside .byte directives
|
||||
# for compatibily with the Renesas assembler.
|
||||
#skip: rx-*-*
|
||||
|
|
|
|||
|
|
@ -10,8 +10,8 @@ Disassembly of section .text:
|
|||
0+0108 <mem\+0x8> 66 20[ ]+mov.l[ ]+#2, r0
|
||||
0+010a <mem\+0xa> 66 10[ ]+mov.l[ ]+#1, r0
|
||||
0+010c <mem\+0xc> 66 00[ ]+mov.l[ ]+#0, r0
|
||||
0+010e <mem\+0xe> 05 f2 fe ff[ ]+bsr.a[ ]+0+0000 <mem-0x100>
|
||||
0+0112 <mem\+0x12> 05 ee fe ff[ ]+bsr.a[ ]+0+0000 <mem-0x100>
|
||||
0+010e <mem\+0xe> 05 .. .. ..[ ]+bsr.a[ ]+[0-9a-f]+ <mem.0x[0-9a-f]+>
|
||||
0+0112 <mem\+0x12> 05 .. .. ..[ ]+bsr.a[ ]+[0-9a-f]+ <mem.0x[0-9a-f]+>
|
||||
0+0116 <mem\+0x16> 62 65[ ]+add[ ]+#6, r5
|
||||
0+0118 <mem\+0x18> 72 74 0b 2e[ ]+add[ ]+#0x2e0b, r7, r4
|
||||
0+011c <mem\+0x1c> ff 2e 00[ ]+add[ ]+r0, r0, r14
|
||||
|
|
|
|||
|
|
@ -7,12 +7,12 @@
|
|||
2: R_V850_HI16_S foo
|
||||
4: 01 16 00 00 addi 0, r1, r2
|
||||
6: R_V850_LO16 foo
|
||||
8: 01 17 00 00 ld\.b 0\[r1\],r2
|
||||
8: 01 17 00 00 ld\.b 0\[r1\], r2
|
||||
a: R_V850_LO16 foo
|
||||
c: 81 17 01 00 ld\.bu 0\[r1\],r2
|
||||
c: 81 17 01 00 ld\.bu 0\[r1\], r2
|
||||
c: R_V850_LO16_SPLIT_OFFSET foo
|
||||
10: a1 17 45 23 ld\.bu 9029\[r1\],r2
|
||||
14: 81 17 57 34 ld\.bu 13398\[r1\],r2
|
||||
18: 20 57 01 00 ld.w 0\[r0\],r10
|
||||
1c: 20 57 79 56 ld.w 22136\[r0\],r10
|
||||
10: a1 17 45 23 ld\.bu 9029\[r1\], r2
|
||||
14: 81 17 57 34 ld\.bu 13398\[r1\], r2
|
||||
18: 20 57 01 00 ld.w 0\[r0\], r10
|
||||
1c: 20 57 79 56 ld.w 22136\[r0\], r10
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -23,8 +23,8 @@ Disassembly of section .text:
|
|||
0x0+30 e7 47 82 4a [ ]*divhu r7, r8, r9
|
||||
0x0+34 ea 5f c2 62 [ ]*divu r10, r11, r12
|
||||
0x0+38 e0 6f 44 73 [ ]*hsw r13, r14
|
||||
0x0+3c a1 17 0d 00 [ ]*ld.bu 13\[r1\],r2
|
||||
0x0+40 e3 27 11 00 [ ]*ld.hu 16\[sp\],gp
|
||||
0x0+3c a1 17 0d 00 [ ]*ld.bu 13\[r1\], r2
|
||||
0x0+40 e3 27 11 00 [ ]*ld.hu 16\[sp\], gp
|
||||
0x0+44 21 06 78 56 34 12 [ ]*mov 0x12345678, r1
|
||||
0x0+4a e5 17 40 1a [ ]*mul 5, r2, sp
|
||||
0x0+4e e1 17 20 1a [ ]*mul r1, r2, sp
|
||||
|
|
@ -35,8 +35,8 @@ Disassembly of section .text:
|
|||
0x0+62 a8 07 03 70 [ ]*prepare {r25 - r27}, 20, sp
|
||||
0x0+66 e1 4f e0 00 [ ]*set1 r9, r1
|
||||
0x0+6a ea 47 00 02 [ ]*sasf nz, r8
|
||||
0x0+6e 60 20 [ ]*sld.bu 0\[ep\],gp
|
||||
0x0+70 77 28 [ ]*sld.hu 14\[ep\],r5
|
||||
0x0+6e 60 20 [ ]*sld.bu 0\[ep\], gp
|
||||
0x0+70 77 28 [ ]*sld.hu 14\[ep\], r5
|
||||
0x0+72 a1 00 [ ]*sxb r1
|
||||
0x0+74 e2 00 [ ]*sxh r2
|
||||
0x0+76 ff 07 e6 00 [ ]*tst1 r0, lp
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
|
||||
Ina Pandit <ina.pandit@kpitcummins.com>
|
||||
|
||||
* v850.h: Add support for V850E2 and V850E2V3.
|
||||
(v850_reloc_type): Update the newly added relocations
|
||||
|
||||
2010-07-20 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* internal.h (ELF_TBSS_SPECIAL): New macro, extracted from..
|
||||
|
|
|
|||
|
|
@ -40,6 +40,11 @@
|
|||
/* v850e1 code. */
|
||||
#define E_V850E1_ARCH 0x20000000
|
||||
|
||||
/* v850e2 code. */
|
||||
#define E_V850E2_ARCH 0x30000000
|
||||
|
||||
/* v850e2v3 code. */
|
||||
#define E_V850E2V3_ARCH 0x40000000
|
||||
|
||||
/* Flags for the st_other field. */
|
||||
#define V850_OTHER_SDA 0x10 /* Symbol had SDA relocations. */
|
||||
|
|
@ -81,6 +86,29 @@ START_RELOC_NUMBERS (v850_reloc_type)
|
|||
RELOC_NUMBER (R_V850_ALIGN, 27)
|
||||
RELOC_NUMBER (R_V850_REL32, 28)
|
||||
RELOC_NUMBER (R_V850_LO16_SPLIT_OFFSET, 29) /* For ld.bu */
|
||||
RELOC_NUMBER (R_V850_16_PCREL, 30) /* For loop */
|
||||
RELOC_NUMBER (R_V850_17_PCREL, 31) /* For br */
|
||||
RELOC_NUMBER (R_V850_23, 32) /* For 23bit ld.[w,h,hu,b,bu],st.[w,h,b] */
|
||||
RELOC_NUMBER (R_V850_32_PCREL, 33) /* For jr32, jarl32 */
|
||||
RELOC_NUMBER (R_V850_32_ABS, 34) /* For jmp32 */
|
||||
RELOC_NUMBER (R_V850_16_SPLIT_OFFSET, 35) /* For ld.bu */
|
||||
RELOC_NUMBER (R_V850_16_S1, 36) /* For ld.w, ld.h st.w st.h */
|
||||
RELOC_NUMBER (R_V850_LO16_S1, 37) /* For ld.w, ld.h st.w st.h */
|
||||
RELOC_NUMBER (R_V850_CALLT_15_16_OFFSET, 38) /* For ld.w, ld.h, ld.hu, st.w, st.h */
|
||||
RELOC_NUMBER (R_V850_32_GOTPCREL, 39) /* GLOBAL_OFFSET_TABLE from pc */
|
||||
RELOC_NUMBER (R_V850_16_GOT, 40) /* GOT ENTRY from gp */
|
||||
RELOC_NUMBER (R_V850_32_GOT, 41)
|
||||
RELOC_NUMBER (R_V850_22_PLT, 42) /* For jr */
|
||||
RELOC_NUMBER (R_V850_32_PLT, 43) /* For jr32 */
|
||||
RELOC_NUMBER (R_V850_COPY, 44)
|
||||
RELOC_NUMBER (R_V850_GLOB_DAT, 45)
|
||||
RELOC_NUMBER (R_V850_JMP_SLOT, 46)
|
||||
RELOC_NUMBER (R_V850_RELATIVE, 47)
|
||||
RELOC_NUMBER (R_V850_16_GOTOFF, 48) /* From gp */
|
||||
RELOC_NUMBER (R_V850_32_GOTOFF, 49)
|
||||
RELOC_NUMBER (R_V850_CODE, 50)
|
||||
RELOC_NUMBER (R_V850_DATA, 51) /* For loop */
|
||||
|
||||
END_RELOC_NUMBERS (R_V850_max)
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,21 @@
|
|||
2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
|
||||
Ina Pandit <ina.pandit@kpitcummins.com>
|
||||
|
||||
* v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
|
||||
PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
|
||||
PROCESSOR_V850E2_ALL.
|
||||
Remove PROCESSOR_V850EA support.
|
||||
(v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
|
||||
V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
|
||||
V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
|
||||
V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
|
||||
V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
|
||||
V850_OPERAND_PERCENT.
|
||||
Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
|
||||
V850_NOT_R0.
|
||||
Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
|
||||
and V850E_PUSH_POP
|
||||
|
||||
2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
|
||||
|
||||
* mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
|
||||
|
|
|
|||
|
|
@ -55,12 +55,18 @@ struct v850_opcode
|
|||
};
|
||||
|
||||
/* Values for the processors field in the v850_opcode structure. */
|
||||
#define PROCESSOR_MASK 0x1f
|
||||
#define PROCESSOR_OPTION_EXTENSION (1 << 5) /* Enable extension opcodes. */
|
||||
#define PROCESSOR_OPTION_ALIAS (1 << 6) /* Enable alias opcodes. */
|
||||
#define PROCESSOR_V850 (1 << 0) /* Just the V850. */
|
||||
#define PROCESSOR_ALL -1 /* Any processor. */
|
||||
#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */
|
||||
#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */
|
||||
#define PROCESSOR_V850EA (1 << 2) /* Just the V850EA. */
|
||||
#define PROCESSOR_V850E1 (1 << 3) /* Just the V850E1. */
|
||||
#define PROCESSOR_ALL PROCESSOR_MASK /* Any processor. */
|
||||
#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */
|
||||
#define PROCESSOR_NOT_V850 (PROCESSOR_ALL & (~ PROCESSOR_V850)) /* Any processor except the V850. */
|
||||
#define PROCESSOR_V850E1 (1 << 2) /* Just the V850E1. */
|
||||
#define PROCESSOR_V850E2 (1 << 3) /* Just the V850E2. */
|
||||
#define PROCESSOR_V850E2V3 (1 << 4) /* Just the V850E2V3. */
|
||||
#define PROCESSOR_V850E2_ALL (PROCESSOR_V850E2 | PROCESSOR_V850E2V3) /* V850E2 & V850E2V3. */
|
||||
#define SET_PROCESSOR_MASK(mask,set) ((mask) = ((mask) & ~PROCESSOR_MASK) | (set))
|
||||
|
||||
/* The table itself is sorted by major opcode number, and is otherwise
|
||||
in the order in which the disassembler should consider
|
||||
|
|
@ -74,7 +80,8 @@ extern const int v850_num_opcodes;
|
|||
struct v850_operand
|
||||
{
|
||||
/* The number of bits in the operand. */
|
||||
/* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */
|
||||
/* If this value is -1 then the operand's bits are in a discontinous
|
||||
distribution in the instruction. */
|
||||
int bits;
|
||||
|
||||
/* (bits >= 0): How far the operand is left shifted in the instruction. */
|
||||
|
|
@ -120,6 +127,8 @@ struct v850_operand
|
|||
|
||||
/* One bit syntax flags. */
|
||||
int flags;
|
||||
|
||||
int default_reloc;
|
||||
};
|
||||
|
||||
/* Elements in the table are retrieved by indexing with values from
|
||||
|
|
@ -129,39 +138,70 @@ extern const struct v850_operand v850_operands[];
|
|||
|
||||
/* Values defined for the flags field of a struct v850_operand. */
|
||||
|
||||
/* This operand names a general purpose register */
|
||||
/* This operand names a general purpose register. */
|
||||
#define V850_OPERAND_REG 0x01
|
||||
|
||||
/* This operand names a system register */
|
||||
#define V850_OPERAND_SRG 0x02
|
||||
|
||||
/* This operand names a condition code used in the setf instruction */
|
||||
#define V850_OPERAND_CC 0x04
|
||||
|
||||
/* This operand takes signed values */
|
||||
#define V850_OPERAND_SIGNED 0x08
|
||||
|
||||
/* This operand is the ep register. */
|
||||
#define V850_OPERAND_EP 0x10
|
||||
#define V850_OPERAND_EP 0x02
|
||||
|
||||
/* This operand is a PC displacement */
|
||||
#define V850_OPERAND_DISP 0x20
|
||||
/* This operand names a system register. */
|
||||
#define V850_OPERAND_SRG 0x04
|
||||
|
||||
/* This is a relaxable operand. Only used for D9->D22 branch relaxing
|
||||
right now. We may need others in the future (or maybe handle them like
|
||||
promoted operands on the mn10300?) */
|
||||
#define V850_OPERAND_RELAX 0x40
|
||||
/* Prologue eilogue type instruction, V850E specific. */
|
||||
#define V850E_OPERAND_REG_LIST 0x08
|
||||
|
||||
/* The register specified must not be r0 */
|
||||
#define V850_NOT_R0 0x80
|
||||
/* This operand names a condition code used in the setf instruction. */
|
||||
#define V850_OPERAND_CC 0x10
|
||||
|
||||
/* push/pop type instruction, V850E specific. */
|
||||
#define V850E_PUSH_POP 0x100
|
||||
#define V850_OPERAND_FLOAT_CC 0x20
|
||||
|
||||
/* This operand names a vector purpose register. */
|
||||
#define V850_OPERAND_VREG 0x40
|
||||
|
||||
/* 16 bit immediate follows instruction, V850E specific. */
|
||||
#define V850E_IMMEDIATE16 0x200
|
||||
#define V850E_IMMEDIATE16 0x80
|
||||
|
||||
/* hi16 bit immediate follows instruction, V850E specific. */
|
||||
#define V850E_IMMEDIATE16HI 0x100
|
||||
|
||||
/* 23 bit immediate follows instruction, V850E specific. */
|
||||
#define V850E_IMMEDIATE23 0x200
|
||||
|
||||
/* 32 bit immediate follows instruction, V850E specific. */
|
||||
#define V850E_IMMEDIATE32 0x400
|
||||
|
||||
/* This is a relaxable operand. Only used for D9->D22 branch relaxing
|
||||
right now. We may need others in the future (or maybe handle them like
|
||||
promoted operands on the mn10300?). */
|
||||
#define V850_OPERAND_RELAX 0x800
|
||||
|
||||
/* This operand takes signed values. */
|
||||
#define V850_OPERAND_SIGNED 0x1000
|
||||
|
||||
/* This operand is a displacement. */
|
||||
#define V850_OPERAND_DISP 0x2000
|
||||
|
||||
/* This operand is a PC displacement. */
|
||||
#define V850_PCREL 0x4000
|
||||
|
||||
/* The register specified must be even number. */
|
||||
#define V850_REG_EVEN 0x8000
|
||||
|
||||
/* The register specified must not be r0. */
|
||||
#define V850_NOT_R0 0x20000
|
||||
|
||||
/* The register specified must not be 0. */
|
||||
#define V850_NOT_IMM0 0x40000
|
||||
|
||||
/* The condition code must not be SA CONDITION. */
|
||||
#define V850_NOT_SA 0x80000
|
||||
|
||||
/* The operand has '!' prefix. */
|
||||
#define V850_OPERAND_BANG 0x100000
|
||||
|
||||
/* The operand has '%' prefix. */
|
||||
#define V850_OPERAND_PERCENT 0x200000
|
||||
|
||||
extern int v850_msg_is_out_of_range (const char * msg);
|
||||
|
||||
#endif /* V850_H */
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
|
||||
Ina Pandit <ina.pandit@kpitcummins.com>
|
||||
|
||||
* configure.tgt: Match all v850 targets.
|
||||
|
||||
2010-07-20 Mike Frysinger <vapier@gentoo.org>
|
||||
|
||||
* ld.texinfo (VERSION): Remove "int" from example script and add ";".
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
|
||||
Ina Pandit <ina.pandit@kpitcummins.com>
|
||||
|
||||
* ld-v850/split-lo16.d: Update the "ld" instructions with a space
|
||||
for second operand.
|
||||
|
||||
2010-07-20 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* ld-powerpc/tlsexe.r: Update.
|
||||
|
|
|
|||
|
|
@ -5,22 +5,22 @@
|
|||
00010000 <.*>:
|
||||
10000: 40 0e 34 12 movhi 4660, r0, r1
|
||||
10004: 01 16 78 56 addi 22136, r1, r2
|
||||
10008: 81 17 79 56 ld\.bu 22136\[r1\],r2
|
||||
10008: 81 17 79 56 ld\.bu 22136\[r1\], r2
|
||||
1000c: 40 0e 36 12 movhi 4662, r0, r1
|
||||
10010: 01 16 78 d8 addi -10120, r1, r2
|
||||
10014: 81 17 79 d8 ld\.bu -10120\[r1\],r2
|
||||
10014: 81 17 79 d8 ld\.bu -10120\[r1\], r2
|
||||
10018: 40 0e 12 00 movhi 18, r0, r1
|
||||
1001c: 81 17 57 34 ld\.bu 13398\[r1\],r2
|
||||
1001c: 81 17 57 34 ld\.bu 13398\[r1\], r2
|
||||
10020: 01 16 56 34 addi 13398, r1, r2
|
||||
10024: 40 0e 14 00 movhi 20, r0, r1
|
||||
10028: 81 17 57 b6 ld\.bu -18858\[r1\],r2
|
||||
10028: 81 17 57 b6 ld\.bu -18858\[r1\], r2
|
||||
1002c: 01 16 56 b6 addi -18858, r1, r2
|
||||
10030: 40 0e 79 56 movhi 22137, r0, r1
|
||||
10034: 01 16 bc 9a addi -25924, r1, r2
|
||||
10038: 81 17 bd 9a ld\.bu -25924\[r1\],r2
|
||||
10038: 81 17 bd 9a ld\.bu -25924\[r1\], r2
|
||||
1003c: 40 0e 9b 78 movhi 30875, r0, r1
|
||||
10040: 81 17 df bc ld\.bu -17186\[r1\],r2
|
||||
10040: 81 17 df bc ld\.bu -17186\[r1\], r2
|
||||
10044: 01 16 de bc addi -17186, r1, r2
|
||||
10048: 40 0e 45 23 movhi 9029, r0, r1
|
||||
1004c: a1 17 89 67 ld\.bu 26505\[r1\],r2
|
||||
1004c: a1 17 89 67 ld\.bu 26505\[r1\], r2
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -1,3 +1,26 @@
|
|||
2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
|
||||
Ina Pandit <ina.pandit@kpitcummins.com>
|
||||
|
||||
* v850-dis.c (v850_sreg_names): Updated structure for system
|
||||
registers.
|
||||
(float_cc_names): new structure for condition codes.
|
||||
(print_value): Update the function that prints value.
|
||||
(get_operand_value): New function to get the operand value.
|
||||
(disassemble): Updated to handle the disassembly of instructions.
|
||||
(print_insn_v850): Updated function to print instruction for different
|
||||
families.
|
||||
* opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
|
||||
extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
|
||||
extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
|
||||
insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
|
||||
extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
|
||||
extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
|
||||
extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
|
||||
insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
|
||||
(insert_d8_7, insert_d5_4, insert_i5div): Remove.
|
||||
(v850_operands): Update with the relocation name. Also update
|
||||
the instructions with specific set of processors.
|
||||
|
||||
2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
|
||||
|
||||
* arm-dis.c (print_insn_arm): Add cases for printing more
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* Disassemble V850 instructions.
|
||||
Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007
|
||||
Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007, 2010
|
||||
Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU opcodes library.
|
||||
|
|
@ -28,45 +28,170 @@
|
|||
#include "opintl.h"
|
||||
|
||||
static const char *const v850_reg_names[] =
|
||||
{ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7",
|
||||
{
|
||||
"r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7",
|
||||
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
|
||||
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
|
||||
"r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp" };
|
||||
"r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp"
|
||||
};
|
||||
|
||||
static const char *const v850_sreg_names[] =
|
||||
{ "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
|
||||
"sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
|
||||
"ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23",
|
||||
"sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
|
||||
"sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23",
|
||||
"sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31" };
|
||||
{
|
||||
"eipc/vip/mpm", "eipsw/mpc", "fepc/tid", "fepsw/ppa", "ecr/vmecr", "psw/vmtid",
|
||||
"sr6/fpsr/vmadr/dcc", "sr7/fpepc/dc0",
|
||||
"sr8/fpst/vpecr/dcv1", "sr9/fpcc/vptid", "sr10/fpcfg/vpadr/spal", "sr11/spau",
|
||||
"sr12/vdecr/ipa0l", "eiic/vdtid/ipa0u", "feic/ipa1l", "dbic/ipa1u",
|
||||
"ctpc/ipa2l", "ctpsw/ipa2u", "dbpc/ipa3l", "dbpsw/ipa3u", "ctbp/dpa0l",
|
||||
"dir/dpa0u", "bpc/dpa0u", "asid/dpa1l",
|
||||
"bpav/dpa1u", "bpam/dpa2l", "bpdv/dpa2u", "bpdm/dpa3l", "eiwr/dpa3u",
|
||||
"fewr", "dbwr", "bsel"
|
||||
};
|
||||
|
||||
static const char *const v850_cc_names[] =
|
||||
{ "v", "c/l", "z", "nh", "s/n", "t", "lt", "le",
|
||||
"nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt" };
|
||||
{
|
||||
"v", "c/l", "z", "nh", "s/n", "t", "lt", "le",
|
||||
"nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt"
|
||||
};
|
||||
|
||||
static const char *const v850_float_cc_names[] =
|
||||
{
|
||||
"f/t", "un/or", "eq/neq", "ueq/ogl", "olt/uge", "ult/oge", "ole/ugt", "ule/ogt",
|
||||
"sf/st", "ngle/gle", "seq/sne", "ngl/gl", "lt/nlt", "nge/ge", "le/nle", "ngt/gt"
|
||||
};
|
||||
|
||||
|
||||
static void
|
||||
print_value (int flags, bfd_vma memaddr, struct disassemble_info *info, long value)
|
||||
{
|
||||
if (flags & V850_PCREL)
|
||||
{
|
||||
bfd_vma addr = value + memaddr;
|
||||
info->print_address_func (addr, info);
|
||||
}
|
||||
else if (flags & V850_OPERAND_DISP)
|
||||
{
|
||||
if (flags & V850_OPERAND_SIGNED)
|
||||
{
|
||||
info->fprintf_func (info->stream, "%ld", value);
|
||||
}
|
||||
else
|
||||
{
|
||||
info->fprintf_func (info->stream, "%lu", value);
|
||||
}
|
||||
}
|
||||
else if (flags & V850E_IMMEDIATE32)
|
||||
{
|
||||
info->fprintf_func (info->stream, "0x%lx", value);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (flags & V850_OPERAND_SIGNED)
|
||||
{
|
||||
info->fprintf_func (info->stream, "%ld", value);
|
||||
}
|
||||
else
|
||||
{
|
||||
info->fprintf_func (info->stream, "%lu", value);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static long
|
||||
get_operand_value (const struct v850_operand *operand,
|
||||
unsigned long insn,
|
||||
int bytes_read,
|
||||
bfd_vma memaddr,
|
||||
struct disassemble_info * info,
|
||||
bfd_boolean noerror,
|
||||
int *invalid)
|
||||
{
|
||||
long value;
|
||||
bfd_byte buffer[4];
|
||||
|
||||
if ((operand->flags & V850E_IMMEDIATE16)
|
||||
|| (operand->flags & V850E_IMMEDIATE16HI))
|
||||
{
|
||||
int status = info->read_memory_func (memaddr + bytes_read, buffer, 2, info);
|
||||
|
||||
if (status == 0)
|
||||
{
|
||||
value = bfd_getl16 (buffer);
|
||||
|
||||
if (operand->flags & V850E_IMMEDIATE16HI)
|
||||
value <<= 16;
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
if (!noerror)
|
||||
info->memory_error_func (status, memaddr + bytes_read, info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (operand->flags & V850E_IMMEDIATE23)
|
||||
{
|
||||
int status = info->read_memory_func (memaddr + 2, buffer, 4, info);
|
||||
|
||||
if (status == 0)
|
||||
{
|
||||
value = bfd_getl32 (buffer);
|
||||
|
||||
value = (operand->extract) (value, invalid);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
if (!noerror)
|
||||
info->memory_error_func (status, memaddr + bytes_read, info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (operand->flags & V850E_IMMEDIATE32)
|
||||
{
|
||||
int status = info->read_memory_func (memaddr + bytes_read, buffer, 4, info);
|
||||
|
||||
if (status == 0)
|
||||
{
|
||||
bytes_read += 4;
|
||||
value = bfd_getl32 (buffer);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
if (!noerror)
|
||||
info->memory_error_func (status, memaddr + bytes_read, info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (operand->extract)
|
||||
value = (operand->extract) (insn, invalid);
|
||||
else
|
||||
{
|
||||
if (operand->bits == -1)
|
||||
value = (insn & operand->shift);
|
||||
else
|
||||
value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
|
||||
|
||||
if (operand->flags & V850_OPERAND_SIGNED)
|
||||
value = ((long)(value << (sizeof (long)*8 - operand->bits))
|
||||
>> (sizeof (long)*8 - operand->bits));
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
disassemble (bfd_vma memaddr,
|
||||
struct disassemble_info * info,
|
||||
unsigned long insn)
|
||||
disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, unsigned long insn)
|
||||
{
|
||||
struct v850_opcode * op = (struct v850_opcode *) v850_opcodes;
|
||||
const struct v850_operand * operand;
|
||||
struct v850_opcode *op = (struct v850_opcode *)v850_opcodes;
|
||||
const struct v850_operand *operand;
|
||||
int match = 0;
|
||||
int short_op = ((insn & 0x0600) != 0x0600);
|
||||
int bytes_read;
|
||||
int target_processor;
|
||||
|
||||
/* Special case: 32 bit MOV. */
|
||||
if ((insn & 0xffe0) == 0x0620)
|
||||
short_op = 1;
|
||||
|
||||
bytes_read = short_op ? 2 : 4;
|
||||
|
||||
/* If this is a two byte insn, then mask off the high bits. */
|
||||
if (short_op)
|
||||
insn &= 0xffff;
|
||||
|
||||
switch (info->mach)
|
||||
{
|
||||
case 0:
|
||||
|
|
@ -79,22 +204,66 @@ disassemble (bfd_vma memaddr,
|
|||
break;
|
||||
|
||||
case bfd_mach_v850e1:
|
||||
target_processor = PROCESSOR_V850E1;
|
||||
target_processor = PROCESSOR_V850E;
|
||||
break;
|
||||
|
||||
case bfd_mach_v850e2:
|
||||
target_processor = PROCESSOR_V850E2;
|
||||
break;
|
||||
|
||||
case bfd_mach_v850e2v3:
|
||||
target_processor = PROCESSOR_V850E2V3;
|
||||
break;
|
||||
}
|
||||
|
||||
/* If this is a two byte insn, then mask off the high bits. */
|
||||
if (bytes_read == 2)
|
||||
insn &= 0xffff;
|
||||
|
||||
/* Find the opcode. */
|
||||
while (op->name)
|
||||
{
|
||||
if ((op->mask & insn) == op->opcode
|
||||
&& (op->processors & target_processor))
|
||||
&& (op->processors & target_processor)
|
||||
&& !(op->processors & PROCESSOR_OPTION_ALIAS))
|
||||
{
|
||||
/* Code check start. */
|
||||
const unsigned char *opindex_ptr;
|
||||
unsigned int opnum;
|
||||
unsigned int memop;
|
||||
|
||||
for (opindex_ptr = op->operands, opnum = 1;
|
||||
*opindex_ptr != 0;
|
||||
opindex_ptr++, opnum++)
|
||||
{
|
||||
int invalid = 0;
|
||||
long value;
|
||||
|
||||
operand = &v850_operands[*opindex_ptr];
|
||||
|
||||
value = get_operand_value (operand, insn, bytes_read, memaddr, info, 1, &invalid);
|
||||
|
||||
if (invalid)
|
||||
goto next_opcode;
|
||||
|
||||
if ((operand->flags & V850_NOT_R0) && value == 0 && (op->memop) <=2)
|
||||
goto next_opcode;
|
||||
|
||||
if ((operand->flags & V850_NOT_SA) && value == 0xd)
|
||||
goto next_opcode;
|
||||
|
||||
if ((operand->flags & V850_NOT_IMM0) && value == 0)
|
||||
goto next_opcode;
|
||||
}
|
||||
|
||||
/* Code check end. */
|
||||
|
||||
match = 1;
|
||||
(*info->fprintf_func) (info->stream, "%s\t", op->name);
|
||||
#if 0
|
||||
fprintf (stderr, "match: insn: %lx, mask: %lx, opcode: %lx, name: %s\n",
|
||||
insn, op->mask, op->opcode, op->name );
|
||||
#endif
|
||||
|
||||
memop = op->memop;
|
||||
/* Now print the operands.
|
||||
|
|
@ -116,24 +285,11 @@ disassemble (bfd_vma memaddr,
|
|||
{
|
||||
long value;
|
||||
int flag;
|
||||
int status;
|
||||
bfd_byte buffer[4];
|
||||
char *prefix;
|
||||
|
||||
operand = &v850_operands[*opindex_ptr];
|
||||
|
||||
if (operand->extract)
|
||||
value = (operand->extract) (insn, 0);
|
||||
else
|
||||
{
|
||||
if (operand->bits == -1)
|
||||
value = (insn & operand->shift);
|
||||
else
|
||||
value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
|
||||
|
||||
if (operand->flags & V850_OPERAND_SIGNED)
|
||||
value = ((long)(value << (32 - operand->bits))
|
||||
>> (32 - operand->bits));
|
||||
}
|
||||
value = get_operand_value (operand, insn, bytes_read, memaddr, info, 0, 0);
|
||||
|
||||
/* The first operand is always output without any
|
||||
special handling.
|
||||
|
|
@ -156,88 +312,57 @@ disassemble (bfd_vma memaddr,
|
|||
The exception (and there's always an exception) is the
|
||||
"jmp" insn which needs square brackets around it's only
|
||||
register argument. */
|
||||
prefix = "";
|
||||
if (operand->flags & V850_OPERAND_BANG)
|
||||
{
|
||||
prefix = "!";
|
||||
}
|
||||
else if (operand->flags & V850_OPERAND_PERCENT)
|
||||
{
|
||||
prefix = "%";
|
||||
}
|
||||
|
||||
if (memop && opnum == memop + 1)
|
||||
info->fprintf_func (info->stream, "[");
|
||||
else if (memop && opnum == memop + 2)
|
||||
info->fprintf_func (info->stream, "],");
|
||||
else if (memop == 1 && opnum == 1
|
||||
&& (operand->flags & V850_OPERAND_REG))
|
||||
info->fprintf_func (info->stream, "[");
|
||||
else if (opnum > 1)
|
||||
info->fprintf_func (info->stream, ", ");
|
||||
if (opnum == 1 && opnum == memop)
|
||||
info->fprintf_func (info->stream, "%s[", prefix);
|
||||
else if (opnum > 1
|
||||
&& (v850_operands[*(opindex_ptr - 1)].flags & V850_OPERAND_DISP) != 0
|
||||
&& opnum == memop)
|
||||
info->fprintf_func (info->stream, "%s[", prefix);
|
||||
else if (opnum > 1)
|
||||
info->fprintf_func (info->stream, ", %s", prefix);
|
||||
|
||||
/* Extract the flags, ignorng ones which
|
||||
do not effect disassembly output. */
|
||||
flag = operand->flags;
|
||||
flag &= ~ V850_OPERAND_SIGNED;
|
||||
flag &= ~ V850_OPERAND_RELAX;
|
||||
flag &= - flag;
|
||||
/* Extract the flags, ignoring ones which do not effect disassembly output. */
|
||||
flag = operand->flags & (V850_OPERAND_REG
|
||||
| V850_REG_EVEN
|
||||
| V850_OPERAND_EP
|
||||
| V850_OPERAND_SRG
|
||||
| V850E_OPERAND_REG_LIST
|
||||
| V850_OPERAND_CC
|
||||
| V850_OPERAND_FLOAT_CC);
|
||||
|
||||
switch (flag)
|
||||
{
|
||||
case V850_OPERAND_REG:
|
||||
info->fprintf_func (info->stream, "%s", v850_reg_names[value]);
|
||||
break;
|
||||
case V850_OPERAND_SRG:
|
||||
info->fprintf_func (info->stream, "%s", v850_sreg_names[value]);
|
||||
break;
|
||||
case V850_OPERAND_CC:
|
||||
info->fprintf_func (info->stream, "%s", v850_cc_names[value]);
|
||||
break;
|
||||
case V850_OPERAND_EP:
|
||||
info->fprintf_func (info->stream, "ep");
|
||||
break;
|
||||
default:
|
||||
info->fprintf_func (info->stream, "%ld", value);
|
||||
break;
|
||||
case V850_OPERAND_DISP:
|
||||
{
|
||||
bfd_vma addr = value + memaddr;
|
||||
case V850_OPERAND_REG: info->fprintf_func (info->stream, "%s", v850_reg_names[value]); break;
|
||||
case (V850_OPERAND_REG|V850_REG_EVEN): info->fprintf_func (info->stream, "%s", v850_reg_names[value*2]); break;
|
||||
case V850_OPERAND_EP: info->fprintf_func (info->stream, "ep"); break;
|
||||
case V850_OPERAND_SRG: info->fprintf_func (info->stream, "%s", v850_sreg_names[value]); break;
|
||||
|
||||
/* On the v850 the top 8 bits of an address are used by an
|
||||
overlay manager. Thus it may happen that when we are
|
||||
looking for a symbol to match against an address with
|
||||
some of its top bits set, the search fails to turn up an
|
||||
exact match. In this case we try to find an exact match
|
||||
against a symbol in the lower address space, and if we
|
||||
find one, we use that address. We only do this for
|
||||
JARL instructions however, as we do not want to
|
||||
misinterpret branch instructions. */
|
||||
if (operand->bits == 22)
|
||||
{
|
||||
if ( ! info->symbol_at_address_func (addr, info)
|
||||
&& ((addr & 0xFF000000) != 0)
|
||||
&& info->symbol_at_address_func (addr & 0x00FFFFFF, info))
|
||||
addr &= 0x00FFFFFF;
|
||||
}
|
||||
info->print_address_func (addr, info);
|
||||
break;
|
||||
}
|
||||
|
||||
case V850E_PUSH_POP:
|
||||
case V850E_OPERAND_REG_LIST:
|
||||
{
|
||||
static int list12_regs[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
|
||||
static int list18_h_regs[32] = { 19, 18, 17, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 30, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
|
||||
static int list18_l_regs[32] = { 3, 2, 1, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 14, 15, 13, 12, 7, 6, 5, 4, 11, 10, 9, 8 };
|
||||
static int list12_regs[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
|
||||
int *regs;
|
||||
int i;
|
||||
unsigned long int mask = 0;
|
||||
int pc = 0;
|
||||
int sr = 0;
|
||||
|
||||
|
||||
switch (operand->shift)
|
||||
{
|
||||
case 0xffe00001: regs = list12_regs; break;
|
||||
case 0xfff8000f: regs = list18_h_regs; break;
|
||||
case 0xfff8001f:
|
||||
regs = list18_l_regs;
|
||||
value &= ~0x10; /* Do not include magic bit. */
|
||||
break;
|
||||
default:
|
||||
/* xgettext:c-format */
|
||||
fprintf (stderr, _("unknown operand shift: %x\n"),
|
||||
operand->shift);
|
||||
fprintf (stderr, _("unknown operand shift: %x\n"), operand->shift );
|
||||
abort ();
|
||||
}
|
||||
|
||||
|
|
@ -249,18 +374,15 @@ disassemble (bfd_vma memaddr,
|
|||
{
|
||||
default: mask |= (1 << regs[ i ]); break;
|
||||
/* xgettext:c-format */
|
||||
case 0:
|
||||
fprintf (stderr, _("unknown pop reg: %d\n"), i );
|
||||
abort ();
|
||||
case 0: fprintf (stderr, _("unknown reg: %d\n"), i ); abort ();
|
||||
case -1: pc = 1; break;
|
||||
case -2: sr = 1; break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
info->fprintf_func (info->stream, "{");
|
||||
|
||||
if (mask || pc || sr)
|
||||
if (mask || pc)
|
||||
{
|
||||
if (mask)
|
||||
{
|
||||
|
|
@ -278,8 +400,7 @@ disassemble (bfd_vma memaddr,
|
|||
else
|
||||
shown_one = 1;
|
||||
|
||||
info->fprintf_func (info->stream,
|
||||
v850_reg_names[first]);
|
||||
info->fprintf_func (info->stream, v850_reg_names[first]);
|
||||
|
||||
for (bit++; bit < 32; bit++)
|
||||
if ((mask & (1 << bit)) == 0)
|
||||
|
|
@ -288,113 +409,227 @@ disassemble (bfd_vma memaddr,
|
|||
last = bit;
|
||||
|
||||
if (last > first + 1)
|
||||
info->fprintf_func (info->stream, " - %s",
|
||||
v850_reg_names[last - 1]);
|
||||
{
|
||||
info->fprintf_func (info->stream, " - %s", v850_reg_names[ last - 1 ]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (pc)
|
||||
info->fprintf_func (info->stream, "%sPC", mask ? ", " : "");
|
||||
if (sr)
|
||||
info->fprintf_func (info->stream, "%sSR", (mask || pc) ? ", " : "");
|
||||
}
|
||||
|
||||
info->fprintf_func (info->stream, "}");
|
||||
}
|
||||
break;
|
||||
|
||||
case V850E_IMMEDIATE16:
|
||||
status = info->read_memory_func (memaddr + bytes_read,
|
||||
buffer, 2, info);
|
||||
if (status == 0)
|
||||
{
|
||||
bytes_read += 2;
|
||||
value = bfd_getl16 (buffer);
|
||||
|
||||
/* If this is a DISPOSE instruction with ff
|
||||
set to 0x10, then shift value up by 16. */
|
||||
if ((insn & 0x001fffc0) == 0x00130780)
|
||||
value <<= 16;
|
||||
|
||||
info->fprintf_func (info->stream, "0x%lx", value);
|
||||
}
|
||||
else
|
||||
info->memory_error_func (status, memaddr + bytes_read,
|
||||
info);
|
||||
break;
|
||||
|
||||
case V850E_IMMEDIATE32:
|
||||
status = info->read_memory_func (memaddr + bytes_read,
|
||||
buffer, 4, info);
|
||||
if (status == 0)
|
||||
{
|
||||
bytes_read += 4;
|
||||
value = bfd_getl32 (buffer);
|
||||
info->fprintf_func (info->stream, "0x%lx", value);
|
||||
}
|
||||
else
|
||||
info->memory_error_func (status, memaddr + bytes_read,
|
||||
info);
|
||||
case V850_OPERAND_CC: info->fprintf_func (info->stream, "%s", v850_cc_names[value]); break;
|
||||
case V850_OPERAND_FLOAT_CC: info->fprintf_func (info->stream, "%s", v850_float_cc_names[value]); break;
|
||||
|
||||
default:
|
||||
print_value (operand->flags, memaddr, info, value);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Handle jmp correctly. */
|
||||
if (memop == 1 && opnum == 1
|
||||
&& ((operand->flags & V850_OPERAND_REG) != 0))
|
||||
if (opnum == 2 && opnum == memop)
|
||||
(*info->fprintf_func) (info->stream, "]");
|
||||
}
|
||||
|
||||
/* Close any square bracket we left open. */
|
||||
if (memop && opnum == memop + 2)
|
||||
(*info->fprintf_func) (info->stream, "]");
|
||||
|
||||
/* All done. */
|
||||
break;
|
||||
}
|
||||
next_opcode:
|
||||
op++;
|
||||
}
|
||||
|
||||
if (!match)
|
||||
{
|
||||
if (short_op)
|
||||
info->fprintf_func (info->stream, ".short\t0x%04lx", insn);
|
||||
else
|
||||
info->fprintf_func (info->stream, ".long\t0x%08lx", insn);
|
||||
}
|
||||
|
||||
return bytes_read;
|
||||
return match;
|
||||
}
|
||||
|
||||
int
|
||||
print_insn_v850 (bfd_vma memaddr, struct disassemble_info * info)
|
||||
{
|
||||
int status;
|
||||
bfd_byte buffer[4];
|
||||
unsigned long insn = 0;
|
||||
int status, status2, match;
|
||||
bfd_byte buffer[8];
|
||||
int length = 0, code_length = 0;
|
||||
unsigned long insn = 0, insn2 = 0;
|
||||
int target_processor;
|
||||
|
||||
/* First figure out how big the opcode is. */
|
||||
status = info->read_memory_func (memaddr, buffer, 2, info);
|
||||
if (status == 0)
|
||||
switch (info->mach)
|
||||
{
|
||||
insn = bfd_getl16 (buffer);
|
||||
case 0:
|
||||
default:
|
||||
target_processor = PROCESSOR_V850;
|
||||
break;
|
||||
|
||||
if ( (insn & 0x0600) == 0x0600
|
||||
&& (insn & 0xffe0) != 0x0620)
|
||||
{
|
||||
/* If this is a 4 byte insn, read 4 bytes of stuff. */
|
||||
status = info->read_memory_func (memaddr, buffer, 4, info);
|
||||
case bfd_mach_v850e:
|
||||
target_processor = PROCESSOR_V850E;
|
||||
break;
|
||||
|
||||
if (status == 0)
|
||||
insn = bfd_getl32 (buffer);
|
||||
}
|
||||
case bfd_mach_v850e1:
|
||||
target_processor = PROCESSOR_V850E;
|
||||
break;
|
||||
|
||||
case bfd_mach_v850e2:
|
||||
target_processor = PROCESSOR_V850E2;
|
||||
break;
|
||||
|
||||
case bfd_mach_v850e2v3:
|
||||
target_processor = PROCESSOR_V850E2V3;
|
||||
break;
|
||||
}
|
||||
|
||||
if (status != 0)
|
||||
status = info->read_memory_func (memaddr, buffer, 2, info);
|
||||
|
||||
if (status)
|
||||
{
|
||||
info->memory_error_func (status, memaddr, info);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Make sure we tell our caller how many bytes we consumed. */
|
||||
return disassemble (memaddr, info, insn);
|
||||
insn = bfd_getl16 (buffer);
|
||||
|
||||
status2 = info->read_memory_func (memaddr+2, buffer, 2 , info);
|
||||
|
||||
if (!status2)
|
||||
{
|
||||
insn2 = bfd_getl16 (buffer);
|
||||
/* fprintf (stderr, "insn2 0x%08lx\n", insn2); */
|
||||
}
|
||||
|
||||
/* Special case. */
|
||||
if (length == 0
|
||||
&& (target_processor == PROCESSOR_V850E2
|
||||
|| target_processor == PROCESSOR_V850E2V3))
|
||||
{
|
||||
if ((insn & 0xffff) == 0x02e0 /* jr 32bit */
|
||||
&& !status2 && (insn2 & 0x1) == 0)
|
||||
{
|
||||
length = 2;
|
||||
code_length = 6;
|
||||
}
|
||||
else if ((insn & 0xffe0) == 0x02e0 /* jarl 32bit */
|
||||
&& !status2 && (insn2 & 0x1) == 0)
|
||||
{
|
||||
length = 2;
|
||||
code_length = 6;
|
||||
}
|
||||
else if ((insn & 0xffe0) == 0x06e0 /* jmp 32bit */
|
||||
&& !status2 && (insn2 & 0x1) == 0)
|
||||
{
|
||||
length = 2;
|
||||
code_length = 6;
|
||||
}
|
||||
}
|
||||
|
||||
if (length == 0
|
||||
&& target_processor == PROCESSOR_V850E2V3)
|
||||
{
|
||||
if (((insn & 0xffe0) == 0x0780 /* ld.b 23bit */
|
||||
&& !status2 && (insn2 & 0x000f) == 0x0005)
|
||||
|| ((insn & 0xffe0) == 0x07a0 /* ld.bu 23bit */
|
||||
&& !status2 && (insn2 & 0x000f) == 0x0005)
|
||||
|| ((insn & 0xffe0) == 0x0780 /* ld.h 23bit */
|
||||
&& !status2 && (insn2 & 0x000f) == 0x0007)
|
||||
|| ((insn & 0xffe0) == 0x07a0 /* ld.hu 23bit */
|
||||
&& !status2 && (insn2 & 0x000f) == 0x0007)
|
||||
|| ((insn & 0xffe0) == 0x0780 /* ld.w 23bit */
|
||||
&& !status2 && (insn2 & 0x000f) == 0x0009))
|
||||
{
|
||||
length = 4;
|
||||
code_length = 6;
|
||||
}
|
||||
else if (((insn & 0xffe0) == 0x0780 /* st.b 23bit */
|
||||
&& !status2 && (insn2 & 0x000f) == 0x000d)
|
||||
|| ((insn & 0xffe0) == 0x07a0 /* st.h 23bit */
|
||||
&& !status2 && (insn2 & 0x000f) == 0x000d)
|
||||
|| ((insn & 0xffe0) == 0x0780 /* st.w 23bit */
|
||||
&& !status2 && (insn2 & 0x000f) == 0x000f))
|
||||
{
|
||||
length = 4;
|
||||
code_length = 6;
|
||||
}
|
||||
}
|
||||
|
||||
if (length == 0
|
||||
&& target_processor != PROCESSOR_V850)
|
||||
{
|
||||
if ((insn & 0xffe0) == 0x0620) /* 32 bit MOV */
|
||||
{
|
||||
length = 2;
|
||||
code_length = 6;
|
||||
}
|
||||
else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm16<<16 */
|
||||
&& !status2 && (insn2 & 0x001f) == 0x0013)
|
||||
{
|
||||
length = 4;
|
||||
code_length = 6;
|
||||
}
|
||||
else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm16 */
|
||||
&& !status2 && (insn2 & 0x001f) == 0x000b)
|
||||
{
|
||||
length = 4;
|
||||
code_length = 6;
|
||||
}
|
||||
else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm32 */
|
||||
&& !status2 && (insn2 & 0x001f) == 0x001b)
|
||||
{
|
||||
length = 4;
|
||||
code_length = 8;
|
||||
}
|
||||
}
|
||||
|
||||
if (length == 4
|
||||
|| (length == 0
|
||||
&& (insn & 0x0600) == 0x0600))
|
||||
{
|
||||
/* This is a 4 byte insn. */
|
||||
status = info->read_memory_func (memaddr, buffer, 4, info);
|
||||
if (!status)
|
||||
{
|
||||
insn = bfd_getl32 (buffer);
|
||||
|
||||
if (!length)
|
||||
length = code_length = 4;
|
||||
}
|
||||
}
|
||||
|
||||
if (code_length > length)
|
||||
{
|
||||
status = info->read_memory_func (memaddr + length, buffer, code_length - length, info);
|
||||
if (status)
|
||||
length = 0;
|
||||
}
|
||||
|
||||
if (length == 0 && !status)
|
||||
length = code_length = 2;
|
||||
|
||||
if (length == 2)
|
||||
insn &= 0xffff;
|
||||
|
||||
match = disassemble (memaddr, info, length, insn);
|
||||
|
||||
if (!match)
|
||||
{
|
||||
int l = 0;
|
||||
|
||||
status = info->read_memory_func (memaddr, buffer, code_length, info);
|
||||
|
||||
while (l < code_length)
|
||||
{
|
||||
if (code_length - l == 2)
|
||||
{
|
||||
insn = bfd_getl16 (buffer + l) & 0xffff;
|
||||
info->fprintf_func (info->stream, ".short\t0x%04lx", insn);
|
||||
l += 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
insn = bfd_getl32 (buffer + l);
|
||||
info->fprintf_func (info->stream, ".long\t0x%08lx", insn);
|
||||
l += 4;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return code_length;
|
||||
}
|
||||
|
|
|
|||
1338
opcodes/v850-opc.c
1338
opcodes/v850-opc.c
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue