(INSTALL_XFORM, INSTALL_XFORM1): Remove.
(install-common): Depend upon installdirs. Use
$(program_transform_name) directly, rather than using
$(INSTALL_XFORM).
(installdirs): New target.
* Makefile.in (INSTALL): Set to @INSTALL@.
(INSTALL_XFORM, INSTALL_XFORM1): Remove.
(install-man): Depend upon installdirs. Use
$(program_transform_name) directly, rather than using
$(INSTALL_XFORM).
(installdirs): New target.
(INSTALL_XFORM, INSTALL_XFORM1): Remove.
(install): Depend upon installdirs. Use $(program_transform_name)
directly, rather than using $(INSTALL_XFORM).
(installdirs): New target.
(INSTALL_XFORM, INSTALL_XFORM1): Remove.
(install): Depend upon installdirs. Use $(program_transform_name)
directly, rather than using $(INSTALL_XFORM) and
$(INSTALL_XFORM1).
(installdirs): New target.
Somewhat simplify "sub" instructions.
Correctly sign extend operands for "mul". Put the correct
half of the result in MDR for "mul" and "mulu".
Implement remaining instructions.
Tweak opcode for "syscall".
* Make-common.in (CSEARCH): Do not include the gdb directory in
the search path.
* Make-common.in (SIM_ENDIAN, SIM_HOSTENDIAN, SIM_INLINE,
SIM_WARNING): Drop, requiring the simulator specific Makefile.in
to explicitly incorporate these.
* aclocal.m4 (--enable-sim-alignment); New option. Strongly
specify the alignment restrictions of the target architecture -
without this option all alignment restrictions are accomodated.
(--enable-sim-assert): New option. Conditionally compile in
assertion statements.
(--enable-sim-float): New option. Strongly specify the target's
floating point support.
(--enable-sim-hardware): New option. Specify the hardware devices
included in the simulation.
(--enable-sim-packages): New option. Specify the hardware
packages included in the simulation.
(--enable-sim-regparm): New option. Specify that parameters be
passed in registers instead of on the stack.
(--enable-sim-reserved-bits): New option. Specify that reserved
bits within an instruction are are correctly set.
(--enable-sim-smp): New option. Specify the level of SMP support
to be included in the simulator.
(--enable-sim-stdcall): New option. Specify an alternative
function call convention.
(--enable-sim-xor-endian): New option. Configure xor-endian
support used by some targets to implement bi-endian support.
(main): New locals sd,no_args,sim_argv.
Run buildargv on -a option. Pass argv to sim_open, argv[0]
is program name. Update call to sim_set_callbacks.
Record result of sim_open, pass to other sim_foo routines.
(SignalException): Pass floating point cases to mips16_entry.
(ValueFPR): Don't restrict fmt_single and fmt_word to even
registers.
(StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
or fmt_word.
(COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
and then set the state to fmt_uninterpreted.
(COP_SW): Temporarily set the state to fmt_word while calling
ValueFPR.
scheme which is more compatible with WinGDB builds.
* configure.in: Improve comment on how to run autoconf.
* configure: Re-run autoconf to get new ../common/aclocal.m4.
* Makefile.in: Use autoconf substitution to install common
makefile fragment.
into here. Makes insertion into makefiles easier. Also, change
the way that callback.o, gentmap, targ-vals.h, targ-map.c,
targ-map.o, and run are built. They are now built in the
individual simulator directories, taking sources from ../common as
necessary. This replaces the merging of libcommon.a into
linsim.a, which was problematic for the WinGDB build process.
* run.c: Include config.h from . instead of ../common.
* Make-common.in: Remove. It's no longer necessary.
array to make gdb implementation easier.
(REG_*): Add definitions for all registers in the state array.
(SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
* simops.c: Related changes.
(mips16_entry): New static function.
(SignalException): Look for mips16 entry and exit instructions.
(simulate): Use the correct index when setting fpr_state after
doing a pending move.
force a 64 bit multiplication.
(build_instruction) [OR]: In mips16 mode, don't do anything if the
destination register is 0, since that is the default mips16 nop
instruction.
(build_endian_shift): Don't check proc64.
(build_instruction): Always set memval to uword64. Cast op2 to
uword64 when shifting it left in memory instructions. Always use
the same code for stores--don't special case proc64.
relative operands.
(build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
jal instruction.
* interp.c (simJALDELAYSLOT): Define.
(JALDELAYSLOT): Define.
(INDELAYSLOT, INJALDELAYSLOT): Define.
(simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
* gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
* interp.c (CHECKHILO): Define away.
(simSIGINT): New macro.
(membank_size): Increase from 1MB to 2MB.
(control_c): New function.
(sim_resume): Rename parameter signal to signal_number. Add local
variable prev. Call signal before and after simulate.
(sim_stop_reason): Add simSIGINT support.
(sim_warning, sim_error, dotrace, SignalException): Define as stdarg
functions always.
(sim_warning): Delete call to SignalException. Do call printf_filtered
if logfh is NULL.
(AddressTranslation): Add #ifdef DEBUG around debugging message and
a call to sim_warning.
to the OP_* declarations.
(write_template): Similarly for function templates.
* interp.c (insn, extension): Remove global variables. Instead
pass them as arguments to the OP_* functions.
* mn10300_sim.h: Remove decls for "insn" and "extension".
* simops.c (OP_*): Accept "insn" and "extension" as arguments
instead of using globals.
Starting to clean things up.
* Makefile.in: Only link in -ltermcap if it exists.
* erc32.c: Update to version 2.6a. Fix uart handling.
* exec.c: Update to version 2.6a. Add sparclite support.
* float.c: Update to version 2.6a. Convert comments to
preprocessor warnings. Add __setfpucw() for i385 hosts so floating
point exceptions work.
* func.c: Update to version 2.6a. Fix uart handling, add support
for user error traps.
* help.c: Update to version 2.6a. Add help note on user error
traps.
* interf.c: Update to version 2.6a. Fix uart handling, and add
sparclite support.
* examples/gccx: Use sparclite cross compiler, not native gcc.
* examples/srt0.S: Use "mov" rather than "wr" for manipulating
the psr register.
(REG_MDR): Define.
* simops.c: Implement "cmp", "calls", "rets", "jmp" and
a few additional random insns.
We can now function calls. We get out of crt0 into main now, then lose
when calls are nested (because don't handle movm yet).
(REG_D0, REG_A0, REG_SP): Define.
* simops.c: Implement "add", "addc" and a few other random
instructions.
Starting to simulate instructions for the mn10300. Executes some of
the crt0 code now!
* gencode.c (inst_type): Add mips16 instruction encoding types.
(GETDATASIZEINSN): Define.
(MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
mtlo.
(MIPS16_DECODE): New table, for mips16 instructions.
(bitmap_val): New static function.
(struct mips16_op): Define.
(mips16_op_table): New table, for mips16 operands.
(build_mips16_operands): New static function.
(process_instructions): If PC is odd, decode a mips16
instruction. Break out instruction handling into new
build_instruction function.
(build_instruction): New static function, broken out of
process_instructions. Check modifiers rather than flags for SHIFT
bit count and m[ft]{hi,lo} direction.
(usage): Pass program name to fprintf.
(main): Remove unused variable this_option_optind. Change
``*loptarg++'' to ``loptarg++''.
(my_strtoul): Parenthesize && within ||.
* interp.c (sim_trace): If tracefh is NULL, set it to stderr.
(LoadMemory): Accept a halfword pAddr if vAddr is odd.
(simulate): If PC is odd, fetch a 16 bit instruction, and
increment PC by 2 rather than 4.
* configure.in: Add case for mips16*-*-*.
* configure: Rebuild.
(SIM_OBJS): Define.
* configure.in: Simplify using macros in ../common/aclocal.m4.
* configure: Regenerated.
* inst.h (enum sim_state): Define.
(cpu_state_type): New member `state'. Set it whenever `exception'
is set.
* compile.c (sim_callback): New global.
(sim_set_simcache_size): Renamed from sim_csize.
(sim_resume, case O_SLEEP): Add right way to decode r0 but #if 0 out
'cus it can't work. Change main loop exit test to use cpu.state.
(sim_trace): New function.
(sim_stop_reason): Add right way to set results, but #if 0 out.
(sim_size): New function.
(sim_info): Redirect calls to printf_filtered through callback.
(sim_set_callbacks): Record callback.
* run.c: Deleted, using one in ../common now.
* tconfig.in: New file.
(SIM_{OBJS,EXTRA_LIBS,EXTRA_LIBDEPS,EXTRA_ALL,EXTRA_INSTALL}): Define.
(SIM_{EXTRA_CLEAN,EXTRA_CFLAGS}): Define.
* configure.in: Simplify using macros in ../common/aclocal.m4.
Call AC_CHECK_HEADERS(stdlib.h).
* configure: Regenerated.
* config.in: New file.
* func.c (sim_set_callbacks): Delete, moved to
* interf.c (sim_set_callbacks): here.
(sim_callback): New global.
Rewrite all calls to printf_filtered to go through callback.
(sim_size,sim_trace): New functions.
(sim_{insert,remove}_breakpoint): #if 0 out.
* sis.c: #include "config.h". #include <stdlib.h> if present.
(main): Coerce fprintf arg to INIT_DISASSEMBLE_INFO to fprintf_ftype.
* sis.h: #include "callback.h".
(myname): New static global.
(main): Recognize new options -a, -c. Also recognize -h if h8/300.
Only process -c ifdef SIM_HAVE_SIMCACHE.
Only process -p/-s ifdef SIM_HAVE_PROFILE.
Parse program name from argv[0] and use in error messages.
Pass sim_args to sim_open. Pass prog_args to sim_create_inferior.
Add support for incomplete h8/300 termination indicators.
(usage): Make more verbose.
* aclocal.m4,config.in,tconfig.in,configure.in,configure: New files.
* Makefile.in,Make-common.in,callback.c: New files.
* nltvals.def,gentmap.c,gentvals.sh: New files.
* Makefile.in: Delete everything that's been moved to
../common/Make-common.in.
(SIM_OBJS): Define.
* configure.in: Simplify using macros in ../common/aclocal.m4.
* configure: Regenerated.
* config.in: New file.
* armos.c: #include config.h.
* wrapper.c (mem_size): Value is in bytes now.
(sim_callback): New global.
(arm_sim_set_profile{,_size}): Delete.
(arm_sim_set_mem_size): Rename to sim_size.
(sim_do_command): Call printf_filtered via callback.
(sim_set_callbacks): Record callback.
* d10v-sim.h (simops): Add flag is_long.
(State): Add pc_changed. Instructions which update the PC should
use the JMP macro which sets this.
(JMP): New macro. Sets the PC and the pc_changed flag.
* gencode.c (write_opcodes): Add is_long field.
* interp.c (lookup_hash): If we blindly apply a short opcode's mask
to a long opcode we could get a false match. Check the opcode size.
(hash): Add a size field to the hash table.
(sim_open): Initialize size field in hash table.
(sim_resume): Change to logic for setting the PC. Used to increment the
PC if it had not been changed. This didn't allow single-instruction loops.
Now checks the flag State.pc_changed. Also now stops when ^C is received.
(dmem_addr): Fix translation of data segments to unified memory.
(sim_ctrl_c): New function. When ^C is received, set stop_simulator flag.
* simops.c: Changed all branch and jump instructions to use new JMP macro.
(OP_20000000): Corrected trace information to show this is a ldi.l, not
a ldi.s instruction.
* interp.c (sim_size): Now allocates unified memory for imap segments
0,1,2, and 127. Initializes imap0 and imap1 to 0x1000. Initializes dmap to 0.
(sim_write): Just call xfer_mem().
(sim_read): Just call xfer_mem().
(xfer_mem): New function. Does appropriate memory mapping and copies bytes.
(dmem_addr): New function. Reads dmap register and translates data
addresses to local addresses.
(pc_addr): New function. Reads imap register and computes local address
corresponding to contents of the PC.
(sim_resume): Change to use pc_addr().
(sim_create_inferior): Change reinitialization code. Also reinitializes
imap[01] and dmap.
(sim_fetch_register): Add fake registers 32,33,34 for imap0, imap1, and dmap.
(sim_store_register): Add fake registers 32,33,34 for imap0, imap1, and dmap.
* simops.c (MEMPTR): Redefine to use dmem_addr().
(OP_5F00): Replace references to STate.imem with dmem_addr().
* d10v-sim.h (State): Remove mem_min and mem_max. Add umem[128].
(RB,SW,RW,SLW,RLW): Redefine to use dmem_addr().
(IMAP0,IMAP1,DMAP,SET_IMAP,SET_IMAP1,SET_DMAP): Define.
(OP_300, OP_400, OP_500, OP_380, OP_480, OP_501): Displacement
is zero extended for sst/sld instructions.
* v850_sim.h (SEX7): Delete. It's no longer needed (and it
was incorrect anyway).
So we properly simulate sst/sld instructions.
autoconf.
* gencode.c (write_opcodes): Pad operands field to account for
MSVC braindamage.
* simops.c: Include errno.h. Exclude SYS_chown, since MSVC
doesn't support it. (Why is this here in the first place?!?)
* v850_sim.h: Get rid of 64 bit defs. Also, get rid of #elif's.
Change number of operands in struct simops from 9 to 6. Define
SIGTRAP and SIGQUIT for MSVC.
* (map): Add support for external mem in the 1->2 meg range.
Also, abort() when memory access is way out of bounds. (Better to
die than to give wrong result. (This will be fixed later.))
* (sim_size): MEM_SIZE is now bytes, not shift factor.
and patterns.
* interp.c (sim_resume): Save and restore PC from the appropriate
register.
* (sim_fetch_register sim_store_register): Fix byte-order problem
with reading and writing registers.
* simops.c (OP_FFFF): Implement pseudo-breakpoint insn.
