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* gencode.c (build_instruction) [MUL]: Cast operands to word64, to

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force a 64 bit multiplication.
	(build_instruction) [OR]: In mips16 mode, don't do anything if the
	destination register is 0, since that is the default mips16 nop
	instruction.
This commit is contained in:
Ian Lance Taylor 1996-12-19 19:08:46 +00:00
parent 9a442fe8a5
commit deffd638b5
2 changed files with 14 additions and 1 deletions
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8
sim/mips/ChangeLog
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@ -1,3 +1,11 @@
Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
* gencode.c (build_instruction) [MUL]: Cast operands to word64, to
force a 64 bit multiplication.
(build_instruction) [OR]: In mips16 mode, don't do anything if the
destination register is 0, since that is the default mips16 nop
instruction.
Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
* gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.

7
sim/mips/gencode.c
View file

@ -1622,7 +1622,7 @@ build_instruction (doisa, features, mips16, insn)
if (insn->flags & UNSIGNED)
printf(" uword64 temp = ((uword64)(op1 & 0xffffffff) * (uword64)(op2 & 0xffffffff));\n");
else
printf(" uword64 temp = (op1 * op2);\n");
printf(" uword64 temp = ((word64) op1 * (word64) op2);\n");
printf(" LO = SIGNEXTEND((%s)WORD64LO(temp),32);\n",regtype);
printf(" HI = SIGNEXTEND((%s)WORD64HI(temp),32);\n",regtype);
}
@ -1795,6 +1795,11 @@ build_instruction (doisa, features, mips16, insn)
break ;
case OR:
/* The default mips16 nop instruction does an or to register
zero; catch that case, so that we don't get useless warnings
from the simulator. */
if (mips16)
printf (" if (destreg != 0)\n");
printf(" GPR[destreg] = %s(op1 | op2);\n",((insn->flags & NOT) ? "~" : ""));
break ;