Commit graph

79 commits

Author SHA1 Message Date
Ron Unrau
2151467d63 sky-vu.[ch]: prototype decls, cast floats to ints before register transfer
interp.c: integrate VU register read/writes
sim-main.h : track tm-txvu.h
1998-04-01 17:31:24 +00:00
James Lemke
1ff39ecb10 * sky-dma.c: Clarify text in warning msg.
* interp.c: Add global option "float-type".
	* sky-vu.h: Add SIM_DESC sd; to VectorUnitState for accessing
	global options.
1998-03-31 21:46:31 +00:00
Frank Ch. Eigler
6ed00b0607 * Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide
128-bit MIPS part.

[ChangeLog]

Mon Mar 30 18:41:43 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* interp.c (decode_coproc): Continuing COP2 work.
  	(cop_[ls]q): Hide 128-bit COP2 more.

	* sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more.

[ChangeLog.sky]

Mon Mar 30 18:44:15 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* sky-libvpe.c: Code too wide - ran indent on SCEI code.

	* sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2
 	interface.

	* sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
1998-03-30 23:56:52 +00:00
Frank Ch. Eigler
7dd4a46650 * Oops, added #ifdef TARGET_SKY around R5900 COP2 implementation skeleton. 1998-03-29 22:53:31 +00:00
Frank Ch. Eigler
15232df4a3 * Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code
into single PKE-style vu.[ch].


[ChangeLog]

Fri Mar 27 16:19:29 1998  Frank Ch. Eigler  <fche@cygnus.com>

start-sanitize-sky
	* Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.

	* interp.c (sim_{load,store}_register): Use new vu[01]_device
 	static to access VU registers.
	(decode_coproc): Added skeleton of sky COP2 (VU) instruction
 	decoding.  Work in progress.

	* mips.igen (LDCzz, SDCzz): Removed *5900 case for this
 	overlapping/redundant bit pattern.
	(LQC2, SQC2): Added *5900 COP2 instruction skeleta.  Work in
	progress.

	* sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
 	status register.

end-sanitize-sky

	* interp.c (cop_lq, cop_sq): New functions for future 128-bit
 	access to coprocessor registers.

	* sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.

[ChangeLog.sky]

	* sky-engine.c (engine_run): Adapted from vu[01] -> vu merge.

	* sky-hardware.c (register_devices): Ditto

	* sky-pke.c (pke_fifo_*): Made these functions private again, now
 	that the GPUIF code does not use them.

	* sky-pke.h (pke_fifo_*): Removed newly private declarations.

	* sky-vu.c (*): Major rework: merge of old sky-vu0.c and
 	sky-vu1.c.  Management of two VU devices parallels two PKEs.
	Work in progress.

	* sky-vu.h (*): Other half of merge.
	(vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
Ron Unrau
d44859a2d8 * sky-vu.c: new file to read/write VU registers
* Makefile.in .Sanitize: add sky-vu.c
	* sky-vu.h: define registers as enum, export read/write routines
        * sky-vu[01].[ch]: use register read/write routines in sky-vu.c
        * interp.c: use register read/write routines in sky-vu.c
1998-03-27 14:44:39 +00:00
Andrew Cagney
82ea14fd9d Define CPU_INDEX. Initialize.
For mips_options, iterate over MAX_NR_PROCESSORS when setting options.
1998-03-27 04:25:45 +00:00
Frank Ch. Eigler
fd90908986 * Numerous changes & small bug fixes in PKE sim code and test suite.
for sim/testsuite/sky:

	* t-pke4.run: Removed test, since it succeeds yet returns a
 	non-zero exit code.

	* Makefile.in (RUNOPTS): Removed --memory-size flag, made
 	unnecessary by sim/mips/interp.c changes.
	(TESTS): Removed t-pke4.ok target.

	* t-pke3.trc: Classified tests with [---] indicators, to match
 	items up with entries documented in testplan.sgml.  Added numerous
 	additional tests.  They assert behavior that assumes certain
 	favorable answers to PKE question set #6 to SCEI.

	* t-pke1.trc: Added some [---] indicators.

  for sim/mips:

	* sky-pke.c (pke_issue): Revamped interrupt & stall code.  Assume
 	that ER1/ER0/PIS bits are only set if not masked by ERR bits.
  	Signal PIS only if unmasked.
	(pke_code_error): Signal ER1 only if unmasked.
	(pke_pc_fifo): Signal ER0 only if unmasked.
	(pke_code_unpack): Round up num_operands for last operand's
 	partial-word.  Factor out "R" bit handling for better coverage
 	analysis.  Fill upper words of a quadword with zeroes for Vn_m
 	UNPACK with n < 4.

	* sky-device.c (device_error): Made function accept varargs.

	* sky-device.h (device_error): Changed declaration to match.

	* interp.c (sim_open): Made 0x0000 area memory be an alias of
	the K0/K1 segments.  Sanitized code.
1998-03-06 22:46:40 +00:00
James Lemke
9ce23bf951 * interp.c (sim_open): Map 4M of memory at zero for SKY sim only. 1998-03-04 23:33:36 +00:00
Ron Unrau
a859684b25 sim-main.h: track SKY register number changes from gdb
interp.c: ditto
1998-03-04 08:47:31 +00:00
Andrew Cagney
0e701ac37b Add generic sim-info.c:sim_info() function using module mechanism.
Clean up compile probs in mips/vr5400.
1998-02-28 02:51:06 +00:00
Doug Evans
7c5d88c1bb * interp.c (DECLARE_OPTION_HANDLER): Use it.
(mips_option_handler): New argument `cpu'.
	(sim_open): Update call to sim_add_option_table.
1998-02-28 02:43:31 +00:00
Ron Unrau
ce4713dc3b Make it compile again for -DTARGET_SKY 1998-02-23 23:40:40 +00:00
Andrew Cagney
a48e8c8d21 sim-main.h: Re-arange r5900 registers so that they have their own
little struct.
interp.c: Update.  Also add floating point Max/Min functions.
mips.igen: Remove r5900 tag from any floating point instructions.
r5900.igen: Rewrite.  Implement *all* floating point insns (except ld/st).
r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
Gavin Romig-Koch
f319bab251 * interp.c (load_memory): Add missing "break"'s. 1998-02-19 15:24:10 +00:00
Ron Unrau
7aa6042f58 configure: rerun autoconf
interp.c: shield dummy vu registers with -DTARGET_SKY
1998-02-16 04:33:28 +00:00
Ron Unrau
97908603a4 configure.in: add -DTARGET_SKY for mips64r5900-sky-elf configure.
sim-main.h: Define regs for sky if -DTARGET_SKY
interp.c: Initial register upload/download support for sky.
1998-02-15 21:33:13 +00:00
Ian Carmichael
2c88fae9ad * Add hardware_init hook. 1998-02-09 23:53:33 +00:00
Andrew Cagney
37379a256b IGEN - Replace IMEM (IMEM_IMMED) macro with IMEM<insn-size> macro,
update v850, tic80 and mips simulators.
IGEN - Prepend prefix to more generated symbols and macros
(idecode_issue, instruction_word).
IGEN - Add -Wnowith option to supress warnings about word size
inflicts in input files.
MIPS - Clean up Makefile.in, m16.igen, m16.dc (new), m16run.c (new) so
that a mips16 simulator built using IGEN can be compiled.
1998-02-03 05:39:15 +00:00
Andrew Cagney
a97f304b04 Add support for configuring the size of the floating point unit (fp_word).
For mips, move fp_registers into a separate array of type fp_word[].
1998-02-02 14:06:52 +00:00
Andrew Cagney
2acd126a47 Rewrite the mipsI/II/III pending-slot code. 1998-02-02 13:49:17 +00:00
Andrew Cagney
192ae475f9 Always compile FP code (test for FP at run-time).
Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
Andrew Cagney
01737f42d8 mips: Add multi-processor support for r5900. Others might work.
common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
Andrew Cagney
9ec6741b17 igen: Fix SMP simulator generator support.
Use the bfd-processor name in the sim-engine switch.
	Add nr_cpus argument to sim_engine_run.
tic80, v850, d30v, mips, common:
	Update
mips:	Fill in bfd-processor field of model records so that
	they match ../bfd/archures.
1998-01-31 06:23:41 +00:00
Mark Alexander
e0e0fc765e * interp.c (sim_monitor): Handle Densan monitor outbyte
and inbyte functions.
1998-01-05 23:43:30 +00:00
Felix Lee
76ef416550 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c). 1997-12-29 16:03:23 +00:00
Andrew Cagney
232156dee9 o Add SIM_SIGFPE to sim-signals
o Start SIM_SIG* at 64 so that the use of host signal numbers can be
  detected and reported.
o Update MIPS simulator to use sim-signal.
1997-11-20 09:50:36 +00:00
Andrew Cagney
a09a30d298 Allow reads/writes to C0_CONFIG register. 1997-11-20 09:17:06 +00:00
Andrew Cagney
030843d7f8 Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1,
SWXC1MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1, MULT, MULTU, BEQZ, ...MTHI,
MFHI instructions.
Trace nullified instruction.
1997-11-11 07:50:13 +00:00
Andrew Cagney
95469cebdd Replace global IPC with function argument cia or current instruction
address.
Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
Andrew Cagney
7ce8b9178c IGEN likes to cache the current instruction address (CIA). Change the
MIPS simulator so that correctly writes the value of CIA back int PC
(the global previously used) when the simulation halts.
Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-06 09:16:16 +00:00
Andrew Cagney
63be8febf7 Rewrite the MIPS simulator's memory model so that it uses the generic
common/sim-core.

Add support for 3, 5, 6, 7 byte transfers to sim core.
1997-11-05 08:17:26 +00:00
Andrew Cagney
22de994d0e Delete -l and -n options, didn't do anything.
Rename option trace to dinero-trace & dinero-file - -t clashed with
common options.
Enable common trace options.
1997-11-05 01:08:12 +00:00
Andrew Cagney
525d929e49 Rewrite sim_monitor (implements read, write, open, et.al. system
calls) and sim_open so that they uses the virtual memory data transfer
functions sim_read & sim_write.  This eliminates all code (other than
in load_memory & store_memory) that makes assumptions about the
implementation of the underlying memory model.
1997-11-05 00:08:14 +00:00
Gavin Romig-Koch
0425cfb3af Correct r5900 sanitization. 1997-11-04 05:50:22 +00:00
Andrew Cagney
16bd5d6e52 Separate r5900 specifoc and mips16 instructions.
Add support for this to configure (vr5400 target only)
1997-10-27 07:55:24 +00:00
Andrew Cagney
dad6f1f326 Add function to fetch 32bit instructions
When address translation of insn fetch fails raise exception immediatly.
Use address_word as type of all address variables (instead of unsigned64),
the former is configured as either 32 or 64 bit type.
Always compile fpu code (no #if has fpu)
1997-10-24 06:43:51 +00:00
Andrew Cagney
aa324b9b1e Output pc profile statistics once gathered. 1997-10-21 07:40:00 +00:00
Andrew Cagney
e2f8ffb736 Delete profile support from MIPS simulator, use sim/common/sim-profile
module instead.
Generate a "gmon.out" (gprof) when profiling the target PC.
Add target PC profiling option --profile-pc-granularity (bucket size)
1997-10-21 03:41:21 +00:00
Andrew Cagney
fb5a2a3e39 Make mips registers of type unsigned_word.
Ensure all references to MIPS registers use same type.
1997-10-20 06:28:53 +00:00
Andrew Cagney
ea985d2472 Move register definitions and macros out of interp.c and into sim-main.h 1997-10-16 03:50:48 +00:00
Andrew Cagney
284e759d1f Rename generated file engine.c to oengine.c. 1997-10-16 03:39:13 +00:00
Andrew Cagney
0c2c5f6141 Move global MIPS simulator variables into sim_cpu struct. 1997-10-14 09:26:03 +00:00
Andrew Cagney
18c64df613 o Add support for configuring wordsize, fp hardware and target
endianness.  Provide defaults for some tier-1 mips targets.
o	Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
Mark Alexander
6eedf3f4e5 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB. 1997-09-26 20:56:55 +00:00
Gavin Romig-Koch
9cb8397f86 * sim/mips/interp.c: Correct some HASFPU problems. 1997-09-16 15:36:18 +00:00
Andrew Cagney
11ac69e013 Short form of sample-size option had wrong value. 1997-09-12 02:29:04 +00:00
Andrew Cagney
972f3a34f5 mips/sim_info was just returning????? 1997-09-10 23:50:32 +00:00
Andrew Cagney
9eeaaefa0f Better word error messages. 1997-09-09 10:38:39 +00:00
Andrew Cagney
fafce69ab1 Add ABFD argument to sim_create_inferior. Document.
Add file sim-hload.c - generic load for hardware only simulators.
Review each simulators sim_open, sim_load, sim_create_inferior so that
they more closely match required behavour.
1997-08-27 04:44:41 +00:00