Commit graph

170 commits

Author SHA1 Message Date
Andrew Cagney
92f91d1ff0 Remove need to update <targ>/Makefile.in when adding optional options
to <targ>/configure.in.
Simplify logic used to select target [default] endianness.
1997-09-23 01:25:26 +00:00
Andrew Cagney
794e9ac96a Simplify logic behind the generic configuration option --enable-sim-alignment. 1997-09-22 02:49:57 +00:00
Andrew Cagney
b45caf050c Add support for --enable-sim-alignment to simulator common aclocal.m4
Add support for --alignment={strict,nonstrict,forced} to simulator common
run-time options.
For v850 use, make the default NONSTRICT_ALIGNMENT.
1997-09-22 00:24:46 +00:00
David Edelsohn
6fea47635b * configure: Regenerated to track ../common/aclocal.m4 changes. 1997-09-05 00:42:05 +00:00
Andrew Cagney
8811705410 Fix doco on enable-sim-inline. 1997-08-27 22:43:18 +00:00
Andrew Cagney
fafce69ab1 Add ABFD argument to sim_create_inferior. Document.
Add file sim-hload.c - generic load for hardware only simulators.
Review each simulators sim_open, sim_load, sim_create_inferior so that
they more closely match required behavour.
1997-08-27 04:44:41 +00:00
Andrew Cagney
7230ff0faa Flush defunct sim_kill. 1997-08-26 02:05:18 +00:00
Andrew Cagney
247fccdeb5 Add ABFD argument to sim_open call. Pass through to sim_config so
that image properties such as endianness can be checked.

More strongly document the expected behavour of each of the sim_*
interfaces.

Add default endian argument to simulator config macro
SIM_AC_OPTION_ENDIAN.  Use in sim_config.
1997-08-25 23:14:25 +00:00
Jeff Law
c370b3cd95 * simops.c: Fix thinko in last change. 1997-06-12 04:14:42 +00:00
Jeff Law
dbdb5bd881 * simops.c: "call" stores the callee saved registers into the
stack!  Update the stack pointer properly when done with
        register saves.
1997-06-10 22:59:13 +00:00
Jeff Law
0a8fa63cb8 * simops.c: Fix return address computation for "call" instructions. 1997-06-10 18:32:40 +00:00
Jeff Law
09e142d5a2 * interp.c (sim_resume): Add missing case in big switch
statement (for extb instruction).
1997-05-22 05:28:34 +00:00
Jeff Law
003c91bec4 * interp.c: Replace all references to load_mem and store_mem
with references to load_byte, load_half, load_3_byte, load_word
        and store_byte, store_half, store_3_byte, store_word.
        (INLINE): Delete definition.
        (load_mem_big): Likewise.
        (max_mem): Make it global.
        (dispatch): Make this function inline.
        (load_mem, store_mem): Delete functions.
        * mn10300_sim.h (INLINE): Define.
        (RLW): Delete unused definition.
        (load_mem, store_mem): Delete declarations.
        (load_mem_big): New definition.
        (load_byte, load_half, load_3_byte, load_word): New functions.
        (store_byte, store_half, store_3_byte, store_word): New functions.
        * simops.c:  Replace all references to load_mem and store_mem
        with references to load_byte, load_half, load_3_byte, load_word
        and store_byte, store_half, store_3_byte, store_word.
1997-05-20 23:53:47 +00:00
Jeff Law
4df7aeb3c5 * interp.c (dispatch): Make this an inline function.
* simops.c (syscall): Use callback->write regardless of
        what file descriptor we're writing too.
1997-05-19 19:55:31 +00:00
Jeff Law
b07a1e78c5 * interp.c (load_mem_big): Remove function. It's now a macro
defined elsewhere.
        (compare_simops): New function.
        (sim_open): Sort the Simops table before inserting entries
        into the hash table.
        * mn10300_sim.h: Remove unused #defines.
        (load_mem_big): Define.
Another 20% so performance improvement for the mn10300 simulator.
1997-05-18 22:57:49 +00:00
Jeff Law
234a9a49cf * interp.c (load_mem): If we get a load from an out of range
address, abort.
        (store_mem): Likewise for stores.
        (max_mem): New variable.
1997-05-16 22:37:02 +00:00
Jeff Law
8def922034 * mn10300_sim.h: Fix ordering of bits in the PSW. 1997-05-06 19:42:17 +00:00
Jeff Law
baa83bcc80 * interp.c: Improve hashing routine to avoid long list
traversals for common instructions.  Add HASH_STAT support.
        Rewrite opcode dispatch code using a big switch instead of
        cascaded if/else statements.  Avoid useless calls to load_mem.
1997-05-06 19:27:22 +00:00
Jeff Law
26e9f63c11 * mn10300_sim.h (struct _state): Add space for mdrq register.
(REG_MDRQ): Define.
        * simops.c: Don't abort for trap.  Add support for the extended
        instructions, "getx", "putx", "mulq", "mulqu", "sat16", "sat24",
        and "bsch".
1997-05-06 00:35:42 +00:00
Andrew Cagney
8517f62b16 Ref gdb/11763 - can't stop a running simulator:
o	Provide poll_quit callback to simulators
		so that they can poll for SIGINT on
		clueless OS's.

	o	Add sim_stop to simulators so that clients
		can request a halt (eg gdbtk's STOP button)
		Works for PPC!

	o	Re-arange remote-sim.c so that the
		hard work is moved from gdbsim_resume()
		to gdbsim_wait() (where it should be).
1997-04-18 12:24:52 +00:00
David Edelsohn
6cc6987e1e * Makefile.in (SIM_OBJS): Add sim-load.o.
* interp.c (sim_kind, myname): New static locals.
	(sim_open): Set sim_kind, myname.  Ignore -E arg.
	(sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
	load file into simulator.  Set start address from bfd.
	(sim_create_inferior): Return SIM_RC.  Delete arg start_address.
1997-04-17 10:27:47 +00:00
Andrew Cagney
87e43259f1 Cleanups to compile under FreeBSD 1997-04-17 06:05:19 +00:00
Andrew Cagney
08db4a658e Get configure to define RETSIGTYPE 1997-04-07 05:58:59 +00:00
Ian Lance Taylor
ea553f5643 * Makefile.in: Change mn10300-opc.o to m10300-opc.o, to match
corresponding change in opcodes directory.
1997-04-05 01:03:01 +00:00
David Edelsohn
8a7c3105b5 * interp.c (sim_open): New arg `kind'. 1997-04-02 23:39:50 +00:00
David Edelsohn
fbda74b1c1 * aclocal.m4: Check for stdlib.h, string.h, strings.h, unistd.h.
(sim-debug): Allow arguments.  Define WITH_DEBUG in addition to
	-DDEBUG.
	* configure: Regenerated to track ../common/aclocal.m4 changes.
1997-04-02 23:17:50 +00:00
Andrew Cagney
a35e91c3c7 New file common/sim-config.c sets/checks simulator configuration options.
Update common/aclocal.m4 to better work with sim-config.[hc].
1997-04-02 05:04:25 +00:00
Andrew Cagney
c695046ac9 Move SIM_AC_OPTION_ macros out of SIM_AC_COMMON macro - was trashing
optional arguments.
* Regenerate all configure scripts.
1997-03-18 14:28:34 +00:00
Andrew Cagney
a77aa7ec4b * configure: Re-generate.
* Make-common.in (CSEARCH): Do not include the gdb directory in
        the search path.
        * Make-common.in (SIM_ENDIAN, SIM_HOSTENDIAN, SIM_INLINE,
        SIM_WARNING): Drop, requiring the simulator specific Makefile.in
        to explicitly incorporate these.

        * aclocal.m4 (--enable-sim-alignment); New option. Strongly
        specify the alignment restrictions of the target architecture -
        without this option all alignment restrictions are accomodated.
        (--enable-sim-assert): New option.  Conditionally compile in
        assertion statements.
        (--enable-sim-float): New option. Strongly specify the target's
        floating point support.
        (--enable-sim-hardware): New option.  Specify the hardware devices
        included in the simulation.
        (--enable-sim-packages): New option.  Specify the hardware
        packages included in the simulation.
        (--enable-sim-regparm): New option.  Specify that parameters be
        passed in registers instead of on the stack.
        (--enable-sim-reserved-bits): New option. Specify that reserved
        bits within an instruction are are correctly set.
        (--enable-sim-smp): New option. Specify the level of SMP support
        to be included in the simulator.
        (--enable-sim-stdcall): New option.  Specify an alternative
        function call convention.
        (--enable-sim-xor-endian): New option.  Configure xor-endian
        support used by some targets to implement bi-endian support.
1997-03-17 15:29:29 +00:00
Michael Meissner
601fb8aea6 Regenerate simulator configure scripts; Remove d10v traps 1-3, Make 15 the system call trap, keeping 0 temporarily 1997-03-14 16:21:57 +00:00
David Edelsohn
53b9417eb3 * interp.c (sim_open): New SIM_DESC result. Argument is now
in argv form.
	(other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
Jeff Law
0ade484f98 * simops.c: Fix carry bit computation for "add" instructions.
More bugs exposed by new mn10300 compiler optimizations.
1997-03-12 22:20:13 +00:00
Jeff Law
09eef8af93 * simops.c: Fix typos in bset insns. Fix arguments to store_mem
for bset imm8,(d8,an) and bclr imm8,(d8,an).
Bugs exposed by new compiler optimizations.
1997-03-12 22:05:49 +00:00
Jeff Law
018f9eb41f * interp.c (init_system): Allocate 2^19 bytes of space for the
simulator.
To match the linker.
1997-01-24 17:48:35 +00:00
Stu Grossman
295dbbe44c * configure configure.in Makefile.in: Update to new configure
scheme which is more compatible with WinGDB builds.
	* configure.in:  Improve comment on how to run autoconf.
	* configure:  Re-run autoconf to get new ../common/aclocal.m4.
	* Makefile.in:  Use autoconf substitution to install common
	makefile fragment.
1997-01-23 22:09:52 +00:00
Jeff Law
f95251f068 * simops.c: Undo last change to "rol" and "ror", original code
was correct!
1997-01-21 22:03:39 +00:00
Jeff Law
b4b290a020 * simops.c: Fix "rol" and "ror".
Something I noticed while working on the mn10200.
1997-01-16 18:28:46 +00:00
Jeff Law
2da0bc1bf9 * simops.c: Use REG macros in few places not using them yet.
Something I noticed while working on the mn10200 simulator.
1997-01-13 20:28:37 +00:00
Jeff Law
bbd1706224 * mn10300_sim.h (struct _state): Fix number of registers!
Just something I noticed while working on the mn10200 simulator.
1997-01-06 23:25:53 +00:00
Jeff Law
b774c0e4b1 * mn10300_sim.h (struct _state): Put all registers into a single
array to make gdb implementation easier.
        (REG_*): Add definitions for all registers in the state array.
        (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
        * simops.c: Related changes.
1996-12-31 23:26:11 +00:00
Jeff Law
d657034d38 * interp.c (sim_resume): Handle 0xff as a single byte insn.
* simops.c: Fix overflow computation for "add" and "inc"
        instructions.
1996-12-18 17:15:21 +00:00
Jeff Law
093e9a32d3 * simops.c: Handle "break" instruction. 1996-12-16 22:31:37 +00:00
Jeff Law
16d2e2b670 * simops.c: Fix restoring the PC for "ret" and "retf" instructions. 1996-12-16 17:08:10 +00:00
Jeff Law
95d18eb74d * simops.c (REG0_4): Define.
Use REG0_4 for indexed loads/stores.
Fixes bugs exposed after minor codegen improvements in the compiler.
1996-12-10 22:10:07 +00:00
Jeff Law
2e8f4133d7 * simops.c (REG0_16): Fix typo. 1996-12-07 16:54:57 +00:00
Jeff Law
b2f7a7e5b3 * simops.c: Call abort for any instruction that's not currently
simulated.
1996-12-06 21:49:27 +00:00
Jeff Law
9f4a551e11 * simops.c: Define accessor macros to extract register
values from instructions.  Use them consistently.
1996-12-06 21:47:21 +00:00
Jeff Law
7c52bf32f2 * interp.c: Delete unused global variable "OP".
(sim_resume): Remove unused variable "opcode".
        * simops.c: Fix some uninitialized variable problems, add
        parens to fix various -Wall warnings.
Fixing assorted -Wall problems.
1996-12-06 21:33:48 +00:00
Jeff Law
d252301029 * gencode.c (write_header): Add "insn" and "extension" arguments
to the OP_* declarations.
        (write_template): Similarly for function templates.
        * interp.c (insn, extension): Remove global variables.  Instead
        pass them as arguments to the OP_* functions.
        * mn10300_sim.h: Remove decls for "insn" and "extension".
        * simops.c (OP_*): Accept "insn" and "extension" as arguments
        instead of using globals.
Starting to clean things up.
1996-12-06 21:19:37 +00:00
Jeff Law
e5a7a53799 * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
Fixes remaining hangs while running c-torture execution tests.
Only 12 c-torture execution failures left:

  * 920625-1.c fails all 6 execution tests.

  * 960521-1.c fails all 6 execution tests.
1996-12-06 07:57:21 +00:00
Jeff Law
4d8ced6cb1 * simops.c: Fix thinkos in last change to "inc dn". 1996-12-06 05:30:24 +00:00
Jeff Law
61ecca95c0 * simops.c: "add imm,sp" does not effect the condition codes.
"inc dn" does effect the condition codes.
Just something I noticed.
1996-12-04 18:02:00 +00:00
Jeff Law
e4e1302293 * simops.c: Treat both operands as signed values for
"div" instruction.
Fixes another dozen c-torture execution failures.
1996-12-04 05:00:49 +00:00
Jeff Law
fcfaf40d78 * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
Fixes 80 or so c-torture execution failures.  400 to go.
1996-12-02 19:35:55 +00:00
Jeff Law
b7b89deb44 * simops.c: Fix overflow computation for many instructions.
Fixes several hangs in the c-torture execution tests.  Also fixes about
40 failures.
1996-12-02 08:35:20 +00:00
Jeff Law
af388638ae * simops.c: Fix "movdm, an", "movbu dm, (an)", and "movhu dm, (an)".
Along with some compiler, bfd, assembler changes this fixes 90 or so
c-torture execution failures.
1996-12-02 07:38:10 +00:00
Jeff Law
c8f0171f5f * simops.c: Fix "mov am, dn".
Fixes more c-torture problems.
1996-12-02 04:23:37 +00:00
Jeff Law
6db7fc49d2 * simops.c: Fix more bugs in "add imm,an" and
"add imm,dn".
Fixes a half-dozen (of several hundred :( c-torture failures.
1996-12-01 23:10:04 +00:00
Jeff Law
6e7a01c144 * simops.c: Fix bugs in "movm" and "add imm,an".
main(){write (0, "hello world\n", 13);} works!
1996-11-27 23:20:24 +00:00
Jeff Law
3bb3fe44e0 * simops.c: Don't lose the upper 24 bits of the return
pointer in "call" and "calls" instructions.  Rough cut
        at emulated system calls.
1996-11-27 18:36:54 +00:00
Jeff Law
de0dce7c5c * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
Everything except the extended instructions, the loop instructions,
trap, rti, and rtm.
1996-11-27 17:56:10 +00:00
Jeff Law
ecb4b5a357 * simops.c Implement remaining 4 byte instructions. 1996-11-27 17:19:44 +00:00
Jeff Law
2e35551c74 * simops.c Implement remaining 3 byte instructions.
Moving right along...
1996-11-27 16:51:30 +00:00
Jeff Law
f5f13c1d73 * simops.c: Implement remaining 2 byte instructions. Call
abort for instructions we're not implementing now.
1996-11-27 16:25:03 +00:00
Jeff Law
707641f658 * simops.c: Implement lots of random instructions.
Implments most instructions with first nibble 0x0 - 0xe and
those with the first byte 0xf0 - 0xf2.
1996-11-27 07:20:36 +00:00
Jeff Law
1f3bea2169 * simops.c: Implement "movm" and "bCC" insns.
Function calls and conditional branches work!
1996-11-27 05:29:49 +00:00
Jeff Law
92284aaa35 * mn10300_sim.h (_state): Add another register (MDR).
(REG_MDR): Define.
        * simops.c: Implement "cmp", "calls", "rets", "jmp" and
        a few additional random insns.
We can now function calls.  We get out of crt0 into main now, then lose
when calls are nested (because don't handle movm yet).
1996-11-27 00:53:25 +00:00
Jeff Law
73e6529893 * mn10300_sim.h (PSW_*): Define for CC status tracking.
(REG_D0, REG_A0, REG_SP): Define.
        * simops.c: Implement "add", "addc" and a few other random
        instructions.
Starting to simulate instructions for the mn10300.  Executes some of
the crt0 code now!
1996-11-26 22:58:24 +00:00
Jeff Law
b5f831ac51 * gencode.c, interp.c: Snapshot current simulator code.
(crude) hashing works, along with dispatch to the OP_* functions.
1996-11-26 20:40:19 +00:00
Jeff Law
05ccbdfdd2 * Makefile.in, config.in, configure, configure.in: New files.
* gencode.c, interp.c, mn10300_sim.h, simops.c: New files.

Skeleton mn10300 simulator
1996-11-25 19:52:08 +00:00