200 lines
6.2 KiB
Text
200 lines
6.2 KiB
Text
Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
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* configure: Regenerate to track ../common/aclocal.m4 changes.
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Thu Mar 13 12:54:45 1997 Doug Evans <dje@canuck.cygnus.com>
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* interp.c (sim_open): New SIM_DESC result. Argument is now
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in argv form.
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(other sim_*): New SIM_DESC argument.
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Wed Mar 12 15:04:00 1997 Jeffrey A Law (law@cygnus.com)
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* simops.c: Fix carry bit computation for "add" instructions.
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* simops.c: Fix typos in bset insns. Fix arguments to store_mem
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for bset imm8,(d8,an) and bclr imm8,(d8,an).
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Wed Mar 5 15:00:10 1997 Jeffrey A Law (law@cygnus.com)
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* simops.c: Fix register references when computing Z and N bits
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for lsr imm8,dn.
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Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
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* Makefile.in (@COMMON_MAKEFILE_FRAG): Use
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COMMON_{PRE,POST}_CONFIG_FRAG instead.
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* configure.in: sinclude ../common/aclocal.m4.
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* configure: Regenerated.
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Fri Jan 24 10:47:25 1997 Jeffrey A Law (law@cygnus.com)
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* interp.c (init_system): Allocate 2^19 bytes of space for the
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simulator.
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Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
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* configure configure.in Makefile.in: Update to new configure
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scheme which is more compatible with WinGDB builds.
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* configure.in: Improve comment on how to run autoconf.
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* configure: Re-run autoconf to get new ../common/aclocal.m4.
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* Makefile.in: Use autoconf substitution to install common
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makefile fragment.
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Tue Jan 21 15:03:04 1997 Jeffrey A Law (law@cygnus.com)
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* simops.c: Undo last change to "rol" and "ror", original code
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was correct!
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Thu Jan 16 11:28:14 1997 Jeffrey A Law (law@cygnus.com)
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* simops.c: Fix "rol" and "ror".
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Wed Jan 15 06:45:58 1997 Jeffrey A Law (law@cygnus.com)
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* simops.c: Fix typo in last change.
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Mon Jan 13 13:22:35 1997 Jeffrey A Law (law@cygnus.com)
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* simops.c: Use REG macros in few places not using them yet.
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Mon Jan 6 16:21:19 1997 Jeffrey A Law (law@cygnus.com)
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* mn10300_sim.h (struct _state): Fix number of registers!
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Tue Dec 31 16:20:41 1996 Jeffrey A Law (law@cygnus.com)
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* mn10300_sim.h (struct _state): Put all registers into a single
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array to make gdb implementation easier.
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(REG_*): Add definitions for all registers in the state array.
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(SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
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* simops.c: Related changes.
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Wed Dec 18 10:10:45 1996 Jeffrey A Law (law@cygnus.com)
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* interp.c (sim_resume): Handle 0xff as a single byte insn.
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* simops.c: Fix overflow computation for "add" and "inc"
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instructions.
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Mon Dec 16 10:03:52 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Handle "break" instruction.
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* simops.c: Fix restoring the PC for "ret" and "retf" instructions.
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Wed Dec 11 09:53:10 1996 Jeffrey A Law (law@cygnus.com)
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* gencode.c (write_opcodes): Also write out the format of the
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opcode.
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* mn10300_sim.h (simops): Add "format" field.
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* interp.c (sim_resume): Deal with endianness issues here.
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Tue Dec 10 15:05:37 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c (REG0_4): Define.
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Use REG0_4 for indexed loads/stores.
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Sat Dec 7 09:50:28 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c (REG0_16): Fix typo.
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Fri Dec 6 14:13:34 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Call abort for any instruction that's not currently
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simulated.
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* simops.c: Define accessor macros to extract register
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values from instructions. Use them consistently.
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* interp.c: Delete unused global variable "OP".
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(sim_resume): Remove unused variable "opcode".
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* simops.c: Fix some uninitialized variable problems, add
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parens to fix various -Wall warnings.
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* gencode.c (write_header): Add "insn" and "extension" arguments
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to the OP_* declarations.
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(write_template): Similarly for function templates.
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* interp.c (insn, extension): Remove global variables. Instead
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pass them as arguments to the OP_* functions.
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* mn10300_sim.h: Remove decls for "insn" and "extension".
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* simops.c (OP_*): Accept "insn" and "extension" as arguments
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instead of using globals.
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Thu Dec 5 22:26:31 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
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* simops.c: Fix thinkos in last change to "inc dn".
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Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: "add imm,sp" does not effect the condition codes.
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"inc dn" does effect the condition codes.
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Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Treat both operands as signed values for
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"div" instruction.
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* simops.c: Fix simulation of division instructions.
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Fix typos/thinkos in several "cmp" and "sub" instructions.
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Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Fix carry bit handling in "sub" and "cmp"
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instructions.
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* simops.c: Fix "mov imm8,an" and "mov imm16,dn".
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Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Fix overflow computation for many instructions.
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* simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
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* simops.c: Fix "mov am, dn".
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* simops.c: Fix more bugs in "add imm,an" and
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"add imm,dn".
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Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Fix bugs in "movm" and "add imm,an".
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* simops.c: Don't lose the upper 24 bits of the return
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pointer in "call" and "calls" instructions. Rough cut
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at emulated system calls.
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* simops.c: Implement the remaining 5, 6 and 7 byte instructions.
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* simops.c: Implement remaining 4 byte instructions.
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* simops.c: Implement remaining 3 byte instructions.
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* simops.c: Implement remaining 2 byte instructions. Call
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abort for instructions we're not implementing now.
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Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Implement lots of random instructions.
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* simops.c: Implement "movm" and "bCC" insns.
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* mn10300_sim.h (_state): Add another register (MDR).
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(REG_MDR): Define.
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* simops.c: Implement "cmp", "calls", "rets", "jmp" and
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a few additional random insns.
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* mn10300_sim.h (PSW_*): Define for CC status tracking.
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(REG_D0, REG_A0, REG_SP): Define.
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* simops.c: Implement "add", "addc" and a few other random
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instructions.
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* gencode.c, interp.c: Snapshot current simulator code.
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Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com)
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* Makefile.in, config.in, configure, configure.in: New files.
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* gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
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