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1039 commits

Author SHA1 Message Date
Fred Fish
b83093ff79 * simops.c (OP_6401): postdecrement on r15 is OK, remove exception. 
(OP_6601): Ditto.
PR 13498
 1997-10-11 16:50:05 +00:00
Fred Fish
93f0cb6975 * simops.c (OP_6401): postdecrement on r15 is OK, remove exception. 
(OP_6601): Ditto.
 1997-10-11 16:48:47 +00:00
Andrew Cagney
49a6eed58a Snap. Gets through igen's checks. 1997-10-09 08:38:22 +00:00
Andrew Cagney
8782bfcfc4 Add -Wnodiscard option so that warning about discarded instructions 
can be suppressed.
Allow ``<insn-spec> { <nmemonic> | <model> }'' in instruction file.
 1997-10-09 08:35:33 +00:00
Andrew Cagney
2875c6c685 Build IGEN with the MIPS simulator. 1997-10-09 00:41:14 +00:00
Andrew Cagney
f2b3001251 MIPS/IGEN checkpoint - doesn't build. 1997-10-08 04:16:01 +00:00
Andrew Cagney
391c71708e Checkpoint IGEN input file for MIPS simulator. 1997-10-07 08:45:11 +00:00
Andrew Cagney
b3c77578dc Rewrite simulator floating point module. Do not rely on host FP 
implementation.  Add preliminary support for different IEEE-754
rounding modes.  Implement SQRT in software.
Update TiC80 simulator.
Add sim-fpu -> TestFloat interface for testing.
 1997-10-03 00:03:35 +00:00
Andrew Cagney
63fe2cc799 Fix typo, WITH_TARGET_WORD_BITSIZE not WITH_TARGET_BITSIZE. 1997-10-02 23:37:30 +00:00
Andrew Cagney
adf4739efe Add access to hi part of r5900 128 bit registers. 1997-09-30 03:45:51 +00:00
Bob Manson
26b20b0a0e * configure: Regenerated. 
Can't hack one without the other...
 1997-09-29 21:46:32 +00:00
Andrew Cagney
e9b53280ba Do not sanitize out sim/testsuite/common directory. 1997-09-29 00:24:08 +00:00
Fred Fish
5f90b21e40 * d10v_sim.h (INC_ADDR): Align MOD_E to increment before testing 
for end condition.
PR 13334
 1997-09-27 20:04:22 +00:00
Fred Fish
823f2df47f * interp.c (pc_addr): Discard upper bit(s) of PC in case 
IMAP1 selects unified memory.
PR 13275
 1997-09-27 19:57:05 +00:00
Mark Alexander
6eedf3f4e5 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB. 1997-09-26 20:56:55 +00:00
Felix Lee
b28ad90b4d * sim-main.h: delete null override of SIM_ENGINE_HALT_HOOK and 
SIM_ENGINE_RESTART_HOOK.
 1997-09-26 19:24:45 +00:00
Stu Grossman
68f92f98ac * sim-break.c (sim_set_breakpoint sim_clear_breakpoint): Use ZALLOC 
and zfree instead of xmalloc and free.  Prevents warnings.
 1997-09-25 18:22:46 +00:00
Andrew Cagney
af51b8d56d Add/use SIM_AC_OPTION_BITSIZE. 1997-09-25 07:19:05 +00:00
Andrew Cagney
7a3fb4e6ea * config/v850/tm-v850.h (BREAKPOINT): Use 1 word DIVH insn with 
RRRRR=0 for simulator breakpoint. Previous breakpoint insn was two
words.
 1997-09-25 07:01:21 +00:00
Andrew Cagney
e63bc706fe Allow gencode.c to generate input to the igen generator. 1997-09-25 04:23:24 +00:00
Andrew Cagney
eb2e3c85ca Pacify GCC -Wall 1997-09-25 04:13:50 +00:00
Stu Grossman
b9d580a4b0 * Make-common.in: New files sim-break.c, sim-break.h. 
* sim-base.h:  Add point to breakpoint list to sim_state_base.
	* sim-break.c sim-break.h:  New modules that implement intrinsic
	breakpoint support.
	* sim-module.c:  Add breakpoint module.
 1997-09-25 00:51:17 +00:00
Jeff Law
bfebf1a52a r5900 sanitization fixes. 1997-09-24 07:27:43 +00:00
Jeff Law
c118539e6b mips64vr5900el-elf -> mips64r5900-elf. 1997-09-23 21:45:43 +00:00
Felix Lee
34d07b7867 * sim-events.c (SIM_EVENTS_POLL_RATE): poll more often than once 
an hour.
        * sim-n-core.h (WITH_XOR_ENDIAN): MSVC barfs on
        if (0) { 1 % 0; }
        * sim-core.c (sim_core_xor_write_buffer): WITH_XOR_ENDIAN + 1.
        (SIGBUS) define for Windows.
        * sim-trace.c (trace_printf,debug_printf): added ALMOST_STDC.
        * sim-resume.c: define SIGTRAP for windows.
        * sim-xcat.h: use token pasting if ALMOST_STDC.
 1997-09-23 18:08:09 +00:00
Jeff Law
832f05e865 vr5900-r5900. 1997-09-23 16:21:23 +00:00
Andrew Cagney
1398204eb0 Check v850eq popm[hl] instructions. 
Check v850 NMI/RETI.
 1997-09-23 08:40:55 +00:00
Andrew Cagney
4141b1c63d * Make-common.in (SIM_SCACHE, SIM_DEFAULT_MODEL): Assign configured values. 
(CONFIG_CFLAGS): Add same.
 1997-09-23 04:05:50 +00:00
Felix Lee
9f4fd82344 * sim-types.h (SIGNED64): ##i64 when _MSC_VER, not _WIN32. 
(SIGNED32): use ##i32.
 1997-09-23 03:51:33 +00:00
Felix Lee
8f80453197 * configure.in: i386-windows is a cross, so don't expect 
libiberty to be there.
	* configure: updated.
 1997-09-23 03:48:59 +00:00
Andrew Cagney
92f91d1ff0 Remove need to update <targ>/Makefile.in when adding optional options 
to <targ>/configure.in.
Simplify logic used to select target [default] endianness.
 1997-09-23 01:25:26 +00:00
Andrew Cagney
76a6247f07 Add memory alignment config option. 1997-09-22 09:40:57 +00:00
Andrew Cagney
8d332f9c1a Enable --alignment option, stop sim-options.c hardwiring the alignment. 1997-09-22 09:34:28 +00:00
Andrew Cagney
4ca7d6d25b Fix disabling of model code when simulator does not support modeling. 
Stops `-p' crashing simulators.
 1997-09-22 09:16:14 +00:00
Andrew Cagney
794e9ac96a Simplify logic behind the generic configuration option --enable-sim-alignment. 1997-09-22 02:49:57 +00:00
Andrew Cagney
b45caf050c Add support for --enable-sim-alignment to simulator common aclocal.m4 
Add support for --alignment={strict,nonstrict,forced} to simulator common
run-time options.
For v850 use, make the default NONSTRICT_ALIGNMENT.
 1997-09-22 00:24:46 +00:00
Nick Clifton
f13f11b494 Removed the v850eq sanitization 1997-09-20 23:40:50 +00:00
Gavin Romig-Koch
c476ac5560 Add handling for 3900's SDBBP, DERET, and RFE insns. 
* gencode.c (SDBBP,DERET): Added (3900) insns.
	(RFE): Turn on for 3900.
	* interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
	(dsstate): Made global.
	(SUBTARGET_R3900): Added.
	(CANCELDELAYSLOT): New.
	(SignalException): Ignore SystemCall rather than ignore and
	terminate.  Add DebugBreakPoint handling.
	(decode_coproc): New insns RFE, DERET; and new registers Debug
	and DEPC protected by SUBTARGET_R3900.
	(sim_engine_run): Use CANCELDELAYSLOT rather than clearing
	bits explicitly.
	* Makefile.in,configure.in: Add mips subtarget option.
	* configure: Update.
 1997-09-20 18:22:22 +00:00
Gavin Romig-Koch
7afa8d4edc * gencode.c: Add r3900 (tx39). 
* gencode.c: Fix some configuration problems by improving
	the relationship between tx19 and tx39.
 1997-09-19 13:39:55 +00:00
Andrew Cagney
8122e3e471 Add alignment option. 
Add support for hardwired and default alignment to configuration.
 1997-09-19 08:11:40 +00:00
Andrew Cagney
f4822f1e6e More tests. 
Have sld check verify that the processor is a v850eq.
 1997-09-19 06:40:11 +00:00
Andrew Cagney
a276b6f057 Clean up tracing for Bcond & jmp insns. 
Fix computation of disp16 and disp22.
Clean up tracing of sld* insns.
 1997-09-19 06:39:21 +00:00
Andrew Cagney
4410c4b925 Correctly locate `_' in generated names. 1997-09-19 04:41:01 +00:00
Andrew Cagney
bd4c35cc6d Fix cmov immed. 1997-09-19 02:20:02 +00:00
Andrew Cagney
6a4c8f1e29 Change semantic function name to semantic_<INSN>_<FMT> instead of 
semantic_<FMT>_<INSN>.
 1997-09-19 00:50:24 +00:00
Andrew Cagney
60fe0e06a8 Fix cmov insn. 1997-09-19 00:50:19 +00:00
Felix Lee
3e906c081a sanitization fixes. typoes, missing fences, "start" instead of "end", etc. 1997-09-18 06:03:52 +00:00
Felix Lee
88770c1c90 add missing files. 1997-09-18 04:56:22 +00:00
Felix Lee
e1625ed217 v850 files that weren't being removed if !keep-v850 1997-09-18 01:33:24 +00:00
Felix Lee
2001e533ff * sim-main.h (kill): macro was missing args. 
(SIGTRAP): define for MSVC.
 1997-09-17 23:46:49 +00:00
Andrew Cagney
8bd89725a7 Test US bit of v850eq. 
Loop program for testing interrupt delivery.
 1997-09-17 13:46:29 +00:00
Andrew Cagney
a72f8fb439 Clean up more tracing. 
FIX interrupt delivery - was zapping PSW before it had been saved.
FIX interrupt return, was one instruction out.
 1997-09-17 08:14:23 +00:00
Andrew Cagney
175c6fd375 * sim-events.c (ETRACE): Use trace_printf not sim_io_printf for 
trace output.
* sim-core.c (sim_core_signal): When bad access halt simulator
SIGSEGV / SIGBUS instead of aborting.
(signal.h): Include.
* sim-watch.c (sim_watchpoint_install): Handler for watchpoint
options was missing.
 1997-09-17 08:13:07 +00:00
Andrew Cagney
6aead89a5f Fix tracing for: "ctret", "bsw", "hsw" 
Fix bugs in: "bsh", "callt", "stsr".
 1997-09-17 05:31:00 +00:00
Andrew Cagney
dfa5c0ca02 Define MOVED macro, move sub-bitfield from XXX to YYY. 1997-09-17 05:28:32 +00:00
Andrew Cagney
fc07e279aa More v850 simulator tests. 1997-09-17 05:27:56 +00:00
Andrew Cagney
1a6eb36b62 More v850 simulator tests. 1997-09-17 03:31:09 +00:00
Andrew Cagney
b52e58c24f Add/test 8bit bit manipuation macros. 
Test LS and MS versions of SEXT macro.
Simplify/test macro returning a single bit.
 1997-09-17 03:25:54 +00:00
Andrew Cagney
8603b0f0ff Generic rules for building simple simulator test programs. 1997-09-16 23:57:57 +00:00
Gavin Romig-Koch
667065d0d4 * sim/mips/gencode.c (build_instruction): Don't need to subtract 4 for 
JALR, just 2.
 1997-09-16 20:01:00 +00:00
Gavin Romig-Koch
9cb8397f86 * sim/mips/interp.c: Correct some HASFPU problems. 1997-09-16 15:36:18 +00:00
Andrew Cagney
fb1fd47514 Smooth some of ALU tracing's rough edges. 
Fix switch insn.
 1997-09-16 14:00:15 +00:00
Andrew Cagney
6a0f95864a More sim-bits testing. 1997-09-16 13:58:44 +00:00
Andrew Cagney
aa5e6a5a78 Add {LS,MS}SEXT and {LS,MS}INSERTED macros. Eliminates bug in SEXT. 1997-09-16 07:04:46 +00:00
Andrew Cagney
3f33acd039 Use trace_one_insn in trace functions. Buffer up trace data so that 
it is displayed in a single block.
 1997-09-16 07:03:41 +00:00
Andrew Cagney
65a87fa9e1 v850eq simulator tests. 1997-09-16 07:01:57 +00:00
Andrew Cagney
c7db488f71 Restrict ldsr (load system register) to modifying just non-reserved PSW bits. 
For v850eq, include PSW[US] in bits that can be modified.
 1997-09-16 04:49:24 +00:00
Andrew Cagney
721478d51b Add v850e version of breakpoint instruction. 1997-09-16 02:15:55 +00:00
Andrew Cagney
3484de0091 Differentiate between a non-zero string and a constant zero field. 1997-09-16 02:14:18 +00:00
Jim Wilson
5262de2167 * simops.c (Multiply64): Don't store into register zero. 1997-09-16 01:45:23 +00:00
Andrew Cagney
4dda50b052 For instructions moved into v850.igen was computing (wrong) NIA when 
this wasn't needed.
 1997-09-15 23:09:26 +00:00
Andrew Cagney
0604253676 * igen.c (gen_run_c): Handle non-multi-sim case. 1997-09-15 22:40:14 +00:00
Andrew Cagney
bda6163995 Fix sanitization for v850 V v850e V v850eq 1997-09-15 14:42:51 +00:00
Andrew Cagney
a2ab5e65eb Update to reflect change to sim/common/aclocal.m4 (allow sim/common 
directory to specify its own unqiue config.h file).
 1997-09-15 08:25:04 +00:00
Andrew Cagney
658303f7d4 For v850eq start up with US bit set. 
Let sim_analyze_program determine the architecture.
Fix various sanitizations.
 1997-09-15 08:18:20 +00:00
Andrew Cagney
08547b1f1d Determine ARCHITECTURE from program if possible. 
Rename common's generated config.h to cconfig.h.
 1997-09-15 08:11:50 +00:00
Andrew Cagney
4bdab45adb * callback.c (os_write): divert stdout and stderr to their 
respective hooks.
 1997-09-15 08:02:23 +00:00
Andrew Cagney
410230cf6d Check reserved bits before executing instructions. 
Make v850[eq] the the default simulator.
Report illegal instructions.
Include v850e instructions in v850eq.
 1997-09-12 05:56:38 +00:00
Andrew Cagney
944deab68e v850eq wasn't building igen directory. 1997-09-12 03:13:27 +00:00
Andrew Cagney
93e7a1b5b7 Add profiling support to v850*. 1997-09-12 02:44:03 +00:00
Andrew Cagney
11ac69e013 Short form of sample-size option had wrong value. 1997-09-12 02:29:04 +00:00
Andrew Cagney
7a2f7ea758 v850* wants igen 1997-09-12 02:27:22 +00:00
Andrew Cagney
cf5c6e6e5d Generate instruction profile call with each instruction. 1997-09-12 02:26:31 +00:00
Martin Hunt
30d8198448 Wed Sep 10 22:30:24 1997 Martin M. Hunt <hunt@cygnus.com> 
* interp.c (sim_resume): Increment PC at end of rep
	loop.

	* simops.c (OP_4201): Fix rachi instruction.
 1997-09-11 05:32:23 +00:00
Andrew Cagney
972f3a34f5 mips/sim_info was just returning????? 1997-09-10 23:50:32 +00:00
Andrew Cagney
cad7297e80 o Wordwrap usage messages from sim-options 
o	Clarify how to use alias options
o	use in sim-watch (better usage message)
o	Don't pass something on the stack into the
	watch-point interrupt hander.
 1997-09-10 22:47:12 +00:00
Andrew Cagney
8f050205eb (gen_itable_h): Output an enum defining the max size of the itable 
string members.
 1997-09-10 22:07:06 +00:00
Andrew Cagney
02508bb179 Have trace_input, trace_output use sim-trace for IO. 1997-09-10 05:40:04 +00:00
Felix Lee
d6cef44df4 * inst.h (sim_state): rename to h8300_sim_state, to avoid conflict 
with sim/common.
	* configure.in: check for sys/param.h
	* compile.c: #ifdef HAVE_SYS_PARAM_H.
	#define SIGTRAP for wingdb.
	(sim_resume): poll keyboard at least once per call.
	(sim_resume): use host_callback instead of printf for syscall
 	output.
 1997-09-10 05:20:37 +00:00
Andrew Cagney
d0b59aa593 Add option architecture-info to list supported architectures. 1997-09-10 05:16:34 +00:00
Gavin Romig-Koch
318b499d8e Support tx19 sanitation. 1997-09-10 04:53:18 +00:00
Felix Lee
31dda65aff * sim-core.h (sim_cpu_core): [WITH_XOR_ENDIAN + 1], to avoid 
illegal zero-sized array.
	* sim-core.c (sim_core_xor_read_buffer): same.
 1997-09-10 04:46:37 +00:00
Felix Lee
a1efa0d880 * interp.c (sim_resume): poll_quit() at least once per call; 
otherwise gdb can loop sim_resume() uninterruptably.
 1997-09-10 03:52:48 +00:00
David Edelsohn
7b4aeebabe * nltvals.def: Regenerate. 1997-09-09 18:20:57 +00:00
Andrew Cagney
9eeaaefa0f Better word error messages. 1997-09-09 10:38:39 +00:00
Andrew Cagney
c31c13b481 Remove GCC specific `0x...LL', replace with SIGNED64 (0x...). 1997-09-09 07:02:02 +00:00
Andrew Cagney
db511584c9 Add basic tests for d10v-elf simulator. 1997-09-09 02:22:07 +00:00
Andrew Cagney
5d37a07bc5 Add multi-sim support to v850/v850e/v850eq simulators. 1997-09-08 17:42:48 +00:00
Andrew Cagney
687f3f1cef Add multi-sim support to simulator. 1997-09-08 17:40:24 +00:00
Andrew Cagney
70c8abdb4c Use updated MSMASK, MSMASKED macros. 
Fix sat problem in d30v.
 1997-09-08 17:23:16 +00:00