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Fix tracing for: "ctret", "bsw", "hsw"

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Fix bugs in: "bsh", "callt", "stsr".
This commit is contained in:
Andrew Cagney 1997-09-17 05:31:00 +00:00
parent dfa5c0ca02
commit 6aead89a5f
4 changed files with 139 additions and 143 deletions
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13
sim/v850/ChangeLog
View file

@ -1,3 +1,16 @@
start-sanitize-v850e
Wed Sep 17 14:02:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c: Move "ctret", "bsw", "hsw" to v850.igen, fix tracing.
(trace_module): Global, save component/module name across insn.
* simops.c: Move "bsh" to v850.igen, fix.
* v850.igen (callt): Load correct number of bytes. Fix tracing.
(stsr, ldsr): Correct src, dest fields. Fix tracing.
(ctret): Force alignment. Fix tracing.
end-sanitize-v850e
Tue Sep 16 22:14:01 1997 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c (trace_output): Add result argument.

57
sim/v850/sim-main.h
View file

@ -139,8 +139,8 @@ nia = PC
#define ECR (State.sregs[4])
#define PSW (State.sregs[5])
/* start-sanitize-v850e */
#define CTPC (State.sregs[16])
#define CTPSW (State.sregs[17])
#define CTPC (SR[16])
#define CTPSW (SR[17])
/* end-sanitize-v850e */
#define DBPC (State.sregs[18])
#define DBPSW (State.sregs[19])
@ -275,11 +275,13 @@ extern int trace_num_values;
extern unsigned32 trace_values[];
extern unsigned32 trace_pc;
extern const char *trace_name;
extern const char *trace_module;
#define TRACE_ALU_INPUT0() \
do { \
if (TRACE_ALU_P (CPU)) { \
trace_pc = CIA; \
trace_module = "alu"; \
trace_pc = cia; \
trace_name = itable[MY_INDEX].name; \
trace_num_values = 0; \
} \
@ -288,7 +290,8 @@ do { \
#define TRACE_ALU_INPUT1(IN1) \
do { \
if (TRACE_ALU_P (CPU)) { \
trace_pc = CIA; \
trace_module = "alu"; \
trace_pc = cia; \
trace_name = itable[MY_INDEX].name; \
trace_values[0] = (IN1); \
trace_num_values = 1; \
@ -298,7 +301,8 @@ do { \
#define TRACE_ALU_INPUT2(IN1, IN2) \
do { \
if (TRACE_ALU_P (CPU)) { \
trace_pc = CIA; \
trace_module = "alu"; \
trace_pc = cia; \
trace_name = itable[MY_INDEX].name; \
trace_values[0] = (IN1); \
trace_values[1] = (IN2); \
@ -313,6 +317,45 @@ do { \
} \
} while (0)
#define TRACE_BRANCH1(IN1) \
do { \
if (TRACE_BRANCH_P (CPU)) { \
trace_module = "branch"; \
trace_pc = cia; \
trace_name = itable[MY_INDEX].name; \
trace_values[0] = (IN1); \
trace_num_values = 1; \
trace_result (1, (nia)); \
} \
} while (0)
#define TRACE_BRANCH2(IN1, IN2) \
do { \
if (TRACE_BRANCH_P (CPU)) { \
trace_module = "branch"; \
trace_pc = cia; \
trace_name = itable[MY_INDEX].name; \
trace_values[0] = (IN1); \
trace_values[1] = (IN2); \
trace_num_values = 2; \
trace_result (1, (nia)); \
} \
} while (0)
#define TRACE_BRANCH3(IN1, IN2, IN3) \
do { \
if (TRACE_BRANCH_P (CPU)) { \
trace_module = "branch"; \
trace_pc = cia; \
trace_name = itable[MY_INDEX].name; \
trace_values[0] = (IN1); \
trace_values[1] = (IN2); \
trace_values[2] = (IN3); \
trace_num_values = 3; \
trace_result (1, (nia)); \
} \
} while (0)
#else
#define trace_input(NAME, IN1, IN2)
@ -323,6 +366,10 @@ do { \
#define TRACE_ALU_INPUT1(IN1)
#define TRACE_ALU_INPUT2(IN1, IN2)
#define TRACE_ALU_RESULT(RESULT)
#define TRACE_BRANCH1(IN1)
#define TRACE_BRANCH2(IN1, IN2)
#define TRACE_BRANCH2(IN1, IN2, IN3)
#endif

106
sim/v850/simops.c
View file

@ -68,6 +68,7 @@ unsigned32 trace_values[3];
int trace_num_values;
unsigned32 trace_pc;
const char *trace_name;
const char *trace_module;
void
@ -82,6 +83,7 @@ trace_input (name, type, size)
trace_pc = PC;
trace_name = name;
trace_module = "alu";
switch (type)
{
@ -238,7 +240,7 @@ trace_result (int has_result, unsigned32 result)
trace_one_insn (simulator, STATE_CPU (simulator, 0), trace_pc,
TRACE_LINENUM_P (STATE_CPU (simulator, 0)),
"simops", __LINE__, "alu",
"simops", __LINE__, trace_module,
"%-*s -%s", SIZE_INSTRUCTION, trace_name, buf);
}
@ -2758,108 +2760,6 @@ OP_30007E0 (void)
}
/* end-sanitize-v850e */
/* start-sanitize-v850e */
/* ctret */
int
OP_14407E0 (void)
{
trace_input ("ctret", OP_NONE, 0);
PC = CTPC;
PSW = CTPSW;
trace_output (OP_NONE);
return 0;
}
/* end-sanitize-v850e */
/* start-sanitize-v850e */
/* hsw */
int
OP_34407E0 (void)
{
unsigned long value;
trace_input ("hsw", OP_REG_REG3, 0);
value = State.regs[ OP[ 1 ] ];
value >>= 16;
value |= (State.regs[ OP[ 1 ] ] << 16);
State.regs[ OP[2] >> 11 ] = value;
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
if (value == 0) PSW |= PSW_Z;
if (value & 0x80000000) PSW |= PSW_S;
if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
trace_output (OP_REG_REG3);
return 4;
}
/* end-sanitize-v850e */
/* start-sanitize-v850e */
#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
/* bsw */
int
OP_34007E0 (void)
{
unsigned long value;
trace_input ("bsw", OP_REG_REG3, 0);
value = State.regs[ OP[ 1 ] ];
value >>= 24;
value |= (State.regs[ OP[ 1 ] ] << 24);
value |= ((State.regs[ OP[ 1 ] ] << 8) & 0x00ff0000);
value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x0000ff00);
State.regs[ OP[2] >> 11 ] = value;
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
if (value == 0) PSW |= PSW_Z;
if (value & 0x80000000) PSW |= PSW_S;
if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
trace_output (OP_REG_REG3);
return 4;
}
/* end-sanitize-v850e */
/* start-sanitize-v850e */
/* bsh */
int
OP_34207E0 (void)
{
unsigned long value;
trace_input ("bsh", OP_REG_REG3, 0);
value = State.regs[ OP[ 1 ] ];
value >>= 8;
value |= ((State.regs[ OP[ 1 ] ] << 8) & 0xff00ff00);
value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x000000ff);
State.regs[ OP[2] >> 11 ] = value;
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
if (value == 0) PSW |= PSW_Z;
if (value & 0x80000000) PSW |= PSW_S;
if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
trace_output (OP_REG_REG3);
return 4;
}
/* end-sanitize-v850e */
/* start-sanitize-v850e */
/* ld.hu */

106
sim/v850/v850.igen
View file

@ -31,7 +31,6 @@
:cache::unsigned:reg1:RRRRR:(RRRRR)
:cache::unsigned:reg2:rrrrr:(rrrrr)
:cache::unsigned:reg3:wwwww:(wwwww)
:cache::unsigned:regID:rrrrr:(rrrrr)
:cache::unsigned:disp4:dddd:(dddd)
# start-sanitize-v850e
@ -233,7 +232,21 @@ rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
// end-sanitize-v850eq
"bsh r<reg2>, r<reg3>"
{
COMPAT_2 (OP_34207E0 ());
unsigned32 value;
TRACE_ALU_INPUT1 (GR[reg2]);
value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
| MOVED32 (GR[reg2], 31, 24, 23, 16)
| MOVED32 (GR[reg2], 7, 0, 15, 8)
| MOVED32 (GR[reg2], 15, 8, 7, 0));
GR[reg3] = value;
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
if (value == 0) PSW |= PSW_Z;
if (value & 0x80000000) PSW |= PSW_S;
if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
TRACE_ALU_RESULT (GR[reg3]);
}
@ -246,9 +259,26 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
// start-sanitize-v850eq
*v850eq
// end-sanitize-v850eq
"bsw r<reg2>, reg3>"
"bsw r<reg2>, r<reg3>"
{
COMPAT_2 (OP_34007E0 ());
#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
unsigned32 value;
TRACE_ALU_INPUT1 (GR[reg2]);
value = GR[reg2];
value >>= 24;
value |= (GR[reg2] << 24);
value |= ((GR[reg2] << 8) & 0x00ff0000);
value |= ((GR[reg2] >> 8) & 0x0000ff00);
GR[reg3] = value;
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
if (value == 0) PSW |= PSW_Z;
if (value & 0x80000000) PSW |= PSW_S;
if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
TRACE_ALU_RESULT (GR[reg3]);
}
@ -263,14 +293,14 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
// end-sanitize-v850eq
"callt <imm6>"
{
unsigned long adr;
SAVE_1;
trace_input ("callt", OP_LOAD16, 1);
unsigned32 adr;
unsigned32 off;
CTPC = cia + 2;
CTPSW = PSW;
adr = CTBP + ((OP[3] & 0x3f) << 1);
nia = CTBP + load_mem (adr, 1);
trace_output (OP_LOAD16);
adr = (CTBP & ~1) + (imm6 << 1);
off = load_mem (adr, 2) & ~1; /* Force alignment */
nia = (CTBP & ~1) + off;
TRACE_BRANCH3 (adr, CTBP, off);
}
@ -306,7 +336,9 @@ rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
// end-sanitize-v850eq
"ctret"
{
COMPAT_2 (OP_14407E0 ());
nia = (CTPC & ~1);
PSW = (CTPSW & (CPU)->psw_mask);
TRACE_BRANCH1 (PSW);
}
@ -484,7 +516,22 @@ rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
// end-sanitize-v850eq
"hsw r<reg2>, r<reg3>"
{
COMPAT_2 (OP_34407E0 ());
unsigned32 value;
TRACE_ALU_INPUT1 (GR[reg2]);
value = GR[reg2];
value >>= 16;
value |= (GR[reg2] << 16);
GR[reg3] = value;
PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
if (value == 0) PSW |= PSW_Z;
if (value & 0x80000000) PSW |= PSW_S;
if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
TRACE_ALU_RESULT (GR[reg3]);
}
@ -565,23 +612,17 @@ rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
// end-sanitize-v850e
// LDSR
//rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
//"ldsr r<reg2>, r<regID>"
//{
// COMPAT_2 (OP_2007E0 ());
//}
rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
"ldsr r<reg1>, r<regID>"
regID,111111,RRRRR + 0000000000100000:IX:::ldsr
"ldsr r<reg1>, s<regID>"
{
SAVE_2;
trace_input ("ldsr", OP_LDSR, 0);
TRACE_ALU_INPUT1 (GR[reg1]);
if (&PSW == &State.sregs[ regID ])
PSW = (State.regs[ reg1 ] & (CPU)->psw_mask);
if (&PSW == &SR[regID])
PSW = (GR[reg1] & (CPU)->psw_mask);
else
State.sregs[ regID ] = State.regs[ reg1 ];
SR[regID] = GR[reg1];
trace_output (OP_LDSR);
TRACE_ALU_RESULT (SR[regID]);
}
@ -1080,17 +1121,12 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
// STSR
//rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
//"stsr r<regID>, r<reg2>"
//{
// COMPAT_2 (OP_4007E0 ());
//}
rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
"stsr r<regID>, r<reg1>"
rrrrr,111111,regID + 0000000001000000:IX:::stsr
"stsr s<regID>, r<reg2>"
{
TRACE_ALU_INPUT0();
GR[reg1] = SR[regID];
TRACE_ALU_RESULT (GR[reg1]);
TRACE_ALU_INPUT1 (SR[regID]);
GR[reg2] = SR[regID];
TRACE_ALU_RESULT (GR[reg2]);
}