Clean up tracing for Bcond & jmp insns.
Fix computation of disp16 and disp22. Clean up tracing of sld* insns.
This commit is contained in:
Andrew Cagney
parent
4410c4b925
commit
a276b6f057
4 changed files with 162 additions and 369 deletions
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@ -1,8 +1,28 @@
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Fri Sep 19 10:37:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* v850.igen (disp16): Use EXTEND16 to sign extend disp.
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(disp22): Only shift left by 1, not 2.
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("jmp"): Ensure PC is 2 byte aligned.
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* simops.c, v850.igen: Move "Bcond", "jr", "jarl" code to
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v850.igen. Fix tracing.
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* simops.c (OP_300, OP_400, OP_500): Move "sdl.b", "sld.h",
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"sld.w" insns to v850.igen. Fix tracing.
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start-sanitize-v850eq
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(OP_70): Ditto for "sld.hu".
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end-sanitize-v850eq
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* v850.igen: Clarify tracing of "sld.b", "sld.h" et.al.
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end-sanitize-v850eq
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* simops.c (condition_met): Make global.
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* sim-main.h (TRACE_ALU_INPUT3, TRACE_BRANCH0): Define.
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* sim-main.h (TRACE_ALU_INPUT3, TRACE_BRANCH0, TRACE_LD,
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TRACE_ST): Define.
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start-sanitize-v850eq
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(TRACE_LD_NAME): Define.
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end-sanitize-v850eq
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start-sanitize-v850e
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* simops.c: Move "cmov", "cmov imm" to v850.igen, fix.
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@ -384,6 +384,43 @@ do { \
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} \
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} while (0)
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#define TRACE_LD(ADDR,RESULT) \
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do { \
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if (TRACE_MEMORY_P (CPU)) { \
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trace_module = "memory"; \
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trace_pc = cia; \
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trace_name = itable[MY_INDEX].name; \
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trace_values[0] = (ADDR); \
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trace_num_values = 1; \
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trace_result (1, (RESULT)); \
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} \
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} while (0)
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/* start-sanitize-v850e */
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#define TRACE_LD_NAME(NAME, ADDR,RESULT) \
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do { \
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if (TRACE_MEMORY_P (CPU)) { \
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trace_module = "memory"; \
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trace_pc = cia; \
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trace_name = (NAME); \
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trace_values[0] = (ADDR); \
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trace_num_values = 1; \
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trace_result (1, (RESULT)); \
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} \
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} while (0)
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/* end-sanitize-v850e */
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#define TRACE_ST(ADDR,RESULT) \
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do { \
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if (TRACE_MEMORY_P (CPU)) { \
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trace_module = "memory"; \
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trace_pc = cia; \
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trace_name = itable[MY_INDEX].name; \
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trace_values[0] = (ADDR); \
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trace_num_values = 1; \
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trace_result (1, (RESULT)); \
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} \
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} while (0)
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#else
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#define trace_input(NAME, IN1, IN2)
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@ -401,6 +438,10 @@ do { \
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#define TRACE_BRANCH1(IN1)
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#define TRACE_BRANCH2(IN1, IN2)
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#define TRACE_BRANCH2(IN1, IN2, IN3)
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#define TRACE_LD(ADDR,RESULT)
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#define TRACE_ST(ADDR,RESULT)
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#endif
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@ -455,77 +455,6 @@ fetch_argv (sd, addr)
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}
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/* sld.b */
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int
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OP_300 ()
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{
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unsigned long result;
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result = load_mem (State.regs[30] + (OP[3] & 0x7f), 1);
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/* start-sanitize-v850eq */
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if (PSW & PSW_US)
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{
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trace_input ("sld.bu", OP_LOAD16, 1);
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State.regs[ OP[1] ] = result;
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}
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else
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{
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/* end-sanitize-v850eq */
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trace_input ("sld.b", OP_LOAD16, 1);
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State.regs[ OP[1] ] = EXTEND8 (result);
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/* start-sanitize-v850eq */
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}
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/* end-sanitize-v850eq */
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trace_output (OP_LOAD16);
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return 2;
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}
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/* sld.h */
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int
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OP_400 ()
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{
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unsigned long result;
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result = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2);
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/* start-sanitize-v850eq */
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if (PSW & PSW_US)
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{
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trace_input ("sld.hu", OP_LOAD16, 2);
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State.regs[ OP[1] ] = result;
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}
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else
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{
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/* end-sanitize-v850eq */
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trace_input ("sld.h", OP_LOAD16, 2);
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State.regs[ OP[1] ] = EXTEND16 (result);
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/* start-sanitize-v850eq */
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}
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/* end-sanitize-v850eq */
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trace_output (OP_LOAD16);
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return 2;
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}
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/* sld.w */
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int
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OP_500 ()
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{
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trace_input ("sld.w", OP_LOAD16, 4);
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State.regs[ OP[1] ] = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 4);
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trace_output (OP_LOAD16);
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return 2;
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}
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/* sst.b */
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int
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OP_380 ()
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@ -667,144 +596,6 @@ OP_10760 ()
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return 4;
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}
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static int
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branch (int code)
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{
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trace_input ("Bcond", OP_COND_BR, 0);
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trace_output (OP_COND_BR);
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if (condition_met (code))
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return SEXT9 (((OP[3] & 0x70) >> 3) | ((OP[3] & 0xf800) >> 7));
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else
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return 2;
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}
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/* bv disp9 */
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int
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OP_580 ()
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{
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return branch (0);
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}
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/* bl disp9 */
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int
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OP_581 ()
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{
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return branch (1);
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}
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/* be disp9 */
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int
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OP_582 ()
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{
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return branch (2);
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}
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/* bnh disp 9*/
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int
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OP_583 ()
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{
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return branch (3);
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}
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/* bn disp9 */
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int
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OP_584 ()
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{
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return branch (4);
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}
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/* br disp9 */
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int
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OP_585 ()
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{
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return branch (5);
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}
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/* blt disp9 */
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int
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OP_586 ()
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{
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return branch (6);
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}
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/* ble disp9 */
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int
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OP_587 ()
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{
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return branch (7);
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}
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/* bnv disp9 */
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int
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OP_588 ()
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{
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return branch (8);
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}
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/* bnl disp9 */
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int
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OP_589 ()
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{
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return branch (9);
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}
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/* bne disp9 */
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int
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OP_58A ()
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{
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return branch (10);
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}
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/* bh disp9 */
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int
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OP_58B ()
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{
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return branch (11);
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}
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/* bp disp9 */
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int
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OP_58C ()
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{
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return branch (12);
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}
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/* bsa disp9 */
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int
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OP_58D ()
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{
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return branch (13);
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}
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/* bge disp9 */
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int
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OP_58E ()
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{
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return branch (14);
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}
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/* bgt disp9 */
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int
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OP_58F ()
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{
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return branch (15);
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}
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/* jarl/jr disp22, reg */
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int
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OP_780 ()
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{
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trace_input ("jarl/jr", OP_JUMP, 0);
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if (OP[ 1 ] != 0)
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State.regs[ OP[1] ] = PC + 4;
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trace_output (OP_JUMP);
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return SEXT22 (((OP[3] & 0x3f) << 16) | OP[2]);
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}
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/* add reg, reg */
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int
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OP_1C0 ()
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@ -2849,37 +2640,6 @@ OP_30780 (void)
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return 4;
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}
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/* end-sanitize-v850e */
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/* start-sanitize-v850e */
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/* sld.hu */
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int
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OP_70 (void)
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{
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unsigned long result;
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result = load_mem (State.regs[30] + ((OP[3] & 0xf) << 1), 2);
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/* start-sanitize-v850eq */
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if (PSW & PSW_US)
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{
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trace_input ("sld.h", OP_LOAD16, 2);
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State.regs[ OP[1] ] = EXTEND16 (result);
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}
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else
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{
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/* end-sanitize-v850eq */
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trace_input ("sld.hu", OP_LOAD16, 2);
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State.regs[ OP[1] ] = result;
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/* start-sanitize-v850eq */
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}
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/* end-sanitize-v850eq */
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trace_output (OP_LOAD16);
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return 2;
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}
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/* end-sanitize-v850e */
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/* start-sanitize-v850e */
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/* mul reg1, reg2, reg3 */
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@ -40,10 +40,9 @@
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:cache::unsigned:disp8:ddddddd:(ddddddd << 1)
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:cache::unsigned:disp8:dddddd:(dddddd << 2)
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:cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
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:cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
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:cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
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:cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
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:cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
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:cache::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
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:cache::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
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:cache::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
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:cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
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:cache::unsigned:imm6:iiiiii:iiiiii
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@ -158,109 +157,13 @@ rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
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// Bcond
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// ddddd,1011,ddd,cccc:III:::Bcond
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// "b%s<cccc> <disp9>"
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// {
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// int cond = condition_met (cccc);
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// if (cond)
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// nia = cia + disp9;
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// TRACE_BRANCH1 (cond);
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// }
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ddddd,1011,ddd,0000:III:::bv
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"bv <disp9>"
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ddddd,1011,ddd,cccc:III:::Bcond
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"b%s<cccc> <disp9>"
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{
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COMPAT_1 (OP_580 ());
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}
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ddddd,1011,ddd,0001:III:::bl
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"bl <disp9>"
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{
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COMPAT_1 (OP_581 ());
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}
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ddddd,1011,ddd,0010:III:::be
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"be <disp9>"
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{
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COMPAT_1 (OP_582 ());
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}
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ddddd,1011,ddd,0011:III:::bnh
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"bnh <disp9>"
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{
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COMPAT_1 (OP_583 ());
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}
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ddddd,1011,ddd,0100:III:::bn
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"bn <disp9>"
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{
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COMPAT_1 (OP_584 ());
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}
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ddddd,1011,ddd,0101:III:::br
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"br <disp9>"
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{
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COMPAT_1 (OP_585 ());
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}
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ddddd,1011,ddd,0110:III:::blt
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"blt <disp9>"
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{
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COMPAT_1 (OP_586 ());
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}
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ddddd,1011,ddd,0111:III:::ble
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"ble <disp9>"
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{
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COMPAT_1 (OP_587 ());
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}
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ddddd,1011,ddd,1000:III:::bnv
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"bnv <disp9>"
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{
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COMPAT_1 (OP_588 ());
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}
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ddddd,1011,ddd,1001:III:::bnl
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"bnl <disp9>"
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{
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COMPAT_1 (OP_589 ());
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}
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ddddd,1011,ddd,1010:III:::bne
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"bne <disp9>"
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{
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COMPAT_1 (OP_58A ());
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}
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ddddd,1011,ddd,1011:III:::bh
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"bh <disp9>"
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{
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COMPAT_1 (OP_58B ());
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}
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ddddd,1011,ddd,1100:III:::bp
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"bp <disp9>"
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{
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COMPAT_1 (OP_58C ());
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}
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ddddd,1011,ddd,1101:III:::bsa
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"bsa <disp9>"
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{
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COMPAT_1 (OP_58D ());
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}
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ddddd,1011,ddd,1110:III:::bge
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"bge <disp9>"
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{
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COMPAT_1 (OP_58E ());
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}
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ddddd,1011,ddd,1111:III:::bgt
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"bgt <disp9>"
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{
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COMPAT_1 (OP_58F ());
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int cond = condition_met (cccc);
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if (cond)
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nia = cia + disp9;
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TRACE_BRANCH1 (cond);
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}
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@ -589,7 +492,9 @@ rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
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rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
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"jarl <disp22>, r<reg2>"
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{
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COMPAT_2 (OP_780 ());
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GR[reg2] = nia;
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nia = cia + disp22;
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TRACE_BRANCH1 (GR[reg2]);
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}
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@ -598,7 +503,7 @@ rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
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00000000011,RRRRR:I:::jmp
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"jmp [r<reg1>]"
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{
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nia = GR[reg1];
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nia = GR[reg1] & ~1;
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TRACE_BRANCH0 ();
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}
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@ -608,14 +513,15 @@ rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
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0000011110,dddddd + ddddddddddddddd,0:V:::jr
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"jr <disp22>"
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{
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COMPAT_2 (OP_780 ());
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nia = cia + disp22;
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TRACE_BRANCH0 ();
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}
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// LD
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rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
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"ld.b <disp16>[r<reg1>, r<reg2>"
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"ld.b <disp16>[r<reg1>], r<reg2>"
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{
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COMPAT_2 (OP_700 ());
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}
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@ -1090,53 +996,119 @@ rrrrr,010100,iiiii:II:::shr
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|||
|
||||
// SLD
|
||||
rrrrr,0110,ddddddd:IV:::sld.b
|
||||
// start-sanitize-v850eq
|
||||
"sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
|
||||
// end-sanitize-v850eq
|
||||
"sld.b <disp7>[ep], r<reg2>"
|
||||
{
|
||||
COMPAT_1 (OP_300 ());
|
||||
unsigned32 addr = EP + disp7;
|
||||
unsigned32 result = load_mem (addr, 1);
|
||||
/* start-sanitize-v850eq */
|
||||
if (PSW & PSW_US)
|
||||
{
|
||||
GR[reg2] = result;
|
||||
TRACE_LD_NAME ("sld.bu", addr, result);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* end-sanitize-v850eq */
|
||||
result = EXTEND8 (result);
|
||||
GR[reg2] = result;
|
||||
TRACE_LD (addr, result);
|
||||
/* start-sanitize-v850eq */
|
||||
}
|
||||
/* end-sanitize-v850eq */
|
||||
}
|
||||
|
||||
rrrrr,1000,ddddddd:IV:::sld.h
|
||||
// start-sanitize-v850eq
|
||||
"sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
|
||||
// end-sanitize-v850eq
|
||||
"sld.h <disp8>[ep], r<reg2>"
|
||||
{
|
||||
COMPAT_1 (OP_400 ());
|
||||
unsigned32 addr = EP + disp8;
|
||||
unsigned32 result = load_mem (addr, 2);
|
||||
/* start-sanitize-v850eq */
|
||||
if (PSW & PSW_US)
|
||||
{
|
||||
GR[reg2] = result;
|
||||
TRACE_LD_NAME ("sld.hu", addr, result);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* end-sanitize-v850eq */
|
||||
result = EXTEND16 (result);
|
||||
GR[reg2] = result;
|
||||
TRACE_LD (addr, result);
|
||||
/* start-sanitize-v850eq */
|
||||
}
|
||||
/* end-sanitize-v850eq */
|
||||
}
|
||||
|
||||
rrrrr,1010,dddddd,0:IV:::sld.w
|
||||
"sld.w <disp8>[ep], r<reg2>"
|
||||
{
|
||||
COMPAT_1 (OP_500 ());
|
||||
unsigned32 addr = EP + disp8;
|
||||
unsigned32 result = load_mem (addr, 4);
|
||||
GR[reg2] = result;
|
||||
TRACE_LD (addr, result);
|
||||
}
|
||||
|
||||
// start-sanitize-v850e
|
||||
rrrrr!0,0000110,dddd:IV:::sld.bu
|
||||
*v850e
|
||||
// start-sanitize-v850eq
|
||||
*v850eq
|
||||
"sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
|
||||
// end-sanitize-v850eq
|
||||
"sld.bu <disp4>[ep], r<reg2>"
|
||||
{
|
||||
unsigned long result;
|
||||
|
||||
SAVE_1;
|
||||
result = load_mem (State.regs[30] + disp4, 1);
|
||||
|
||||
unsigned32 addr = EP + disp4;
|
||||
unsigned32 result = load_mem (addr, 1);
|
||||
/* start-sanitize-v850eq */
|
||||
if (PSW & PSW_US) {
|
||||
trace_input ("sld.b", OP_LOAD16, 1);
|
||||
|
||||
State.regs[ reg2 ] = EXTEND8 (result);
|
||||
} else {
|
||||
if (PSW & PSW_US)
|
||||
{
|
||||
result = EXTEND8 (result);
|
||||
GR[reg2] = result;
|
||||
TRACE_LD_NAME ("sld.b", addr, result);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* end-sanitize-v850eq */
|
||||
trace_input ("sld.bu", OP_LOAD16, 1);
|
||||
State.regs[ reg2 ] = result;
|
||||
GR[reg2] = result;
|
||||
TRACE_LD (addr, result);
|
||||
/* start-sanitize-v850eq */
|
||||
}
|
||||
}
|
||||
/* end-sanitize-v850eq */
|
||||
trace_output (OP_LOAD16);
|
||||
}
|
||||
|
||||
// end-sanitize-v850e
|
||||
// start-sanitize-v850e
|
||||
rrrrr!0,0000111,dddd:IV:::sld.hu
|
||||
*v850e
|
||||
// start-sanitize-v850eq
|
||||
*v850eq
|
||||
"sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
|
||||
// end-sanitize-v850eq
|
||||
"sld.hu <disp5>[ep], r<reg2>"
|
||||
{
|
||||
COMPAT_1 (OP_70 ());
|
||||
unsigned32 addr = EP + disp5;
|
||||
unsigned32 result = load_mem (addr, 2);
|
||||
/* start-sanitize-v850eq */
|
||||
if (PSW & PSW_US)
|
||||
{
|
||||
result = EXTEND16 (result);
|
||||
GR[reg2] = result;
|
||||
TRACE_LD_NAME ("sld.h", addr, result);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* end-sanitize-v850eq */
|
||||
GR[reg2] = result;
|
||||
TRACE_LD (addr, result);
|
||||
/* start-sanitize-v850eq */
|
||||
}
|
||||
/* end-sanitize-v850eq */
|
||||
}
|
||||
|
||||
// end-sanitize-v850e
|
||||
|
|
|
|||
Loading…
Reference in a new issue