When generating relocation (tc_gen_reloc) 32 bit relocation fixup
is changed to new 32 bit PC relative relocation if the fixup has pc-relative
flag set.
bfd/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* elf32-avr.c: Add 32 bit PC relative relocation for AVR target.
gas/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* config/tc-avr.c (tc_gen_reloc): Change 32 bit relocation to
32 bit PC relative and update offset if the fixup is pc-relative.
* config/tc-avr.h (DIFF_EXPR_OK): Define to enable PC relative diff
relocs.
gas/testsuite/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* gas/avr/pc-relative-reloc.d: New test for 32 bit pc relative reloc.
* gas/avr/per-function-debugline.s: New test source.
include/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* elf/avr.h: Add new 32 bit PC relative relocation.
ld/testsuite/ChangeLog
2015-07-06 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
* ld-avr/gc-section-debugline.d: New test.
* ld-avr/per-function-debugline.s: Source for new test.
Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations. I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8. This
patch fixes that problem.
Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code. ie. you might need to modify
makefiles to pass -m860 to gas.
include/opcode/
* ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
opcodes/
* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
gas/
* config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
gas/testsuite/
* gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
This patch uses ELF strtab with GC and suffix merging support to create
ELF .strtab section. There is some small memory overhead to use ELF
strtab:
==14928== HEAP SUMMARY:
==14928== in use at exit: 3,276,318 bytes in 679 blocks
==14928== total heap usage: 1,544 allocs, 865 frees, 15,259,146 bytes allocated
vs.
==14936== HEAP SUMMARY:
==14936== in use at exit: 3,276,318 bytes in 679 blocks
==14936== total heap usage: 1,532 allocs, 853 frees, 15,026,402 bytes allocated
when running:
./ld-new -m elf_x86_64 -o tmpdir/ld-partial.o -r ldgram.o ldlex-wrapper.o lexsup.o ldlang.o mri.o ldctor.o ldmain.o plugin.o ldwrite.o ldexp.o ldemul.o ldver.o ldmisc.o ldfile.o ldcref.o eelf_x86_64.o eelf32_x86_64.o eelf_i386.o eelf_iamcu.o ei386linux.o eelf_l1om.o eelf_k1om.o ldbuildid.o
The results are
[32] .strtab STRTAB 0+ 3beff8 00407a 00 0 0 1
vs
[32] .strtab STRTAB 0+ 3beff8 0041d8 00 0 0 1
It reduces the .strtab size by 350 bytes, about 2%
Saving on libc.so from glibc is much more since libc.so has many alias
symbols with the same suffix. For x32 glibc,
[82] .strtab STRTAB 0+ 81b348 0159e7 00 0 0 1
vs
[82] .strtab STRTAB 0+ 81b8bc 019e72 00 0 0 1
It reduces the .strtab size by 17547 bytes, about 16%.
bfd/
PR gas/18451
* elf-bfd.h (elf_sym_strtab): New.
(elf_link_hash_table): Add strtabcount, strtabsize and
strtab.
(_bfd_elf_stringtab_init): Removed.
* elf.c (_bfd_elf_stringtab_init): Removed.
(_bfd_elf_compute_section_file_positions): Replace
bfd_strtab_hash/_bfd_elf_stringtab_init/_bfd_stringtab_free/
_bfd_stringtab_size with
elf_strtab_hash/_bfd_elf_strtab_init/_bfd_elf_strtab_free/
_bfd_elf_strtab_size. Use _bfd_elf_strtab_add,
_bfd_elf_strtab_finalize and _bfd_elf_strtab_offset to get
st_name.
(swap_out_syms): Likewise.
* elflink.c (elf_final_link_info): Replace bfd_strtab_hash
with elf_strtab_hash. Remove symbuf, symbuf_count,
symbuf_size and shndxbuf_size.
(elf_link_flush_output_syms): Removed.
(elf_link_output_sym): Renamed to ...
(elf_link_output_symstrtab): This. Replace _bfd_stringtab_add
with _bfd_elf_strtab_add. Don't flush symbols to the file nor
swap out symbols.
(elf_link_swap_symbols_out): New.
(elf_link_output_extsym): Replace elf_link_output_sym with
elf_link_output_symstrtab.
(elf_link_input_bfd): Likewise.
(elf_final_link_free): Replace _bfd_stringtab_free with
_bfd_elf_strtab_free. Remove symbuf.
(bfd_elf_final_link): Replace _bfd_elf_stringtab_init with
_bfd_elf_strtab_init. Don't set symbuf, symbuf_count,
symbuf_size nor shndxbuf_size. Initialize strtabsize and
strtab. Initialize symshndxbuf to -1 when number of sections
>= 64K. Replace elf_link_output_sym/elf_link_output_sym with
elf_link_output_symstrtab/elf_link_output_symstrtab. Don't
call elf_link_flush_output_syms. Call _bfd_elf_strtab_finalize
and elf_link_swap_symbols_out. Replace _bfd_stringtab_size
and _bfd_stringtab_emit with _bfd_elf_strtab_size and
_bfd_elf_strtab_emit.
gas/testsuite/
PR gas/18451
* gas/elf/elf.exp: Run strtab.
* gas/elf/strtab.d: New file.
* gas/elf/strtab.s: Likewise.
ld/testsuite/
PR gas/18451
* ld-elf/strtab.d: New file.
* ld-elf/strtab.s: Likewise.
ISA 2.07 added a new category called Elemental Memory Barriers that modifies
the sync instruction to accept an additional operand ESYNC. Edmar added
support for this insruction varient here:
https://sourceware.org/ml/binutils/2012-02/msg00221.html
Looking at this closer, I see that the insert_ls() function is misnamed
(since it's attached to the ESYNC operand, not the LS operand) but more
importantly, it is silently modifying the LS operand value behind the
users back when the LS operand is either invalid or is incompatible with
the new ESYNC operand. The ISA 2.07 doc has an Assembler Note that clearly
states that assemblers that support the ESYNC operand should report all
invalid uses of LS and ESYNC. This patch changes the assembler to
error out on invalid and incompatible operand usage.
opcodes/
* ppc-opc.c (insert_ls): Test for invalid LS operands.
(insert_esync): New function.
(LS, WC): Use insert_ls.
(ESYNC): Use insert_esync.
gas/testsuite/
* gas/ppc/e6500.s <sync>: Fix invalid test.
* gas/ppc/e6500.d: Likewise.
include * dis-asm.h (struct disassemble_info): Add stop_vma field.
binuti * objdump.c (disassemble_bytes): Set the stop_vma field in the
disassemble_info structure when disassembling code sections with
-d.
* doc/binutils.texi (objdump): Document the discrepancy between -d
and -D.
opcodes * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
requested region lies beyond it.
* bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
looking for 32-bit insns.
* mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
data.
* sh-dis.c (print_insn_sh): Likewise.
* tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
blocks of instructions.
* vax-dis.c (print_insn_vax): Check that the requested address
does not clash with the stop_vma.
tests * gas/arm/backslash-at.s: Add extra .byte directives so that the
foo symbol does not appear to point half way through an
instruction.
* gas/arm/backslash-at.d: Update expected disassembly.
* gas/i386/ilp32/x86-64-opcode-inval-intel.d: Likewise.
* gas/i386/ilp32/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1. It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case. I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.
This fixes the rfebb issue. I also fixed the mftb and mfcr instructions
so they use the same mechanism. This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].
include/opcode/
* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
(ppc_optional_operand_value): New inline function.
opcodes/
* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
* ppc-opc.c (FXM4): Add non-zero optional value.
(TBR): Likewise.
(SXL): Likewise.
(insert_fxm): Handle new default operand value.
(extract_fxm): Likewise.
(insert_tbr): Likewise.
(extract_tbr): Likewise.
gas/
* config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
Allow for optional operands without insert functions.
gas/testsuite/
* gas/ppc/power8.d: Fixup rfebb test results.
* gas/ppc/a2.s: Fix invalid mfcr test.
* gas/ppc/a2.d: Likewise.
PR gas/18541
gas * config/tc-arm.c (md_apply_fix): Add support for ADR in thumb
mode against a nearby symbol.
tests * gas/arm/thumb.s: Add test of ADR against a nearby symbol.
* gas/arm/thumb.d: Update expected output.
* gas/arm/thumb-eabi.d: Likewise.
PR gas/18481
bfd * elf32-arm.c (R_ARM_TLS_LE32): Set the special function to NULL.
gas * config/tc-arm.c (tc_gen_reloc): Include BFD_RELOC_ARM_TLS_LE32
in the same case as BFD_RELOC_ARM_TLS_IS32.
tests * gas/arm/tls.s: Add tests of the tpoff pseudo with a local
symbol.
* gas/arm/tls.d: Update expected output.
PR gas/18499
gas * config/tc-arm.c (move_or_literal_pool): Add support for LDR Rx,=
to MOV.w or MVN.w for Thumb2.
tests * gas/arm/thumb2_ldr_immediate_armv6.s: New test case.
* gas/arm/thumb2_ldr_immediate_armv6.d: Expected disassembly.
* gas/arm/thumb2_ldr_immediate_armv6t2.s: New test case.
* gas/arm/thumb2_ldr_immediate_armv6t2.d: Expected disassembly.
PR gas/18500
gas * config/tc-arm.c (is_double_a_single): New function.
(double_to_single): New function.
(move_or_literal_pool): Add support for converting VLDR to VMOV.
tests * gas/arm/vfpv2-ldr_immediate.s: New test case.
* gas/arm/vfpv2-ldr_immediate.d: Expected disassembly.
* gas/arm/vfpv3-ldr_immediate.s: New test case.
* gas/arm/vfpv3-ldr_immediate.d: Expected disassembly.
* gas/arm/vfpv3xd-ldr_immediate.s: New test case.
* gas/arm/vfpv3xd-ldr_immediate.d: Expected disassembly.
out_debug_aranges uses frag_align to make sure the addresses start
out aligned. Using frag_align will call frag_var[_init], which will
end up calling TC_FRAG_INIT. On arm and aarch64 TC_FRAG_INIT will
generate a $d mapping symbol for the .debug_aranges to show that at
that point a sequence of data items starts.
Such a symbol pointing into a non-allocated debug section will confuse
eu-strip -g. And it seems inefficient and wrong in general to have
additional mapping symbols for debug sections, which won't contain
actual code in the first place.
Just keep track of the aranges header size and use plain padding to
align the addresses which avoids generating any mapping symbols on
aarch64 and arm.
Includes a testcase for aarch64 that PASS with this patch and shows
the extra $d mapping symbol in .debug_aranges before.
gas/ChangeLog
* dwarf2dbg.c (out_header): Document EXPR->X_add_number value,
out_debug_aranges depends on it.
(out_debug_aranges): Track size of header to properly pad header
for address alignment.
gas/testsuite/ChangeLog
* gas/aarch64/dwarf.d: New.
* gas/aarch64/dwarf.s: New.
As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so disassembler should produce output accordingly.
gas/testsuite/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512f.s: Adjust operand order for Intel syntax
vcvt{,u}si2ss.
* gas/i386/x86-64-avx512f.s: Adjust operand order for Intel
syntax vcvt{,u}si2s{d,s}.
opcodes/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (print_insn): Swap rounding mode specifier and
general purpose register in Intel mode.
As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so gas should accept such input. As the brojen code got
released already we sadly will need to continue to also accept the
badly ordered operands.
gas/testsuite/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512f-intel.d: Adjust expectations on operand order.
* gas/i386/evex-lig256-intel.d: Likewise.
* gas/i386/evex-lig512-intel.d: Likewise.
* gas/i386/x86-64-avx512f-intel.d: Likewise.
* gas/i386/x86-64-evex-lig256-intel.d: Likewise.
* gas/i386/x86-64-evex-lig512-intel.d: Likewise.
opcodes/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
* i386-tbl.h: Regenerate.
AMD64 spec and Intel64 spec differ in direct unconditional branches in
64-bit mode. AMD64 supports direct unconditional branches with 16-bit
offset via the data size prefix, which truncates RIP to 16 bits, while
the data size prefix is ignored by Intel64.
This patch adds -mamd64/-mintel64 option to x86-64 assembler and
-Mamd64/-Mintel64 option to x86-64 disassembler. The most permissive
ISA, which is AMD64, is the default.
GDB can add an option, similar to
(gdb) help set disassembly-flavor
Set the disassembly flavor.
The valid values are "att" and "intel", and the default value is "att".
to select which ISA to disassemble.
binutils/
PR binutis/18386
* doc/binutils.texi: Document -Mamd64 and -Mintel64.
gas/
PR binutis/18386
* config/tc-i386.c (OPTION_MAMD64): New.
(OPTION_MINTEL64): Likewise.
(md_longopts): Add -mamd64 and -mintel64.
(md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
(md_show_usage): Add -mamd64 and -mintel64.
* doc/c-i386.texi: Document -mamd64 and -mintel64.
gas/testsuite/
PR binutis/18386
* gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3.
* gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump.
* gas/i386/ilp32/x86-64-branch.d: Likewise.
* gas/i386/x86-64-branch-2.d: New file.
* gas/i386/x86-64-branch-2.s: Likewise.
* gas/i386/x86-64-branch-3.l: Likewise.
* gas/i386/x86-64-branch-3.s: Likewise.
ld/testsuite/
PR binutis/18386
* ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump.
* ld-x86-64/tlspic.dd: Likewise.
* ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to
objdump for tlspic.dd and tlsgdesc.dd.
opcodes/
PR binutis/18386
* i386-dis.c: Add comments for '@'.
(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
(enum x86_64_isa): New.
(isa64): Likewise.
(print_i386_disassembler_options): Add amd64 and intel64.
(print_insn): Handle amd64 and intel64.
(putop): Handle '@'.
(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
* i386-opc.h (AMD64): New.
(CpuIntel64): Likewise.
(i386_cpu_flags): Add cpuamd64 and cpuintel64.
* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
Mark direct call/jmp without Disp16|Disp32 as Intel64.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
This patch adds -mshared option to x86 ELF assembler. By default,
assembler will optimize out non-PLT relocations against defined non-weak
global branch targets with default visibility. The -mshared option tells
the assembler to generate code which may go into a shared library
where all non-weak global branch targets with default visibility can
be preempted. The resulting code is slightly bigger. This option
only affects the handling of branch instructions.
This Linux kernel patch is needed to create a working x86 Linux kernel if
it hasn't been applied:
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index ae6588b..b91a00c 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -339,8 +339,8 @@ early_idt_handlers:
i = i + 1
.endr
-/* This is global to keep gas from relaxing the jumps */
-ENTRY(early_idt_handler)
+/* This is weak to keep gas from relaxing the jumps */
+WEAK(early_idt_handler)
cld
cmpl $2,(%rsp) # X86_TRAP_NMI
--
gas/
* config/tc-i386.c (shared): New.
(OPTION_MSHARED): Likewise.
(elf_symbol_resolved_in_segment_p): Add relocation argument.
Check PLT relocations and shared.
(md_estimate_size_before_relax): Pass fragP->fr_var to
elf_symbol_resolved_in_segment_p.
(md_longopts): Add -mshared.
(md_show_usage): Likewise.
(md_parse_option): Handle OPTION_MSHARED.
* doc/c-i386.texi: Document -mshared.
gas/testsuite/
* gas/i386/i386.exp: Don't run pcrel for ELF targets. Run
pcrel-elf, relax-4 and x86-64-relax-3 for ELF targets.
* gas/i386/pcrel-elf.d: New file.
* gas/i386/relax-4.d: Likewise.
* gas/i386/x86-64-relax-3.d: Likewise.
* gas/i386/relax-3.d: Pass -mshared to assembler. Updated.
* gas/i386/x86-64-relax-2.d: Likewise.
* gas/i386/relax-3.s: Add test for PLT relocation.
Remove the wait instructions for server processors, since they were never
implemented. Also add the extra operands added to the tlbie and slbia
instructions with ISA 2.06 and ISA 2.05 respectively.
binutils/
* MAINTAINERS: Add myself as PPC maintainer.
opcodes/
* ppc-opc.c (IH) New define.
(powerpc_opcodes) <wait>: Do not enable for POWER7.
<tlbie>: Add RS operand for POWER7.
<slbia>: Add IH operand for POWER6.
gas/testsuite/
* gas/ppc/power4.d: Add a slbia test.
* gas/ppc/power4.s: Likewise.
* gas/ppc/power6.d: Add slbia and tlbie tests.
* gas/ppc/power6.s: Likewise.
* gas/ppc/power7.d: Remove wait tests. Add a tlbie test.
* gas/ppc/power7.s: Likewise.
Extra condition 'abs (addr - trampaddr) < J_RANGE / 2' for trampoline
selection results in regressions: when relaxable jump is little longer
than J_RANGE so that single trampoline makes two new jumps, one longer
than J_RANGE / 2 and one shorter, correct trampoline cannot be found.
Drop that condition.
2015-05-13 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (xtensa_relax_frag): Allow trampoline to be
closer than J_RANGE / 2 to jump frag.
gas/testsuite/
* gas/xtensa/trampoline.s: Add regression testcase.
PR gas/18347
* config/tc-arm.h (TC_EQUAL_IN_INSN): Define.
* config/tc-arm.c (arm_tc_equal_in_insn): New function. Move
the symbol name checking code to here from...
(md_undefined_symbo): ... here.
On ELF target, the assembler normally generates code which can go into a
shared library where non-weak symbols can be preempted. The -mno-shared
option tells the assembler to generate code not for a shared library,
where non-weak symbols won't be preempted. The resulting code is slightly
smaller. This option mainly affects the handling of branch instructions.
gas/
* config/tc-i386.c (no_shared): New.
(OPTION_MNO_SHARED): Likewise.
(elf_symbol_resolved_in_segment_p): Check no_shared.
(md_longopts): Add mno-shared.
(md_parse_option): Handle OPTION_MNO_SHARED.
(md_show_usage): Add -mno-shared.
* doc/c-i386.texi: Document -mno-shared.
gas/testsuite/
* gas/i386/i386.exp: Run relax-4 and x86-64-relax-3.
* gas/i386/relax-4.d: New file.
* gas/i386/x86-64-relax-3.d: Likewise.
Branches to global non-weak symbols defined in the same segment with
non-default visibility can be optimized the same way as branches to
local symbols.
gas/
* config/tc-i386.c (elf_symbol_resolved_in_segment_p): New.
(md_estimate_size_before_relax): Use it.
gas/testsuite/
* gas/i386/i386.exp: Run relax-3 and x86-64-relax-2.
* gas/i386/relax-3.d: New file.
* gas/i386/relax-3.s: Likewise.
* gas/i386/x86-64-relax-2.d: Likewise.
gas/ChangeLog:
2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Support the %ncc "natural"
condition codes
* doc/c-sparc.texi (Sparc-Regs): Document %ncc.
gas/testsuite/ChangeLog:
2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
* gas/sparc/natural.s: New file.
* gas/sparc/natural-32.s: Likewise.
* gas/sparc/natural.d: Likewise.
* gas/sparc/natural-32.d: Likewise.
* gas/sparc/sparc.exp (sparc_elf_setup): Run the tests natural and
natural-32.
This x86 assembler patch:
https://sourceware.org/ml/binutils/2001-11/msg00344.html
generates a .note section for .arch directive so that GDB can tell which
architecture an i386 binary belongs:
https://sourceware.org/ml/binutils/2001-11/msg00271.html
However, x86 assembly code can have any instructions. A .note section
doesn't help. This patch removes it.
gas/
* config/tc-i386.c (i386_elf_emit_arch_note): Removed.
* config/tc-i386.h (md_end): Likewise.
(i386_elf_emit_arch_note): Likewise.
gas/testsuite/
* gas/i386/i386.exp: Run note.
* gas/i386/note.d: New file.
* gas/i386/note.s: Likewise.
PR gas/18347
gas * config/tc-arm.c (md_undefined_symbol): Issue a warning message
(if enabled) when the user creates a symbol with the same name as
an ARM instruction.
(flag_warn_syms): New static variable.
(arm_opts): Add mwarn-syms and mno-warn-syms.
* doc/c-arm.texi (ARM Options): Document the -m[no-]warn-syms
options.
tests * gas/arm/pr18347.s: New file: Test case.
* gas/arm/pr18347.l: New file: Expected assembler output.
* gas/arm/pr18347.d: New file: Test driver.
gas PR 18256
* config/tc-arm.c (encode_arm_cp_address): Issue an error message
if the operand is neither a register nor a vector.
tests * gas/arm/pr18256.s: New file: Test case.
* gas/arm/pr18256.l: New file: Expected assembler output.
* gas/arm/pr18256.d: New file: Test driver.
* ppc-opc.c (DCBT_EO): New define.
(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
<lharx>: Likewise.
<stbcx.>: Likewise.
<sthcx.>: Likewise.
<waitrsv>: Do not enable for POWER7 and later.
<waitimpl>: Likewise.
<dcbt>: Default to the two operand form of the instruction for all
"old" cpus. For "new" cpus, use the operand ordering that matches
whether the cpu is server or embedded.
<dcbtst>: Likewise.
gas/testsuite/
* gas/ppc/a2.s: Fixup test case due to dcbt/dcbtst embedded operand
ordering change.
* gas/ppc/a2.d: Likewise.
* gas/ppc/476.d: Likewise.
* gas/ppc/booke.s: Remove invalid 3 operand dcbt tests.
* gas/ppc/booke.d: Likewise.
* gas/ppc/power7.s: Remove lbarx, lharx, stbcx., sthcx., waitrsv
and waitimpl tests.
* gas/ppc/power7.d: Likewise.
