[AArch64] Support for ARMv8.1a Limited Ordering Regions extension
2015-06-02 Matthew Wahab <matthew.wahab@arm.com> include/ * aarch64.h (AARCH64_FEATURE_LOR): New. opcodes/ * aarch64-tbl.h (aarch64_feature_lor): New. (LOR): New. (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr", "stllrb", "stllrh". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ * config/tc-aarch64.c (aarch64_features): Add "lor". * doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of architecture extensions. gas/testsuite/ * lor-directive.d: New. * lor.d: New. * lor.s: New.
This commit is contained in:
Matthew Wahab
Jiong Wang
parent
8d683210f1
commit
290806fd94
14 changed files with 589 additions and 401 deletions
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@ -1,3 +1,9 @@
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2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
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* config/tc-aarch64.c (aarch64_features): Add "lor".
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* doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of
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architecture extensions.
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2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
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* config/tc-aarch64.c (parse_sys_reg): New parameter. Check target
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@ -7400,6 +7400,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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{"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0)},
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{"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
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{"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0)},
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{"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0)},
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{NULL, AARCH64_ARCH_NONE}
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};
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@ -135,6 +135,8 @@ automatically cause those extensions to be disabled.
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@tab Enable Advanced SIMD extensions. This implies @code{fp}.
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@item @code{pan} @tab ARMv8-A @tab ARMv8-A or later
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@tab Enable Privileged Access Never support.
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@item @code{lor} @tab ARMv8-A @tab ARMv8-A or later
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@tab Enable Limited Ordering Regions extensions.
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@end multitable
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@node AArch64 Syntax
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@ -1,3 +1,9 @@
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2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
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* lor-directive.d: New.
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* lor.d: New.
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* lor.s: New
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2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
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* pan-directive.d: New.
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25
gas/testsuite/gas/aarch64/lor-directive.d
Normal file
25
gas/testsuite/gas/aarch64/lor-directive.d
Normal file
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@ -0,0 +1,25 @@
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#objdump: -dr
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#as: --defsym DIRECTIVE=1
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#source: lor.s
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.*: file format .*
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Disassembly of section \.text:
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0000000000000000 <.text>:
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0: 889f7c00 stllr w0, \[x0\]
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4: c89f7c00 stllr x0, \[x0\]
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8: 889f7c01 stllr w1, \[x0\]
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c: c89f7c22 stllr x2, \[x1\]
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10: 489f7c43 stllrh w3, \[x2\]
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14: 089f7c64 stllrb w4, \[x3\]
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18: 089f7fe5 stllrb w5, \[sp\]
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1c: 88df7c00 ldlar w0, \[x0\]
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20: c8df7c00 ldlar x0, \[x0\]
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24: 88df7c01 ldlar w1, \[x0\]
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28: c8df7c22 ldlar x2, \[x1\]
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2c: 08df7c43 ldlarb w3, \[x2\]
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30: 48df7c64 ldlarh w4, \[x3\]
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34: 88df7fe5 ldlar w5, \[sp\]
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23
gas/testsuite/gas/aarch64/lor.d
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23
gas/testsuite/gas/aarch64/lor.d
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@ -0,0 +1,23 @@
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#objdump: -dr
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#as: -march=armv8-a+lor
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.*: file format .*
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Disassembly of section \.text:
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0000000000000000 <.text>:
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0: 889f7c00 stllr w0, \[x0\]
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4: c89f7c00 stllr x0, \[x0\]
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8: 889f7c01 stllr w1, \[x0\]
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c: c89f7c22 stllr x2, \[x1\]
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10: 489f7c43 stllrh w3, \[x2\]
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14: 089f7c64 stllrb w4, \[x3\]
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18: 089f7fe5 stllrb w5, \[sp\]
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1c: 88df7c00 ldlar w0, \[x0\]
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20: c8df7c00 ldlar x0, \[x0\]
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24: 88df7c01 ldlar w1, \[x0\]
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28: c8df7c22 ldlar x2, \[x1\]
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2c: 08df7c43 ldlarb w3, \[x2\]
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30: 48df7c64 ldlarh w4, \[x3\]
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34: 88df7fe5 ldlar w5, \[sp\]
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43
gas/testsuite/gas/aarch64/lor.s
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43
gas/testsuite/gas/aarch64/lor.s
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@ -0,0 +1,43 @@
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/* lor.s Test file for AArch64 LOR extension instructions.
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Copyright (C) 2015 Free Software Foundation, Inc. Contributed by ARM Ltd.
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This file is part of GAS.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the license, or
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(at your option) any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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.text
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.ifdef DIRECTIVE
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.arch_extension lor
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.endif
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stllr w0, [x0]
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stllr x0, [x0]
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stllr w1, [x0]
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stllr x2, [x1]
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stllrh w3, [x2]
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stllrb w4, [x3]
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stllrb w5, [sp]
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ldlar w0, [x0]
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ldlar x0, [x0]
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ldlar w1, [x0]
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ldlar x2, [x1]
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ldlarb w3, [x2]
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ldlarh w4, [x3]
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ldlar w5, [sp]
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@ -1,3 +1,7 @@
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2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64.h (AARCH64_FEATURE_LOR): New.
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2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64.h (AARCH64_FEATURE_PAN): New.
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@ -40,6 +40,7 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
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#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
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#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
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#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
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/* Architectures are the sum of the base and extensions. */
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#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
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@ -1,3 +1,13 @@
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2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-tbl.h (aarch64_feature_lor): New.
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(LOR): New.
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(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
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"stllrb", "stllrh".
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc-2.c: Regenerate.
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2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-opc.c (F_ARCHEXT): New.
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@ -155,188 +155,188 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 595: /* ror */
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value = 594; /* --> extr. */
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break;
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case 746: /* bic */
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value = 745; /* --> and. */
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case 752: /* bic */
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value = 751; /* --> and. */
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break;
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case 748: /* mov */
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value = 747; /* --> orr. */
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case 754: /* mov */
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value = 753; /* --> orr. */
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break;
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case 751: /* tst */
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value = 750; /* --> ands. */
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case 757: /* tst */
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value = 756; /* --> ands. */
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break;
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case 756: /* uxtw */
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case 755: /* mov */
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value = 754; /* --> orr. */
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case 762: /* uxtw */
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case 761: /* mov */
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value = 760; /* --> orr. */
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break;
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case 758: /* mvn */
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value = 757; /* --> orn. */
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case 764: /* mvn */
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value = 763; /* --> orn. */
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break;
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case 762: /* tst */
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value = 761; /* --> ands. */
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case 768: /* tst */
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value = 767; /* --> ands. */
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break;
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case 888: /* staddb */
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value = 792; /* --> ldaddb. */
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case 894: /* staddb */
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value = 798; /* --> ldaddb. */
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break;
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case 889: /* staddh */
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value = 793; /* --> ldaddh. */
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case 895: /* staddh */
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value = 799; /* --> ldaddh. */
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break;
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case 890: /* stadd */
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value = 794; /* --> ldadd. */
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case 896: /* stadd */
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value = 800; /* --> ldadd. */
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break;
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case 891: /* staddlb */
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value = 796; /* --> ldaddlb. */
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case 897: /* staddlb */
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value = 802; /* --> ldaddlb. */
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break;
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case 892: /* staddlh */
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value = 799; /* --> ldaddlh. */
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case 898: /* staddlh */
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value = 805; /* --> ldaddlh. */
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break;
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case 893: /* staddl */
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value = 802; /* --> ldaddl. */
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case 899: /* staddl */
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value = 808; /* --> ldaddl. */
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break;
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case 894: /* stclrb */
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value = 804; /* --> ldclrb. */
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case 900: /* stclrb */
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value = 810; /* --> ldclrb. */
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break;
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case 895: /* stclrh */
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value = 805; /* --> ldclrh. */
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case 901: /* stclrh */
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value = 811; /* --> ldclrh. */
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break;
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case 896: /* stclr */
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value = 806; /* --> ldclr. */
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case 902: /* stclr */
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value = 812; /* --> ldclr. */
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break;
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case 897: /* stclrlb */
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value = 808; /* --> ldclrlb. */
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case 903: /* stclrlb */
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value = 814; /* --> ldclrlb. */
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break;
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case 898: /* stclrlh */
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value = 811; /* --> ldclrlh. */
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case 904: /* stclrlh */
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value = 817; /* --> ldclrlh. */
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break;
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case 899: /* stclrl */
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value = 814; /* --> ldclrl. */
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case 905: /* stclrl */
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value = 820; /* --> ldclrl. */
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break;
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case 900: /* steorb */
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value = 816; /* --> ldeorb. */
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case 906: /* steorb */
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value = 822; /* --> ldeorb. */
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break;
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case 901: /* steorh */
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value = 817; /* --> ldeorh. */
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case 907: /* steorh */
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value = 823; /* --> ldeorh. */
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break;
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case 902: /* steor */
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value = 818; /* --> ldeor. */
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case 908: /* steor */
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value = 824; /* --> ldeor. */
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break;
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case 903: /* steorlb */
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value = 820; /* --> ldeorlb. */
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case 909: /* steorlb */
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value = 826; /* --> ldeorlb. */
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break;
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case 904: /* steorlh */
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value = 823; /* --> ldeorlh. */
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case 910: /* steorlh */
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value = 829; /* --> ldeorlh. */
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break;
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case 905: /* steorl */
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value = 826; /* --> ldeorl. */
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case 911: /* steorl */
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value = 832; /* --> ldeorl. */
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break;
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case 906: /* stsetb */
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value = 828; /* --> ldsetb. */
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case 912: /* stsetb */
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value = 834; /* --> ldsetb. */
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break;
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case 907: /* stseth */
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value = 829; /* --> ldseth. */
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case 913: /* stseth */
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value = 835; /* --> ldseth. */
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break;
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case 908: /* stset */
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value = 830; /* --> ldset. */
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case 914: /* stset */
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value = 836; /* --> ldset. */
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break;
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case 909: /* stsetlb */
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value = 832; /* --> ldsetlb. */
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case 915: /* stsetlb */
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value = 838; /* --> ldsetlb. */
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break;
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case 910: /* stsetlh */
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value = 835; /* --> ldsetlh. */
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case 916: /* stsetlh */
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value = 841; /* --> ldsetlh. */
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break;
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case 911: /* stsetl */
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value = 838; /* --> ldsetl. */
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case 917: /* stsetl */
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value = 844; /* --> ldsetl. */
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break;
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case 912: /* stsmaxb */
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value = 840; /* --> ldsmaxb. */
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case 918: /* stsmaxb */
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value = 846; /* --> ldsmaxb. */
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break;
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case 913: /* stsmaxh */
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value = 841; /* --> ldsmaxh. */
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case 919: /* stsmaxh */
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value = 847; /* --> ldsmaxh. */
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break;
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case 914: /* stsmax */
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value = 842; /* --> ldsmax. */
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case 920: /* stsmax */
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value = 848; /* --> ldsmax. */
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break;
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case 915: /* stsmaxlb */
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value = 844; /* --> ldsmaxlb. */
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case 921: /* stsmaxlb */
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value = 850; /* --> ldsmaxlb. */
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break;
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case 916: /* stsmaxlh */
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value = 847; /* --> ldsmaxlh. */
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case 922: /* stsmaxlh */
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value = 853; /* --> ldsmaxlh. */
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break;
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case 917: /* stsmaxl */
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value = 850; /* --> ldsmaxl. */
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case 923: /* stsmaxl */
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value = 856; /* --> ldsmaxl. */
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break;
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case 918: /* stsminb */
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value = 852; /* --> ldsminb. */
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case 924: /* stsminb */
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value = 858; /* --> ldsminb. */
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break;
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case 919: /* stsminh */
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value = 853; /* --> ldsminh. */
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case 925: /* stsminh */
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value = 859; /* --> ldsminh. */
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break;
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case 920: /* stsmin */
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value = 854; /* --> ldsmin. */
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case 926: /* stsmin */
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value = 860; /* --> ldsmin. */
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break;
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case 921: /* stsminlb */
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value = 856; /* --> ldsminlb. */
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case 927: /* stsminlb */
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value = 862; /* --> ldsminlb. */
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break;
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case 922: /* stsminlh */
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value = 859; /* --> ldsminlh. */
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case 928: /* stsminlh */
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value = 865; /* --> ldsminlh. */
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break;
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case 923: /* stsminl */
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value = 862; /* --> ldsminl. */
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case 929: /* stsminl */
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value = 868; /* --> ldsminl. */
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break;
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case 924: /* stumaxb */
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value = 864; /* --> ldumaxb. */
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case 930: /* stumaxb */
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value = 870; /* --> ldumaxb. */
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break;
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case 925: /* stumaxh */
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value = 865; /* --> ldumaxh. */
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case 931: /* stumaxh */
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value = 871; /* --> ldumaxh. */
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break;
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case 926: /* stumax */
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value = 866; /* --> ldumax. */
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case 932: /* stumax */
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value = 872; /* --> ldumax. */
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break;
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case 927: /* stumaxlb */
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value = 868; /* --> ldumaxlb. */
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case 933: /* stumaxlb */
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value = 874; /* --> ldumaxlb. */
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break;
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case 928: /* stumaxlh */
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value = 871; /* --> ldumaxlh. */
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case 934: /* stumaxlh */
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value = 877; /* --> ldumaxlh. */
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break;
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case 929: /* stumaxl */
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value = 874; /* --> ldumaxl. */
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case 935: /* stumaxl */
|
||||
value = 880; /* --> ldumaxl. */
|
||||
break;
|
||||
case 930: /* stuminb */
|
||||
value = 876; /* --> lduminb. */
|
||||
case 936: /* stuminb */
|
||||
value = 882; /* --> lduminb. */
|
||||
break;
|
||||
case 931: /* stuminh */
|
||||
value = 877; /* --> lduminh. */
|
||||
case 937: /* stuminh */
|
||||
value = 883; /* --> lduminh. */
|
||||
break;
|
||||
case 932: /* stumin */
|
||||
value = 878; /* --> ldumin. */
|
||||
case 938: /* stumin */
|
||||
value = 884; /* --> ldumin. */
|
||||
break;
|
||||
case 933: /* stuminlb */
|
||||
value = 880; /* --> lduminlb. */
|
||||
case 939: /* stuminlb */
|
||||
value = 886; /* --> lduminlb. */
|
||||
break;
|
||||
case 934: /* stuminlh */
|
||||
value = 883; /* --> lduminlh. */
|
||||
case 940: /* stuminlh */
|
||||
value = 889; /* --> lduminlh. */
|
||||
break;
|
||||
case 935: /* stuminl */
|
||||
value = 886; /* --> lduminl. */
|
||||
case 941: /* stuminl */
|
||||
value = 892; /* --> lduminl. */
|
||||
break;
|
||||
case 937: /* mov */
|
||||
value = 936; /* --> movn. */
|
||||
case 943: /* mov */
|
||||
value = 942; /* --> movn. */
|
||||
break;
|
||||
case 939: /* mov */
|
||||
value = 938; /* --> movz. */
|
||||
case 945: /* mov */
|
||||
value = 944; /* --> movz. */
|
||||
break;
|
||||
case 950: /* sevl */
|
||||
case 949: /* sev */
|
||||
case 948: /* wfi */
|
||||
case 947: /* wfe */
|
||||
case 946: /* yield */
|
||||
case 945: /* nop */
|
||||
value = 944; /* --> hint. */
|
||||
case 956: /* sevl */
|
||||
case 955: /* sev */
|
||||
case 954: /* wfi */
|
||||
case 953: /* wfe */
|
||||
case 952: /* yield */
|
||||
case 951: /* nop */
|
||||
value = 950; /* --> hint. */
|
||||
break;
|
||||
case 959: /* tlbi */
|
||||
case 958: /* ic */
|
||||
case 957: /* dc */
|
||||
case 956: /* at */
|
||||
value = 955; /* --> sys. */
|
||||
case 965: /* tlbi */
|
||||
case 964: /* ic */
|
||||
case 963: /* dc */
|
||||
case 962: /* at */
|
||||
value = 961; /* --> sys. */
|
||||
break;
|
||||
default: return NULL;
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -145,24 +145,24 @@ static const unsigned op_enum_table [] =
|
|||
697,
|
||||
703,
|
||||
704,
|
||||
741,
|
||||
742,
|
||||
743,
|
||||
744,
|
||||
747,
|
||||
748,
|
||||
749,
|
||||
750,
|
||||
12,
|
||||
510,
|
||||
511,
|
||||
936,
|
||||
938,
|
||||
940,
|
||||
748,
|
||||
939,
|
||||
937,
|
||||
942,
|
||||
944,
|
||||
946,
|
||||
754,
|
||||
945,
|
||||
943,
|
||||
259,
|
||||
499,
|
||||
509,
|
||||
508,
|
||||
746,
|
||||
752,
|
||||
505,
|
||||
502,
|
||||
495,
|
||||
|
|
@ -171,7 +171,7 @@ static const unsigned op_enum_table [] =
|
|||
504,
|
||||
506,
|
||||
507,
|
||||
756,
|
||||
762,
|
||||
526,
|
||||
529,
|
||||
532,
|
||||
|
|
|
|||
|
|
@ -1222,6 +1222,8 @@ static const aarch64_feature_set aarch64_feature_crc =
|
|||
AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
|
||||
static const aarch64_feature_set aarch64_feature_lse =
|
||||
AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0);
|
||||
static const aarch64_feature_set aarch64_feature_lor =
|
||||
AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
|
||||
|
||||
#define CORE &aarch64_feature_v8
|
||||
#define FP &aarch64_feature_fp
|
||||
|
|
@ -1229,6 +1231,7 @@ static const aarch64_feature_set aarch64_feature_lse =
|
|||
#define CRYPTO &aarch64_feature_crypto
|
||||
#define CRC &aarch64_feature_crc
|
||||
#define LSE &aarch64_feature_lse
|
||||
#define LOR &aarch64_feature_lor
|
||||
|
||||
struct aarch64_opcode aarch64_opcode_table[] =
|
||||
{
|
||||
|
|
@ -2017,6 +2020,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
{"ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
|
||||
{"stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
|
||||
{"ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
|
||||
/* Limited Ordering Regions load/store instructions. */
|
||||
{"ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
|
||||
{"ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
|
||||
{"ldlarh", 0x48df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
|
||||
{"stllr", 0x889f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
|
||||
{"stllrb", 0x089f7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
|
||||
{"stllrh", 0x489f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
|
||||
/* Load/store no-allocate pair (offset). */
|
||||
{"stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
|
||||
{"ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
|
||||
|
|
|
|||
Loading…
Reference in a new issue