Commit graph

86 commits

Author SHA1 Message Date
Frank Ch. Eigler
5630c289dc * Adapt to changed R5900 SQC2 opcode.
Thu Jun 18 17:48:01 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* mips.igen (SDC2): Removed R5900 alternative.
	* r5900.igen (SQC2): Updated bit pattern to
	match changed R5900 specs.
1998-06-18 15:11:28 +00:00
Frank Ch. Eigler
702968c54b * ECC (tx39) and sky changes.
[ChangeLog]
start-sanitize-tx3904
Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* dv-tx3904tmr.c: Deschedule timer event after dispatching.
	Reduce unnecessarily high timer event frequency.
	* dv-tx3904cpu.c: Ditto for interrupt event.
end-sanitize-tx3904
start-sanitize-sky
Tue Jun 16 14:12:09 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* interp.c (decode_coproc): Removed COP2 branches.
	* r5900.igen: Moved COP2 branch instructions here.
	* mips.igen: Restricted COPz == COP2 bit pattern to
	exclude COP2 branches.
end-sanitize-sky
1998-06-16 18:13:47 +00:00
James Lemke
1106213c56 Fix unresolved external error for sky_cpcond0 on non-SKY builds. 1998-06-16 18:13:46 +00:00
James Lemke
05faca8731 Implement CPCOND0 and insns BC0F/BC0FL/BC0T/BC0TL. 1998-06-15 17:36:23 +00:00
Ian Carmichael
895a7dc2aa * Handle 10 and 20-bit versions of Break instruction. Move handling
* of special values from signal_exception() in interp.c into mips.igen.
*
* Modified: gencode.c interp.c mips.igen sim-main.h
1998-06-09 16:54:08 +00:00
Gavin Romig-Koch
2b5d87dfa4 * mips.igen (SWC1) : Correct the handling of ReverseEndian
and BigEndianCPU.
1998-06-09 15:54:05 +00:00
Andrew Cagney
0e797366ef The r5900 doesn't have HI/LO DIV/MUL register problems. Hobble
checks on hi/lo usage but retain functions so that they can be used
for HI/LO stall counting code.
1998-06-04 08:46:56 +00:00
Andrew Cagney
26feb3a83d Fix sign extension on 32 bit add/sub instructions. 1998-05-21 09:32:07 +00:00
Frank Ch. Eigler
3fa454e95f * Monster patch - may destablize MIPS sims for a little while.
* Followup patch for SCEI PR 15853
* First check-in of TX3904 interrupt controller devices for ECC. [sanitized]
* First implementation of MIPS hardware interrupt emulation.
Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 	modules.  Recognize TX39 target with "mips*tx39" pattern.
	* configure: Rebuilt.
	* sim-main.h (*): Added many macros defining bits in
 	TX39 control registers.
	(SignalInterrupt): Send actual PC instead of NULL.
	(SignalNMIReset): New exception type.
	* interp.c (board): New variable for future use to identify
	a particular board being simulated.
	(mips_option_handler,mips_options): Added "--board" option.
	(interrupt_event): Send actual PC.
	(sim_open): Make memory layout conditional on board setting.
	(signal_exception): Initial implementation of hardware interrupt
 	handling.  Accept another break instruction variant for simulator
 	exit.
	(decode_coproc): Implement RFE instruction for TX39.
	(mips.igen): Decode RFE instruction as such.
start-sanitize-tx3904
	* configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
	* interp.c: Define "jmr3904" and "jmr3904debug" board types and
	bbegin to implement memory map.
	* dv-tx3904cpu.c: New file.
	* dv-tx3904irc.c: New file.
end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
Gavin Romig-Koch
94dda41a0c * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
Replace check_op_hilo with check_mult_hilo and check_div_hilo.
	Add special r3900 version of do_mult_hilo.
	(do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
	with calls to check_mult_hilo.
	(do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
	with calls to check_div_hilo.
1998-05-13 14:00:56 +00:00
Andrew Cagney
97f4d18341 Implement ERET instruction.
Add {signed,unsigned}_address type.
1998-04-21 04:30:27 +00:00
Andrew Cagney
421cbaae98 For new IGEN simulators, rewrite checks validating correct use of the
HI/LO registers.  For old gencode simulator, delete all checks.
1998-04-21 01:17:58 +00:00
Andrew Cagney
74025eeea7 Re-fix 32 bit DSRAV instruction.
Fix mips16 BRANCH, unsigned ADD/SUB and SRAV instructions.
1998-04-15 14:04:01 +00:00
Andrew Cagney
f3bdd368ea Debug tx19 built from igen sources.
Rework ifetch{16,32} to match the more recent do_load function.
1998-04-15 07:23:28 +00:00
Andrew Cagney
c0a4c3ba17 Implement 32 bit MIPS16 instructions listed in m16.igen. 1998-04-14 14:34:48 +00:00
Frank Ch. Eigler
ebcfd86a2e * R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF
masking facility for PATH3 transfers.

[ChangeLog.sky]

Sun Apr  5 12:11:45 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* sky-libvpe.c (exec-inst): Added "M" bit detection for upper
 	instruction.

	* sky-pke.c (pke_check_stall): Added more assertions.
	(pke_code_mskpath3): Use new GPUIF M3P control register.

	* sky-pke.h (VU[01]_CIA): New macros that give VU CIA
 	pseudo-register addresses.

	* sky-vu.h (vu_device, VectorUnitState): Merged structs.
	(VectorUnitState.mflag): New field.
	(VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers.

	* sky-vu.c (vu0_busy): New function.
	(vu0_q_busy): New function.
	(vu0_macro_issue): New function.
	(vu0_micro_interlock_released): New function.
	(vu0_busy_in_{micro,macro}_mode): Deleted stubs.
	(vu0_macro_hazard_check): Deleted stubs.
	(vu_attach): Adapted code to merged device & state struct.
	(read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register.

[ChangeLog]
start-sanitize-sky
Sun Apr  5 12:05:44 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* interp.c (*): Adapt code to merged VU device & state structs.
	(decode_coproc): Execute COP2 each macroinstruction without
 	pipelining, by stepping VU to completion state.  Adapted to
	read_vu_*_reg style of register access.

	* mips.igen ([SL]QC2): Removed these COP2 instructions.

	* r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.

	* sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.

end-sanitize-sky
1998-04-05 16:40:03 +00:00
Andrew Cagney
725fc5d927 For mips get_mem_size call. Force the return of a 32 bit value
regardless of the target's word bitsize.
1998-04-02 03:27:24 +00:00
Frank Ch. Eigler
6b0c51c929 * You bop one on the head ... another one appears.
Wed Apr 1 08:20:31 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
1998-04-01 13:19:07 +00:00
Frank Ch. Eigler
15232df4a3 * Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code
into single PKE-style vu.[ch].


[ChangeLog]

Fri Mar 27 16:19:29 1998  Frank Ch. Eigler  <fche@cygnus.com>

start-sanitize-sky
	* Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.

	* interp.c (sim_{load,store}_register): Use new vu[01]_device
 	static to access VU registers.
	(decode_coproc): Added skeleton of sky COP2 (VU) instruction
 	decoding.  Work in progress.

	* mips.igen (LDCzz, SDCzz): Removed *5900 case for this
 	overlapping/redundant bit pattern.
	(LQC2, SQC2): Added *5900 COP2 instruction skeleta.  Work in
	progress.

	* sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
 	status register.

end-sanitize-sky

	* interp.c (cop_lq, cop_sq): New functions for future 128-bit
 	access to coprocessor registers.

	* sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.

[ChangeLog.sky]

	* sky-engine.c (engine_run): Adapted from vu[01] -> vu merge.

	* sky-hardware.c (register_devices): Ditto

	* sky-pke.c (pke_fifo_*): Made these functions private again, now
 	that the GPUIF code does not use them.

	* sky-pke.h (pke_fifo_*): Removed newly private declarations.

	* sky-vu.c (*): Major rework: merge of old sky-vu0.c and
 	sky-vu1.c.  Management of two VU devices parallels two PKEs.
	Work in progress.

	* sky-vu.h (*): Other half of merge.
	(vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00
Andrew Cagney
ca6f76d135 Fix DIV, DIV1 (wrong check for overflow) and DIVU1 (shouldn't check
for overflow).
Pacify GCC.
1998-03-03 05:39:49 +00:00
Andrew Cagney
f89c0689a1 Finish implementation of r5900 instructions. 1998-02-25 15:31:15 +00:00
Andrew Cagney
a48e8c8d21 sim-main.h: Re-arange r5900 registers so that they have their own
little struct.
interp.c: Update.  Also add floating point Max/Min functions.
mips.igen: Remove r5900 tag from any floating point instructions.
r5900.igen: Rewrite.  Implement *all* floating point insns (except ld/st).
r5400.igen: Tag mdmx functions as being mdmx specific.
1998-02-23 16:55:38 +00:00
Jeff Law
23850e9219 * mips.igen (MSUB): Fix to work like MADD.
* gencode.c (MSUB): Similarly.
1997-12-11 00:11:04 +00:00
Andrew Cagney
a94c5493a7 Make the signess of compares between GPR's explicit using a cast to
signed_word.
1997-11-11 12:31:24 +00:00
Andrew Cagney
030843d7f8 Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1,
SWXC1MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1, MULT, MULTU, BEQZ, ...MTHI,
MFHI instructions.
Trace nullified instruction.
1997-11-11 07:50:13 +00:00
Andrew Cagney
7ce8b9178c IGEN likes to cache the current instruction address (CIA). Change the
MIPS simulator so that correctly writes the value of CIA back int PC
(the global previously used) when the simulation halts.
Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-06 09:16:16 +00:00
Andrew Cagney
63be8febf7 Rewrite the MIPS simulator's memory model so that it uses the generic
common/sim-core.

Add support for 3, 5, 6, 7 byte transfers to sim core.
1997-11-05 08:17:26 +00:00
Andrew Cagney
01b9cd49ca common/sim-bits.h: Document ROTn macro.
igen/{igen.c,ld-insns.h}: Document mnemonic string formats.
mips/Makefile.in: Add dependencies for files included by mips.igen
mips/vr5400.igen: checkpoint vr5400 instructions.
1997-10-29 04:02:30 +00:00
Andrew Cagney
89d0973831 Add support for 16 byte quantities to sim-endian macro H2T.
Add model-filter field to option, include, model anf function igen records
1997-10-28 07:10:36 +00:00
Andrew Cagney
16bd5d6e52 Separate r5900 specifoc and mips16 instructions.
Add support for this to configure (vr5400 target only)
1997-10-27 07:55:24 +00:00
Andrew Cagney
90ad43b2de Add mips64vr5400 to configuration list
Mark mipsIV instructions as being implemented by the vr5400.
Sanitize.
1997-10-27 06:42:13 +00:00
Andrew Cagney
49a7683337 Checkpoint IGEN version of mips sim 1997-10-24 06:38:44 +00:00
Andrew Cagney
085c1cb988 Checkpoint IGEN version of MIPS simulator. 1997-10-16 03:41:57 +00:00
Andrew Cagney
055ee2977f Checkpoint IGEN version of MIPS simulator. 1997-10-14 09:34:08 +00:00
Andrew Cagney
49a6eed58a Snap. Gets through igen's checks. 1997-10-09 08:38:22 +00:00
Andrew Cagney
f2b3001251 MIPS/IGEN checkpoint - doesn't build. 1997-10-08 04:16:01 +00:00