* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
* mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
immediate or code as a hex value with the "%#lx" format.
(ANDI): Likewise, and fix printed instruction name.
* mips.igen (check_fpu): Enable check for coprocessor 1 usability.
* sim-main.h (COP_Usable): Define, but for now coprocessor 1
is always enabled.
(SignalExceptionCoProcessorUnusable): Take as argument the
unusable coprocessor number.
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
* mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
add a comma) so that it more closely match the MIPS ISA
documentation opcode partitioning.
(PREF): Put useful names on opcode fields, and include
instruction-printing string.
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
* mips.igen (do_load_left, do_load_right): Move to be immediately
following do_load.
(do_store_left, do_store_right): Move to be immediately following
do_store.
* mips.igen: Add some additional comments about supported
models, and about which instructions go where.
(BC1b, MFC0, MTC0, RFE): Sort supported models in the same
order as is used in the rest of the file.
* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
indicating that ALU32_END or ALU64_END are there to check
for overflow.
(DADD): Likewise, but also remove previous comment about
overflow checking.
* mips.igen (ADDI): Print immediate value.
(BREAK): Print code.
(DADDIU, DSRAV, DSRLV): Print correct instruction name.
(SLL): Print "nop" specially, and don't run the code
that does the shift for the "nop" case.
PENDING_FILL. Use PENDING_SCHED directly to handle the pending
set of the FCSR.
* sim-main.h (COCIDX): Remove definition; this isn't supported by
PENDING_FILL, and you can get the intended effect gracefully by
calling PENDING_SCHED directly.
* merge from internal repo -> sourceware
2000-03-02 Frank Ch. Eigler <fche@redhat.com>
* configure: Regenerated.
Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
* interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
calls, conditional on the simulator being in verbose mode.
1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
(load_word): Call SIM_CORE_SIGNAL hook on error.
(signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
starting. For exception dispatching, pass PC instead of NULL_CIA.
(decode_coproc): Use COP0_BADVADDR to store faulting address.
* sim-main.h (COP0_BADVADDR): Define.
(SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
(SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
(_sim_cpu): Add exc_* fields to store register value snapshots.
* mips.igen (*): Replace memory-related SignalException* calls
with references to SIM_CORE_SIGNAL hook.
* dv-tx3904irc.c (tx3904irc_port_event): printf format warning
fix.
* sim-main.c (*): Minor warning cleanups.
Set mips_fpu, and mips_fpu_bitsize.
Set sim_gen, and sim_igen_machine.
* configure: Rebuild.
* mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
* sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
