2002-03-03 Chris Demetriou <cgd@broadcom.com>
* mips.igen: Remove whitespace at end of lines.
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f42ce16e2f
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4a0bd8769a
2 changed files with 16 additions and 12 deletions
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@ -1,3 +1,7 @@
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2002-03-03 Chris Demetriou <cgd@broadcom.com>
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* mips.igen: Remove whitespace at end of lines.
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2002-03-02 Chris Demetriou <cgd@broadcom.com>
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* mips.igen (loadstore_ea): New function to do effective
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@ -130,7 +130,7 @@
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// Helper:
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//
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//
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// Check that an access to a HI/LO register meets timing requirements
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//
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// The following requirements exist:
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@ -148,7 +148,7 @@
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sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
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itable[MY_INDEX].name,
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new, (long) CIA,
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(long) history->mf.cia);
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(long) history->mf.cia);
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return 0;
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}
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return 1;
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@ -206,7 +206,7 @@
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itable[MY_INDEX].name,
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(long) CIA,
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(long) history->op.cia,
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(long) peer->mt.cia);
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(long) peer->mt.cia);
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ok = 0;
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}
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history->mf.timestamp = time;
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@ -272,7 +272,7 @@
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// Helper:
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//
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//
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// Check that the 64-bit instruction can currently be used, and signal
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// an ReservedInstruction exception if not.
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//
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@ -834,7 +834,7 @@
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else
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{
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/* If we get this far, we're not an instruction reserved by the sim. Raise
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/* If we get this far, we're not an instruction reserved by the sim. Raise
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the exception. */
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SignalException(BreakPoint, instruction_0);
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}
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@ -1100,7 +1100,7 @@
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unsigned64 op2 = GPR[rt];
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check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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/* make signed multiply unsigned */
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/* make signed multiply unsigned */
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sign = 0;
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if (signed_p)
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{
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@ -3036,13 +3036,13 @@
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}
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// Helper:
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//
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//
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// Check that the FPU is currently usable, and signal a CoProcessorUnusable
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// exception if not.
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//
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:function:::void:check_fpu:
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*mipsI:
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*mipsI:
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*mipsII:
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*mipsIII:
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*mipsIV:
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@ -3484,7 +3484,7 @@
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else
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{
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if (STATE_VERBOSE_P(SD))
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sim_io_eprintf (SD,
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sim_io_eprintf (SD,
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"Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
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(long) CIA);
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PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
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@ -3517,7 +3517,7 @@
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else
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{
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if (STATE_VERBOSE_P(SD))
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sim_io_eprintf (SD,
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sim_io_eprintf (SD,
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"Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
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(long) CIA);
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GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
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@ -3595,7 +3595,7 @@
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110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
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110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
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"lwc1 f<FT>, <OFFSET>(r<BASE>)"
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*mipsI:
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*mipsII:
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@ -3667,7 +3667,7 @@
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if (SizeFGR() == 64)
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{
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if (STATE_VERBOSE_P(SD))
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sim_io_eprintf (SD,
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sim_io_eprintf (SD,
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"Warning: PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
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(long) CIA);
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PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
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