darkkirb/old-cross-binutils
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960 commits

Author SHA1 Message Date
Felix Lee
8f80453197 * configure.in: i386-windows is a cross, so don't expect 
libiberty to be there.
	* configure: updated.
 1997-09-23 03:48:59 +00:00
Andrew Cagney
92f91d1ff0 Remove need to update <targ>/Makefile.in when adding optional options 
to <targ>/configure.in.
Simplify logic used to select target [default] endianness.
 1997-09-23 01:25:26 +00:00
Andrew Cagney
76a6247f07 Add memory alignment config option. 1997-09-22 09:40:57 +00:00
Andrew Cagney
8d332f9c1a Enable --alignment option, stop sim-options.c hardwiring the alignment. 1997-09-22 09:34:28 +00:00
Andrew Cagney
4ca7d6d25b Fix disabling of model code when simulator does not support modeling. 
Stops `-p' crashing simulators.
 1997-09-22 09:16:14 +00:00
Andrew Cagney
794e9ac96a Simplify logic behind the generic configuration option --enable-sim-alignment. 1997-09-22 02:49:57 +00:00
Andrew Cagney
b45caf050c Add support for --enable-sim-alignment to simulator common aclocal.m4 
Add support for --alignment={strict,nonstrict,forced} to simulator common
run-time options.
For v850 use, make the default NONSTRICT_ALIGNMENT.
 1997-09-22 00:24:46 +00:00
Nick Clifton
f13f11b494 Removed the v850eq sanitization 1997-09-20 23:40:50 +00:00
Gavin Romig-Koch
c476ac5560 Add handling for 3900's SDBBP, DERET, and RFE insns. 
* gencode.c (SDBBP,DERET): Added (3900) insns.
	(RFE): Turn on for 3900.
	* interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
	(dsstate): Made global.
	(SUBTARGET_R3900): Added.
	(CANCELDELAYSLOT): New.
	(SignalException): Ignore SystemCall rather than ignore and
	terminate.  Add DebugBreakPoint handling.
	(decode_coproc): New insns RFE, DERET; and new registers Debug
	and DEPC protected by SUBTARGET_R3900.
	(sim_engine_run): Use CANCELDELAYSLOT rather than clearing
	bits explicitly.
	* Makefile.in,configure.in: Add mips subtarget option.
	* configure: Update.
 1997-09-20 18:22:22 +00:00
Gavin Romig-Koch
7afa8d4edc * gencode.c: Add r3900 (tx39). 
* gencode.c: Fix some configuration problems by improving
	the relationship between tx19 and tx39.
 1997-09-19 13:39:55 +00:00
Andrew Cagney
8122e3e471 Add alignment option. 
Add support for hardwired and default alignment to configuration.
 1997-09-19 08:11:40 +00:00
Andrew Cagney
f4822f1e6e More tests. 
Have sld check verify that the processor is a v850eq.
 1997-09-19 06:40:11 +00:00
Andrew Cagney
a276b6f057 Clean up tracing for Bcond & jmp insns. 
Fix computation of disp16 and disp22.
Clean up tracing of sld* insns.
 1997-09-19 06:39:21 +00:00
Andrew Cagney
4410c4b925 Correctly locate `_' in generated names. 1997-09-19 04:41:01 +00:00
Andrew Cagney
bd4c35cc6d Fix cmov immed. 1997-09-19 02:20:02 +00:00
Andrew Cagney
6a4c8f1e29 Change semantic function name to semantic_<INSN>_<FMT> instead of 
semantic_<FMT>_<INSN>.
 1997-09-19 00:50:24 +00:00
Andrew Cagney
60fe0e06a8 Fix cmov insn. 1997-09-19 00:50:19 +00:00
Felix Lee
3e906c081a sanitization fixes. typoes, missing fences, "start" instead of "end", etc. 1997-09-18 06:03:52 +00:00
Felix Lee
88770c1c90 add missing files. 1997-09-18 04:56:22 +00:00
Felix Lee
e1625ed217 v850 files that weren't being removed if !keep-v850 1997-09-18 01:33:24 +00:00
Felix Lee
2001e533ff * sim-main.h (kill): macro was missing args. 
(SIGTRAP): define for MSVC.
 1997-09-17 23:46:49 +00:00
Andrew Cagney
8bd89725a7 Test US bit of v850eq. 
Loop program for testing interrupt delivery.
 1997-09-17 13:46:29 +00:00
Andrew Cagney
a72f8fb439 Clean up more tracing. 
FIX interrupt delivery - was zapping PSW before it had been saved.
FIX interrupt return, was one instruction out.
 1997-09-17 08:14:23 +00:00
Andrew Cagney
175c6fd375 * sim-events.c (ETRACE): Use trace_printf not sim_io_printf for 
trace output.
* sim-core.c (sim_core_signal): When bad access halt simulator
SIGSEGV / SIGBUS instead of aborting.
(signal.h): Include.
* sim-watch.c (sim_watchpoint_install): Handler for watchpoint
options was missing.
 1997-09-17 08:13:07 +00:00
Andrew Cagney
6aead89a5f Fix tracing for: "ctret", "bsw", "hsw" 
Fix bugs in: "bsh", "callt", "stsr".
 1997-09-17 05:31:00 +00:00
Andrew Cagney
dfa5c0ca02 Define MOVED macro, move sub-bitfield from XXX to YYY. 1997-09-17 05:28:32 +00:00
Andrew Cagney
fc07e279aa More v850 simulator tests. 1997-09-17 05:27:56 +00:00
Andrew Cagney
1a6eb36b62 More v850 simulator tests. 1997-09-17 03:31:09 +00:00
Andrew Cagney
b52e58c24f Add/test 8bit bit manipuation macros. 
Test LS and MS versions of SEXT macro.
Simplify/test macro returning a single bit.
 1997-09-17 03:25:54 +00:00
Andrew Cagney
8603b0f0ff Generic rules for building simple simulator test programs. 1997-09-16 23:57:57 +00:00
Gavin Romig-Koch
667065d0d4 * sim/mips/gencode.c (build_instruction): Don't need to subtract 4 for 
JALR, just 2.
 1997-09-16 20:01:00 +00:00
Gavin Romig-Koch
9cb8397f86 * sim/mips/interp.c: Correct some HASFPU problems. 1997-09-16 15:36:18 +00:00
Andrew Cagney
fb1fd47514 Smooth some of ALU tracing's rough edges. 
Fix switch insn.
 1997-09-16 14:00:15 +00:00
Andrew Cagney
6a0f95864a More sim-bits testing. 1997-09-16 13:58:44 +00:00
Andrew Cagney
aa5e6a5a78 Add {LS,MS}SEXT and {LS,MS}INSERTED macros. Eliminates bug in SEXT. 1997-09-16 07:04:46 +00:00
Andrew Cagney
3f33acd039 Use trace_one_insn in trace functions. Buffer up trace data so that 
it is displayed in a single block.
 1997-09-16 07:03:41 +00:00
Andrew Cagney
65a87fa9e1 v850eq simulator tests. 1997-09-16 07:01:57 +00:00
Andrew Cagney
c7db488f71 Restrict ldsr (load system register) to modifying just non-reserved PSW bits. 
For v850eq, include PSW[US] in bits that can be modified.
 1997-09-16 04:49:24 +00:00
Andrew Cagney
721478d51b Add v850e version of breakpoint instruction. 1997-09-16 02:15:55 +00:00
Andrew Cagney
3484de0091 Differentiate between a non-zero string and a constant zero field. 1997-09-16 02:14:18 +00:00
Jim Wilson
5262de2167 * simops.c (Multiply64): Don't store into register zero. 1997-09-16 01:45:23 +00:00
Andrew Cagney
4dda50b052 For instructions moved into v850.igen was computing (wrong) NIA when 
this wasn't needed.
 1997-09-15 23:09:26 +00:00
Andrew Cagney
0604253676 * igen.c (gen_run_c): Handle non-multi-sim case. 1997-09-15 22:40:14 +00:00
Andrew Cagney
bda6163995 Fix sanitization for v850 V v850e V v850eq 1997-09-15 14:42:51 +00:00
Andrew Cagney
a2ab5e65eb Update to reflect change to sim/common/aclocal.m4 (allow sim/common 
directory to specify its own unqiue config.h file).
 1997-09-15 08:25:04 +00:00
Andrew Cagney
658303f7d4 For v850eq start up with US bit set. 
Let sim_analyze_program determine the architecture.
Fix various sanitizations.
 1997-09-15 08:18:20 +00:00
Andrew Cagney
08547b1f1d Determine ARCHITECTURE from program if possible. 
Rename common's generated config.h to cconfig.h.
 1997-09-15 08:11:50 +00:00
Andrew Cagney
4bdab45adb * callback.c (os_write): divert stdout and stderr to their 
respective hooks.
 1997-09-15 08:02:23 +00:00
Andrew Cagney
410230cf6d Check reserved bits before executing instructions. 
Make v850[eq] the the default simulator.
Report illegal instructions.
Include v850e instructions in v850eq.
 1997-09-12 05:56:38 +00:00
Andrew Cagney
944deab68e v850eq wasn't building igen directory. 1997-09-12 03:13:27 +00:00