* mips16-opc.c: New file.
* mips-dis.c: Include "elf-bfd.h" and "elf/mips.h".
(mips16_reg_names): New static array.
(print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or
after seeing a 16 bit symbol.
(print_insn_little_mips): Likewise.
(print_insn_mips16): New static function.
(print_mips16_insn_arg): New static function.
* mips-opc.c: Add jalx instruction.
* Makefile.in (mips16-opc.o): New target.
* configure.in: Use mips16-opc.o for bfd_mips_arch.
* configure: Rebuild.
specifier of the effective-address operand in immediate forms of
arithmetic instructions. The specifier for the immediate operand
notes how and where the constant will be stored.
addresses symbolically if possible.
* mn10300-opc.c: Distinguish between absolute memory addresses,
pc-relative offsets & random immediates.
More disassembler work.
* mn10300-opc.c (mn10300_opcodes): Fix masks on several insns.
Selects opcodes & consumes bytes. Breaks badly if given data instead of
code. No operands yet.
in MN10300_OPERAND_SPLIT operands for how many bits
appear in the basic insn word. Add IMM32_HIGH24,
IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
(mn10300_opcodes): Use new operands as needed.
Support for everything in the basic instruction manual (yippie!)
operands. Update opcode table as appropriate.
(IMM32): Add MN10300_OPERAND_SPLIT flag.
(mn10300_opcodes): Fix single bit error in mov imm32,dn insn.
Cleaning up a little.
Attempting to insert most 32bit operands.
And a bug found by assembler testsuite.
operands (for indexed load/stores). Fix bitpos for DI
operand. Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the
few instructions that insert immediates/displacements in the
middle of the instruction. Add IMM8E for 8 bit immediate in
the extended part of an instruction.
(mn10300_operands): Use new opcodes as appropriate.
Opcode table changes so we can correctly insert everything except
32bit operands.
a data/address register that appears in register field 0
and register field 1.
(mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN
Hacking Matsushita again. Yippie!
* alpha-dis.c (print_insn_alpha): Use new NOPAL mask for
standard disassembly.
* alpha-opc.c (alpha_operands): Rearrange flags slot.
(alpha_opcodes): Add new BWX, CIX, and MAX instructions.
Recategorize PALcode instructions.
field for movhu instruction.
Bug found by gas testsuite.
* v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands,
cast value to "long" not "signed long" to keep hpux10
compiler quiet.
Found in an attempt to build the v850 on hpux10 with the HP
compiler.
Fix various typos. Add "PAREN" operand.
(MEM, MEM2): Define.
(mn10300_opcodes): Surround all memory addresses with "PAREN"
operands. Fix several typos.
Should parse all opcodes in the instruction specification, except the
"user extension instructions".
(mn10300_operands): Rough cut. Enough to parse "mov" instructions
at this time.
(mn10300_opcodes): Break opcode format out into its own field.
Update many operand fields to deal with signed vs unsigned
issues. Fix one or two typos in the "mov" instruction
opcode, mask and/or operand fields.
Checkpointing today's work. Matsushita.
']' characters into the output stream.
* v850-opc.c (v850_opcodes: Remove size field from all opcodes.
Add "memop" field to all opcodes (for the disassembler).
Reorder opcodes so that "nop" comes before "mov" and "jr"
comes before "jarl".
Should give us a functional disassembler.
(v850_sreg_names, v850_cc_names): Likewise.
(disassemble): Very rough cut at printing operands (unformatted).
One step at a time.
* v850-opc.c (BOP_MASK): Fix.
(v850_opcodes): Fix mask for jarl and jr.
Bugs exposed by disassembler testing.
* Makefile.in Remove v850 references, they're not needed here
and they weren't being sanitized away.
* configure.in: Add v850-dis.o when building v850 toolchains.
* configure: Rebuilt.
* disassemble.c (disassembler): Call v850 disassembler.
Skeleton support for V850 disassembler.
(insert_d8_6, extract_d8_6): New functions.
(v850_operands): Rename D7S to D7; operand for D7 is unsigned.
Rename D8 to D8_7, use {insert,extract}_d8_7 routines.
Add D8_6.
(IF4A, IF4B): Use "D7" instead of "D7S".
(IF4C, IF4D): Use "D8_7" instead of "D8".
(IF4E, IF4F): New. Use "D8_6".
(v850_opcodes): Use IF4A/IF4B for sld.b/sst.b. Use IF4C/IF4D for
sld.h/sst.h. Use IF4E/IF4F for sld.w/sst.w.
So we can assemble sst/sld instructions correctly.
(v850_operands): Change D16 to D16_15, use special insert/extract
routines. New new D16 that uses the generic insert/extract code.
(IF7A, IF7B): Use D16_15.
(IF7C, IF7D): New. Use D16.
(v850_opcodes): Use IF7C and IF7D for ld.b and st.b.
Add D8 for 8-bit unsigned field in short load/store insns.
(IF4A, IF4D): These both need two registers.
(IF4C, IF4D): Define. Use 8-bit unsigned field.
(v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use
IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand
for "ldsr" and "stsr".
* v850-opc.c (v850_operands): 3-bit immediate for bit insns
is unsigned.
Fixing up the parser again.
* arm-opc.h: (arm_opcodes): Added halfword and sign-extension
memory transfer instructions. Add new format string entries %h and %s.
* arm-dis.c: (print_insn_arm): Provide decoding of the new
formats %h and %s.
(print_insn_alpha_vms): Remove.
(print_insn_alpha): Make globally visible. Chose the register
names based on info->flavour.
* disassemble.c: Always return print_insn_alpha for the alpha.
* d10v-opc.c: Changes to support signed and unsigned numbers.
All instructions with the same name that have long and short forms
now end in ".l" or ".s". Divs added.
* d10v-dis.c: Changes to support signed and unsigned numbers.
* m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
move ccr/sr insns more strict so that the disassembler only
selects them when the addressing mode is data register.
Mon Jul 22 11:25:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (pre_defined_registers): Declare.
* d10v-dis.c (print_operand): Now uses pre_defined_registers
to pick a better name for the registers.
end-sanitize-d10v
* alpha-dis.c (print_insn_alpha): No longer the user-visible
print routine. Take new regnames and cpumask arguments.
Kill the environment variable nonsense.
(print_insn_alpha_osf): New function. Do OSF/1 style regnames.
(print_insn_alpha_vms): New function. Do VMS style regnames.
* disassemble.c (disassembler): Test bfd flavour to pick
between OSF and VMS routines. Default to OSF.
the 8086 instruction set.
* i386-dis.c: General cleanups. Make most things static. Add
prototypes. Get rid of static variables aflags and dflags. Pass
them as args (to almost everything).
to just "mode".
start-sanitize-h8s
* disassemble.c (disassembler): Handle H8/S.
* h8300-dis.c (print_insn_h8300s): New function for H8/S.
end-sanitize-h8s
Even more H8/S goo.
not "abs", which may be needed for the absolute in something
like btst #0,@10:8. Print L_3 immediates separately from other
immediates. Change ABSMOV reference to ABS8MEM.
One day we'll actually disassemble btst #0,@10:8 correctly... But not
yet. hmse.
(current_arch_mask): New static global.
(compute_arch_mask): New static function.
(print_insn_sparc): Delete sparc_v9_p. New static local
current_mach. Resort opcode table if current_mach changes.
Generalize "insn not supported" test.
(compare_opcodes): Prefer supported opcodes to nonsupported ones.
Delete test for v9/!v9.
* sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK.
(v6notlet): Define.
(brfc): Split into CBR and FBR for coprocessor/fp branches.
(brfcx): Renamed to FBRX.
(condfc): Renamed to CONDFC. Pass v6notlet to CBR (standard
coprocessor mnemonics are not supported on the sparclet).
(condf): Renamed to CONDF.
(SLCBCC2): Delete F_ALIAS flag.
