* Makefile.in (ALL_MACHINES): Add v850-opc.o.
* configure: (bfd_v850v_arch) Add new case. * configure.in: (bfd_v850_arch) Add new case. * v850-opc.c: New file.
This commit is contained in:
J.T. Conklin
parent
3f5d1c2c1e
commit
6d1e1ee875
3 changed files with 239 additions and 0 deletions
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@ -31,6 +31,15 @@ else
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lose_these_too="${d10v_files} ${lose_these_too}"
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fi
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v850_files="v850-opc.c"
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if ( echo $* | grep keep\-v850 > /dev/null ) ; then
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keep_these_too="${v850_files} ${keep_these_too}"
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else
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lose_these_too="${v850_files} ${lose_these_too}"
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fi
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# All files listed between the "Things-to-keep:" line and the
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# "Files-to-sed:" line will be kept. All other files will be removed.
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# Directories listed in this section will have their own Sanitize
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@ -75,6 +84,7 @@ sh-dis.c
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sparc-dis.c
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sparc-opc.c
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sysdep.h
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v850-opc.c
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w65-dis.c
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w65-opc.h
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z8k-dis.c
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@ -141,6 +151,35 @@ else
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done
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fi
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v850_files="ChangeLog Makefile.in configure.in configure disassemble.c"
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if ( echo $* | grep keep\-v850 > /dev/null ) ; then
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for i in $v850_files ; do
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if test ! -d $i && (grep sanitize-v850 $i > /dev/null) ; then
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if [ -n "${verbose}" ] ; then
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echo Keeping v850 stuff in $i
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fi
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fi
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done
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else
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for i in $v850_files ; do
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if test ! -d $i && (grep sanitize-v850 $i > /dev/null) ; then
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if [ -n "${verbose}" ] ; then
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echo Removing traces of \"v850\" from $i...
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fi
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cp $i new
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sed '/start\-sanitize\-v850/,/end-\sanitize\-v850/d' < $i > new
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if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
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if [ -n "${verbose}" ] ; then
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echo Caching $i in .Recover...
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fi
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mv $i .Recover
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fi
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mv new $i
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fi
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done
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fi
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for i in * ; do
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if test ! -d $i && (grep sanitize $i > /dev/null) ; then
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echo '***' Some mentions of Sanitize are still left in $i! 1>&2
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@ -1,3 +1,12 @@
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start-sanitize-v850
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Tue Aug 20 14:41:03 1996 J.T. Conklin <jtc@hippo.cygnus.com>
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* Makefile.in (ALL_MACHINES): Add v850-opc.o.
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* configure: (bfd_v850v_arch) Add new case.
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* configure.in: (bfd_v850_arch) Add new case.
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* v850-opc.c: New file.
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end-sanitize-v850
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Mon Aug 19 15:21:38 1996 Doug Evans <dje@canuck.cygnus.com>
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* sparc-dis.c (print_insn_sparc): Handle little endian sparcs.
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191
opcodes/v850-opc.c
Normal file
191
opcodes/v850-opc.c
Normal file
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@ -0,0 +1,191 @@
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#include "ansidecl.h"
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#include "opcode/v850.h"
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/* regular opcode */
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#define OP(x) ((x & 0x3f) << 5)
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#define OP_MASK OP(0x3f)
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/* conditional branch opcode */
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#define BOP(x) ((0x0b << 7) | (x & 0x0f))
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#define BOP_MASK ((0x0b << 7) | 0x0f)
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/* one-word opcodes */
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#define one(x) ((unsigned int) (x))
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/* two-word opcodes */
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#define two(x,y) ((unsigned int) (y) | ((unsigned int) (x) << 16))
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const struct v850_operand v850_operands[] = {
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#define UNUSED 0
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{ 0, 0 },
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/* The R1 field in a format 1, 6, 7, or 9 insn. */
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#define R1 (UNUSED+1)
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{ 5, 0 },
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/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
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#define R2 (R1+1)
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{ 5, 11 },
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/* The IMM5 field in a format 2 insn. */
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#define I5 (R2+1)
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{ 5, 0 },
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#define IMM16 field in a format 6 insn. */
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#define I16 (I5+1)
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{ 16, 0 },
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/* The DISP6 field in a format 4 insn. */
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#define D6 (I16+1)
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{ 6, 1 },
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/* The DISP8 field in a format 3 insn. */
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#define D8 (D6+1)
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{ 9, 0 },
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/* The DISP16 field in a format 6 insn. */
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#define D16 (D8+1)
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{ 16, 0 },
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/* The DISP22 field in a format 4 insn. */
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#define D22 (D16+1)
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{ 16, 0 }
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} ;
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/* reg-reg instruction format (Format I) */
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#define IF1 {R1, R2}
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/* imm-reg instruction format (Format II) */
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#define IF2 {I5, R2}
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/* conditional branch instruction format (Format III) */
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#define IF3 {D8}
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/* 16-bit load/store instruction (Format IV) */
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#define IF4 {D6}
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/* Jump instruction (Format V) */
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#define IF5 {D22}
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/* 3 operand instruction (Format VI) */
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#define IF6 {R1, R2, I16}
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/* 32-bit load/store instruction (Format VII) */
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#define IF7 {R1, R2, D16}
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/* Bit manipulation function
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/* The opcode table.
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The format of the opcode table is:
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NAME OPCODE MASK { OPERANDS }
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NAME is the name of the instruction.
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OPCODE is the instruction opcode.
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MASK is the opcode mask; this is used to tell the disassembler
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which bits in the actual opcode must match OPCODE.
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OPERANDS is the list of operands.
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The disassembler reads the table in order and prints the first
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instruction which matches, so this table is sorted to put more
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specific instructions before more general instructions. It is also
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sorted by major opcode. */
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const struct v850_opcode v850_opcodes[] = {
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/* load/store instructions */
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/* XXX */
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/* arithmetic operation instructions */
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{ "add", OP(0x0e), OP_MASK, IF1 },
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{ "add", OP(0x12), OP_MASK, IF2 },
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{ "addi", OP(0x30), OP_MASK, IF6 },
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{ "sub", OP(0x0d), OP_MASK, IF1 },
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{ "subr", OP(0x0c), OP_MASK, IF1 },
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{ "mulh", OP(0x07), OP_MASK, IF1 },
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{ "mulh", OP(0x17), OP_MASK, IF2 },
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{ "mulhi", OP(0x37), OP_MASK, IF6 },
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{ "divh", OP(0x02), OP_MASK, IF1 },
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{ "cmp", OP(0x0f), OP_MASK, IF1 },
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{ "cmp", OP(0x13), OP_MASK, IF2 },
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/* XXX missing setf */
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/* saturated operation instructions */
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{ "satadd", OP(0x06), OP_MASK, IF1 },
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{ "satadd", OP(0x11), OP_MASK, IF2 },
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{ "satsub", OP(0x05), OP_MASK, IF1 },
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{ "satsubi", OP(0x33), OP_MASK, IF6 },
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{ "satsubr", OP(0x04), OP_MASK, IF1 },
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/* logical operation instructions */
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{ "tst", OP(0x0b), OP_MASK, IF1 },
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{ "or", OP(0x08), OP_MASK, IF1 },
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{ "ori", OP(0x34), OP_MASK, IF6 },
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{ "and", OP(0x0a), OP_MASK, IF1 },
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{ "andi", OP(0x36), OP_MASK, IF6 },
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{ "xor", OP(0x09), OP_MASK, IF1 },
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{ "xori", OP(0x35), OP_MASK, IF6 },
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{ "not", OP(0x01), OP_MASK, IF1 },
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{ "sar", OP(0x15), OP_MASK, IF2 },
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{ "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2} },
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{ "shl", OP(0x16), OP_MASK, IF2 },
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{ "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2} },
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{ "shr", OP(0x14), OP_MASK, IF2 },
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{ "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2} },
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/* branch instructions */
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{ "bv", BOP(0x0), BOP_MASK, IF3 },
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{ "bnv", BOP(0x8), BOP_MASK, IF3 },
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{ "bc", BOP(0x1), BOP_MASK, IF3 },
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{ "bl", BOP(0x1), BOP_MASK, IF3 },
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{ "bnc", BOP(0x9), BOP_MASK, IF3 },
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{ "bnl", BOP(0x9), BOP_MASK, IF3 },
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{ "bz", BOP(0x2), BOP_MASK, IF3 },
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{ "be", BOP(0x2), BOP_MASK, IF3 },
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{ "bnz", BOP(0xa), BOP_MASK, IF3 },
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{ "bne", BOP(0xa), BOP_MASK, IF3 },
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{ "bnh", BOP(0x3), BOP_MASK, IF3 },
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{ "bh", BOP(0xb), BOP_MASK, IF3 },
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{ "bn", BOP(0x4), BOP_MASK, IF3 },
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{ "bp", BOP(0xc), BOP_MASK, IF3 },
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{ "bt", BOP(0x5), BOP_MASK, IF3 },
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{ "bsa", BOP(0xd), BOP_MASK, IF3 },
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{ "blt", BOP(0x6), BOP_MASK, IF3 },
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{ "bge", BOP(0xe), BOP_MASK, IF3 },
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{ "ble", BOP(0x7), BOP_MASK, IF3 },
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{ "bgt", BOP(0xf), BOP_MASK, IF3 },
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{ "jmp", one(0x0060), one(0xffe0), IF1 },
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{ "jarl", one(0x0780), one(0xf83f), { R2,D22 } },
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{ "jr", one(0x0780), one(0xffe0), { D22 } },
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#if 0
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/* bit manipulation instructions */
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{ "set1", one(0x07c0), one(0xc7e0), {B3, R1, D16} },
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{ "not1", one(0x47c0), one(0xc7e0), {B3, R1, D16} },
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{ "clr1", one(0x87c0), one(0xc7e0), {B3, R1, D16} },
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{ "tst1", one(0xc7c0), one(0xc7e0), {B3, R1, D16} },
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#endif
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/* special instructions */
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{ "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0} },
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{ "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0} },
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{ "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0} },
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{ "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0} },
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#if 0
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{ "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5} },
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#endif
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{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), {0} },
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{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), {0} },
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{ "nop", one(0x00), one(0xff), {0} },
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} ;
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const int v850_num_opcodes =
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sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
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