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Use strtab with GC and suffix merging for .strtab This patch uses ELF strtab with GC and suffix merging support to create ELF .strtab section. There is some small memory overhead to use ELF strtab: ==14928== HEAP SUMMARY: ==14928== in use at exit: 3,276,318 bytes in 679 blocks ==14928== total heap usage: 1,544 allocs, 865 frees, 15,259,146 bytes allocated vs. ==14936== HEAP SUMMARY: ==14936== in use at exit: 3,276,318 bytes in 679 blocks ==14936== total heap usage: 1,532 allocs, 853 frees, 15,026,402 bytes allocated when running: ./ld-new -m elf_x86_64 -o tmpdir/ld-partial.o -r ldgram.o ldlex-wrapper.o lexsup.o ldlang.o mri.o ldctor.o ldmain.o plugin.o ldwrite.o ldexp.o ldemul.o ldver.o ldmisc.o ldfile.o ldcref.o eelf_x86_64.o eelf32_x86_64.o eelf_i386.o eelf_iamcu.o ei386linux.o eelf_l1om.o eelf_k1om.o ldbuildid.o The results are [32] .strtab STRTAB 0+ 3beff8 00407a 00 0 0 1 vs [32] .strtab STRTAB 0+ 3beff8 0041d8 00 0 0 1 It reduces the .strtab size by 350 bytes, about 2% Saving on libc.so from glibc is much more since libc.so has many alias symbols with the same suffix. For x32 glibc, [82] .strtab STRTAB 0+ 81b348 0159e7 00 0 0 1 vs [82] .strtab STRTAB 0+ 81b8bc 019e72 00 0 0 1 It reduces the .strtab size by 17547 bytes, about 16%. bfd/ PR gas/18451 * elf-bfd.h (elf_sym_strtab): New. (elf_link_hash_table): Add strtabcount, strtabsize and strtab. (_bfd_elf_stringtab_init): Removed. * elf.c (_bfd_elf_stringtab_init): Removed. (_bfd_elf_compute_section_file_positions): Replace bfd_strtab_hash/_bfd_elf_stringtab_init/_bfd_stringtab_free/ _bfd_stringtab_size with elf_strtab_hash/_bfd_elf_strtab_init/_bfd_elf_strtab_free/ _bfd_elf_strtab_size. Use _bfd_elf_strtab_add, _bfd_elf_strtab_finalize and _bfd_elf_strtab_offset to get st_name. (swap_out_syms): Likewise. * elflink.c (elf_final_link_info): Replace bfd_strtab_hash with elf_strtab_hash. Remove symbuf, symbuf_count, symbuf_size and shndxbuf_size. (elf_link_flush_output_syms): Removed. (elf_link_output_sym): Renamed to ... (elf_link_output_symstrtab): This. Replace _bfd_stringtab_add with _bfd_elf_strtab_add. Don't flush symbols to the file nor swap out symbols. (elf_link_swap_symbols_out): New. (elf_link_output_extsym): Replace elf_link_output_sym with elf_link_output_symstrtab. (elf_link_input_bfd): Likewise. (elf_final_link_free): Replace _bfd_stringtab_free with _bfd_elf_strtab_free. Remove symbuf. (bfd_elf_final_link): Replace _bfd_elf_stringtab_init with _bfd_elf_strtab_init. Don't set symbuf, symbuf_count, symbuf_size nor shndxbuf_size. Initialize strtabsize and strtab. Initialize symshndxbuf to -1 when number of sections >= 64K. Replace elf_link_output_sym/elf_link_output_sym with elf_link_output_symstrtab/elf_link_output_symstrtab. Don't call elf_link_flush_output_syms. Call _bfd_elf_strtab_finalize and elf_link_swap_symbols_out. Replace _bfd_stringtab_size and _bfd_stringtab_emit with _bfd_elf_strtab_size and _bfd_elf_strtab_emit. gas/testsuite/ PR gas/18451 * gas/elf/elf.exp: Run strtab. * gas/elf/strtab.d: New file. * gas/elf/strtab.s: Likewise. ld/testsuite/ PR gas/18451 * ld-elf/strtab.d: New file. * ld-elf/strtab.s: Likewise.
2015-06-25 15:16:00 +00:00
2015-06-25 H.J. Lu <hongjiu.lu@intel.com>
PR gas/18451
* gas/elf/elf.exp: Run strtab.
* gas/elf/strtab.d: New file.
* gas/elf/strtab.s: Likewise.
PPC sync instruction accepts invalid and incompatible operands ISA 2.07 added a new category called Elemental Memory Barriers that modifies the sync instruction to accept an additional operand ESYNC. Edmar added support for this insruction varient here: https://sourceware.org/ml/binutils/2012-02/msg00221.html Looking at this closer, I see that the insert_ls() function is misnamed (since it's attached to the ESYNC operand, not the LS operand) but more importantly, it is silently modifying the LS operand value behind the users back when the LS operand is either invalid or is incompatible with the new ESYNC operand. The ISA 2.07 doc has an Assembler Note that clearly states that assemblers that support the ESYNC operand should report all invalid uses of LS and ESYNC. This patch changes the assembler to error out on invalid and incompatible operand usage. opcodes/ * ppc-opc.c (insert_ls): Test for invalid LS operands. (insert_esync): New function. (LS, WC): Use insert_ls. (ESYNC): Use insert_esync. gas/testsuite/ * gas/ppc/e6500.s <sync>: Fix invalid test. * gas/ppc/e6500.d: Likewise.
2015-06-22 19:55:24 +00:00
2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
* gas/ppc/e6500.s <sync>: Fix invalid test.
* gas/ppc/e6500.d: Likewise.
Stop "objdump -d" from disassembling past a symbolic address. include * dis-asm.h (struct disassemble_info): Add stop_vma field. binuti * objdump.c (disassemble_bytes): Set the stop_vma field in the disassemble_info structure when disassembling code sections with -d. * doc/binutils.texi (objdump): Document the discrepancy between -d and -D. opcodes * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the requested region lies beyond it. * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when looking for 32-bit insns. * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading data. * sh-dis.c (print_insn_sh): Likewise. * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading blocks of instructions. * vax-dis.c (print_insn_vax): Check that the requested address does not clash with the stop_vma. tests * gas/arm/backslash-at.s: Add extra .byte directives so that the foo symbol does not appear to point half way through an instruction. * gas/arm/backslash-at.d: Update expected disassembly. * gas/i386/ilp32/x86-64-opcode-inval-intel.d: Likewise. * gas/i386/ilp32/x86-64-opcode-inval.d: Likewise. * gas/i386/x86-64-opcode-inval-intel.d: Likewise. * gas/i386/x86-64-opcode-inval.d: Likewise.
2015-06-22 15:53:27 +00:00
2015-06-22 Nick Clifton <nickc@redhat.com>
* gas/arm/backslash-at.s: Add extra .byte directives so that the
foo symbol does not appear to point half way through an
instruction.
* gas/arm/backslash-at.d: Update expected disassembly.
* gas/i386/ilp32/x86-64-opcode-inval-intel.d: Likewise.
* gas/i386/ilp32/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
Allow for optional operands with non-zero default values. ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand with the value of either a 0 or 1. It also defines an extended mnemonic with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1". I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the problem is, optional operands that are ommitted always default to the value 0, which is wrong in this case. I have added support for allowing non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE that specifies that the default operand value to be used is stored in the SHIFT field of the operand field immediately following this one. This fixes the rfebb issue. I also fixed the mftb and mfcr instructions so they use the same mechanism. This allows us to flag invalid uses of mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd]. include/opcode/ * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New. (ppc_optional_operand_value): New inline function. opcodes/ * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value. * ppc-opc.c (FXM4): Add non-zero optional value. (TBR): Likewise. (SXL): Likewise. (insert_fxm): Handle new default operand value. (extract_fxm): Likewise. (insert_tbr): Likewise. (extract_tbr): Likewise. gas/ * config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value. Allow for optional operands without insert functions. gas/testsuite/ * gas/ppc/power8.d: Fixup rfebb test results. * gas/ppc/a2.s: Fix invalid mfcr test. * gas/ppc/a2.d: Likewise.
2015-06-19 22:17:07 +00:00
2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
* gas/ppc/power8.d: Fixup rfebb test results.
* gas/ppc/a2.s: Fix invalid mfcr test.
* gas/ppc/a2.d: Likewise.
Add support for using the ADR alias in Thumb mode against nearby symbols. PR gas/18541 gas * config/tc-arm.c (md_apply_fix): Add support for ADR in thumb mode against a nearby symbol. tests * gas/arm/thumb.s: Add test of ADR against a nearby symbol. * gas/arm/thumb.d: Update expected output. * gas/arm/thumb-eabi.d: Likewise.
2015-06-18 09:23:16 +00:00
2015-06-18 Nick Clifton <nickc@redhat.com>
PR gas/18541
* gas/arm/thumb.s: Add test of ADR against a nearby symbol.
* gas/arm/thumb.d: Update expected output.
* gas/arm/thumb-eabi.d: Likewise.
Fix the computation of the addends for an ARM_TLS_LE32 reloc. PR gas/18481 bfd * elf32-arm.c (R_ARM_TLS_LE32): Set the special function to NULL. gas * config/tc-arm.c (tc_gen_reloc): Include BFD_RELOC_ARM_TLS_LE32 in the same case as BFD_RELOC_ARM_TLS_IS32. tests * gas/arm/tls.s: Add tests of the tpoff pseudo with a local symbol. * gas/arm/tls.d: Update expected output.
2015-06-18 09:18:42 +00:00
2015-06-18 Nick Clifton <nickc@redhat.com>
PR gas/18481
* gas/arm/tls.s: Add tests of the tpoff pseudo with a local
symbol.
* gas/arm/tls.d: Update expected output.
Add support for converting VLDR <reg>,=<constant> to a VMOV instruction when appropriate. PR gas/18500 gas * config/tc-arm.c (is_double_a_single): New function. (double_to_single): New function. (move_or_literal_pool): Add support for converting VLDR to VMOV. tests * gas/arm/vfpv2-ldr_immediate.s: New test case. * gas/arm/vfpv2-ldr_immediate.d: Expected disassembly. * gas/arm/vfpv3-ldr_immediate.s: New test case. * gas/arm/vfpv3-ldr_immediate.d: Expected disassembly. * gas/arm/vfpv3xd-ldr_immediate.s: New test case. * gas/arm/vfpv3xd-ldr_immediate.d: Expected disassembly.
2015-06-17 11:56:17 +00:00
2015-06-17 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
PR gas/18500
* gas/arm/vfpv2-ldr_immediate.s: New test case.
* gas/arm/vfpv2-ldr_immediate.d: Expected disassembly.
* gas/arm/vfpv3-ldr_immediate.s: New test case.
* gas/arm/vfpv3-ldr_immediate.d: Expected disassembly.
* gas/arm/vfpv3xd-ldr_immediate.s: New test case.
* gas/arm/vfpv3xd-ldr_immediate.d: Expected disassembly.
Add support for converting LDR Rx,=<imm> to MOV or MVN in Thumb2 mode. PR gas/18499 gas * config/tc-arm.c (move_or_literal_pool): Add support for LDR Rx,= to MOV.w or MVN.w for Thumb2. tests * gas/arm/thumb2_ldr_immediate_armv6.s: New test case. * gas/arm/thumb2_ldr_immediate_armv6.d: Expected disassembly. * gas/arm/thumb2_ldr_immediate_armv6t2.s: New test case. * gas/arm/thumb2_ldr_immediate_armv6t2.d: Expected disassembly.
2015-06-17 12:50:52 +00:00
PR gas/18499
* gas/arm/thumb2_ldr_immediate_armv6.s: New test case.
* gas/arm/thumb2_ldr_immediate_armv6.d: Expected disassembly.
* gas/arm/thumb2_ldr_immediate_armv6t2.s: New test case.
* gas/arm/thumb2_ldr_immediate_armv6t2.d: Expected disassembly.
[AArch64] Support id_mmfr4 system register 2015-06-16 Matthew Wahab <matthew.wahab@arm.com> opcodes/ * aarch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1". gas/testsuite * sysreg.d: Add id_mmfr4_el1, update expected output. * sysreg.s: Add id_mmfr4_el1.
2015-06-16 13:15:54 +00:00
2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
* sysreg.d: Add id_mmfr4_el1, update expected output.
* sysreg.s: Add id_mmfr4_el1.
[AArch64] Gas add BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 support 2015-06-15 Renlin Li <renlin.li@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_LD64_GOTOFF_LO15): New entry. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_LD64_GOTOFF_LO15. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifier. (md_apply_fix): Support BFD_RELOC_AARCH64_LD64_GOTOFF_LO15. (aarch64_force_relocation): Ditto gas/testsuite/ * gas/aarch64/reloc-insn.s: Update test * gas/aarch64/reloc-insn.d: Update expected result.
2015-06-15 10:07:37 +00:00
2015-06-15 Renlin Li <renlin.li@arm.com>
* gas/aarch64/reloc-insn.s: Update test
* gas/aarch64/reloc-insn.d: Update expected result.
gas: Don't use frag_align but use plain padding to align .debug_aranges. out_debug_aranges uses frag_align to make sure the addresses start out aligned. Using frag_align will call frag_var[_init], which will end up calling TC_FRAG_INIT. On arm and aarch64 TC_FRAG_INIT will generate a $d mapping symbol for the .debug_aranges to show that at that point a sequence of data items starts. Such a symbol pointing into a non-allocated debug section will confuse eu-strip -g. And it seems inefficient and wrong in general to have additional mapping symbols for debug sections, which won't contain actual code in the first place. Just keep track of the aranges header size and use plain padding to align the addresses which avoids generating any mapping symbols on aarch64 and arm. Includes a testcase for aarch64 that PASS with this patch and shows the extra $d mapping symbol in .debug_aranges before. gas/ChangeLog * dwarf2dbg.c (out_header): Document EXPR->X_add_number value, out_debug_aranges depends on it. (out_debug_aranges): Track size of header to properly pad header for address alignment. gas/testsuite/ChangeLog * gas/aarch64/dwarf.d: New. * gas/aarch64/dwarf.s: New.
2015-06-13 21:47:41 +00:00
2015-06-13 Mark Wielaard <mjw@redhat.com>
* gas/aarch64/dwarf.d: New.
* gas/aarch64/dwarf.s: New.
[ARM] Commit approaved testcases missed in previous commit 2015-06-03 Matthew Wahab <matthew.wahab@arm.com> * gas/arm/armv8-a+rdma.d: New. * gas/arm/armv8-a+rdma.s: New.
2015-06-03 09:52:34 +00:00
2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
* gas/arm/armv8-a+rdma.d: New.
* gas/arm/armv8-a+rdma.s: New.
[AArch64] Support for ARMv8.1a Adv.SIMD instructions 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> gas/ * config/tc-aarch64.c (aarch64_features): Add "rdma". * doc/c-aarch64.texi (AArch64 Extensions): Add "rdma". gas/testsuite/ * rdma-directive.d: New. * rdma.d: New. * rdma.s: New. include/opcode/ * aarch64.h (AARCH64_FEATURE_RDMA): New. opcode/ * aarch64-tbl.h (aarch64_feature_rdma): New. (RDMA): New. (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate.
2015-06-02 11:20:00 +00:00
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
[ARM] Add support for ARMv8.1 PAN extension
2015-06-02 11:30:38 +00:00
* gas/arm/armv8-a+pan.d: New.
* gas/arm/armv8-a+pan.s: New.
[AArch64] Support for ARMv8.1a Adv.SIMD instructions 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> gas/ * config/tc-aarch64.c (aarch64_features): Add "rdma". * doc/c-aarch64.texi (AArch64 Extensions): Add "rdma". gas/testsuite/ * rdma-directive.d: New. * rdma.d: New. * rdma.s: New. include/opcode/ * aarch64.h (AARCH64_FEATURE_RDMA): New. opcode/ * aarch64-tbl.h (aarch64_feature_rdma): New. (RDMA): New. (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate.
2015-06-02 11:20:00 +00:00
[AArch64] Support for ARMv8.1a Limited Ordering Regions extension 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> include/ * aarch64.h (AARCH64_FEATURE_LOR): New. opcodes/ * aarch64-tbl.h (aarch64_feature_lor): New. (LOR): New. (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr", "stllrb", "stllrh". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ * config/tc-aarch64.c (aarch64_features): Add "lor". * doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of architecture extensions. gas/testsuite/ * lor-directive.d: New. * lor.d: New. * lor.s: New.
2015-06-02 10:29:15 +00:00
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
[ARM] Add support for ARMv8.1 PAN extension
2015-06-02 11:30:38 +00:00
* gas/aarch64/rdma-directive.d: New.
* gas/aarch64/rdma.d: New.
* gas/aarch64/rdma.s: New.
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/lor-directive.d: New.
* gas/aarch64/lor.d: New.
* gas/aarch64/lor.s: New
[AArch64] Support for ARMv8.1a Limited Ordering Regions extension 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> include/ * aarch64.h (AARCH64_FEATURE_LOR): New. opcodes/ * aarch64-tbl.h (aarch64_feature_lor): New. (LOR): New. (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr", "stllrb", "stllrh". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ * config/tc-aarch64.c (aarch64_features): Add "lor". * doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of architecture extensions. gas/testsuite/ * lor-directive.d: New. * lor.d: New. * lor.s: New.
2015-06-02 10:29:15 +00:00
[AArch64][GAS] Add support for PAN architecture extension 2015-06-01 Matthew Wahab <matthew.wahab@arm.com> gas/ * config/tc-aarch64.c (parse_sys_reg): New parameter. Check target support. Fix whitespace. (parse_operands): Update for parse_sys_reg changes. (aarch64_features): Add "pan". * doc/c-aarch64.texi (Aarch64 Extensions): Add "pan". gas/testsuite/ * pan-directive.d: New. * pan.d: New. * pan.s: New
2015-06-01 15:05:58 +00:00
2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
[ARM] Add support for ARMv8.1 PAN extension
2015-06-02 11:30:38 +00:00
* gas/aarch64/pan-directive.d: New.
* gas/aarch64/pan.d: New.
* gas/aarch64/pan.s: New
[AArch64][GAS] Add support for PAN architecture extension 2015-06-01 Matthew Wahab <matthew.wahab@arm.com> gas/ * config/tc-aarch64.c (parse_sys_reg): New parameter. Check target support. Fix whitespace. (parse_operands): Update for parse_sys_reg changes. (aarch64_features): Add "pan". * doc/c-aarch64.texi (Aarch64 Extensions): Add "pan". gas/testsuite/ * pan-directive.d: New. * pan.d: New. * pan.s: New
2015-06-01 15:05:58 +00:00
[AArch64] GAS support BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 This patch add BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 support in Gas. The relocation modifier === :gotpage_lo14:symbol 2015-06-01 Jiong.Wang <jiong.wang@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14): New entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers. (md_apply_fix): Support BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14. (aarch64_force_relocation): Ditto. gas/testsuite/ * gas/aarch64/ilp32-basic.s: New testcase. * gas/aarch64/ilp32-basic.d: Ditto.
2015-06-01 14:41:54 +00:00
2015-06-01 Jiong Wang <jiong.wang@arm.com>
* gas/aarch64/ilp32-basic.s: New testcase.
* gas/aarch64/ilp32-basic.d: Ditto.
[AArch64] GAS Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15 2015-06-01 Jiong.Wang <jiong.wang@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15): New entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers. (md_apply_fix): Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15. (aarch64_force_relocation): Ditto. gas/testsuite/ * gas/aarch64/reloc-insn.s: New testcase. * gas/aarch64/reloc-insn.d: Ditto.
2015-06-01 09:22:15 +00:00
2015-06-01 Jiong Wang <jiong.wang@arm.com>
* gas/aarch64/reloc-insn.s: New testcase.
* gas/aarch64/reloc-insn.d: Ditto.
x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand order As pointed out before, the documentation mandates the rounding mode to follow the GPR, so disassembler should produce output accordingly. gas/testsuite/ 2015-06-01 Jan Beulich <jbeulich@suse.com> * gas/i386/avx512f.s: Adjust operand order for Intel syntax vcvt{,u}si2ss. * gas/i386/x86-64-avx512f.s: Adjust operand order for Intel syntax vcvt{,u}si2s{d,s}. opcodes/ 2015-06-01 Jan Beulich <jbeulich@suse.com> * i386-dis.c (print_insn): Swap rounding mode specifier and general purpose register in Intel mode.
2015-06-01 07:51:28 +00:00
2015-06-01 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512f.s: Adjust operand order for Intel syntax
vcvt{,u}si2ss.
* gas/i386/x86-64-avx512f.s: Adjust operand order for Intel
syntax vcvt{,u}si2s{d,s}.
x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s} As pointed out before, the documentation mandates the rounding mode to follow the GPR, so gas should accept such input. As the brojen code got released already we sadly will need to continue to also accept the badly ordered operands. gas/testsuite/ 2015-06-01 Jan Beulich <jbeulich@suse.com> * gas/i386/avx512f-intel.d: Adjust expectations on operand order. * gas/i386/evex-lig256-intel.d: Likewise. * gas/i386/evex-lig512-intel.d: Likewise. * gas/i386/x86-64-avx512f-intel.d: Likewise. * gas/i386/x86-64-evex-lig256-intel.d: Likewise. * gas/i386/x86-64-evex-lig512-intel.d: Likewise. opcodes/ 2015-06-01 Jan Beulich <jbeulich@suse.com> * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. * i386-tbl.h: Regenerate.
2015-06-01 07:50:00 +00:00
2015-06-01 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512f-intel.d: Adjust expectations on operand order.
* gas/i386/evex-lig256-intel.d: Likewise.
* gas/i386/evex-lig512-intel.d: Likewise.
* gas/i386/x86-64-avx512f-intel.d: Likewise.
* gas/i386/x86-64-evex-lig256-intel.d: Likewise.
* gas/i386/x86-64-evex-lig512-intel.d: Likewise.
Compact EH Support The specification for the Compact EH format is available at: https://github.com/MentorEmbedded/cxx-abi/blob/master/MIPSCompactEH.pdf 2015-05-28 Catherine Moore <clm@codesourcery.com> Bernd Schmidt <bernds@codesourcery.com> Paul Brook <paul@codesourcery.com> bfd/ * bfd-in2.h: Regenerated. * elf-bfd.h (DWARF2_EH_HDR, COMPACT_EH_HDR): Define. (COMPACT_EH_CANT_UNWIND_OPCODE): Define. (dwarf_eh_frame_hdr_info): Move dwarf-specific fields from eh_frame_hdr_info. (compact_eh_frame_hdr_info): Declare. (eh_frame_hdr_info): Redeclare with union for dwarf-specific fields and compact-eh fields. (elf_backend_data): Add cant_unwind_opcode and compact_eh_encoding. (bfd_elf_section_data): Add eh_frame_entry_field. (elf_section_eh_frame_entry): Define. (bfd_elf_parse_eh_frame_entries): Declare. (_bfd_elf_parse_eh_frame_entry): Declare. (_bfd_elf_end_eh_frame_parsing): Declare. (_bfd_elf_write_section_eh_frame_entry): Declare. (_bfd_elf_eh_frame_entry_present): Declare. (_bfd_elf_section_for_symbol): Declare. * elf-eh-frame.c (bfd_elf_discard_eh_frame_entry): New function. (bfd_elf_record_eh_frame_entry): New function. (_bfd_elf_parse_eh_frame_entry): New function. (_bfd_elf_parse_eh_frame): Update hdr_info field references. (cmp_eh_frame_hdr): New function. (add_eh_frame_hdr_terminator): New function. (_bfd_elf_end_eh_frame_parsing): New function. (find_merged_cie): Update hdr_info field references. (_bfd_elf_discard_section_eh_frame): Likewise. (_bfd_elf_discard_section_eh_frame_hdr): Add Compact EH support. (_bfd_elf_eh_frame_entry_present): New function. (_bfd_elf_maybe_strip_eh_frame_hdr): Add Compact EH support. (_bfd_elf_write_section_eh_frame_entry): New function. (_bfd_elf_write_section_eh_frame): Update hdr_info field references. (_bfd_elf_fixup_eh_frame_hdr): New function. (write_compact_eh_frame_hdr): New function. (write_dwarf_eh_frame_hdr): New function. (_bfd_elf_write_section_eh_frame_hdr): Add Compact EH support. * elflink.c (_bfd_elf_section_for_symbol): New function. (elf_section_ignore_discarded_relocs): Add Compact EH support. (elf_link_input_bfd): Likewise. (bfd_elf_final_link): Likewise. (_bfd_elf_gc_mark): Likewise. (bfd_elf_parse_eh_frame_entries): New function. (bfd_elf_gc_sections): Add Compact EH support. (bfd_elf_discard_info): Likewise. * elfxx-mips.c: Include dwarf2.h. (_bfd_mips_elf_compact_eh_encoding): New function. (_bfd_mips_elf_cant_unwind_opcode): New function. * elfxx-mips.h (_bfd_mips_elf_compact_eh_encoding): Declare. (_bfd_mips_elf_cant_unwind_opcode): Declare. (elf_backend_compact_eh_encoding): Define. (elf_backend_cant_unwind_opcode): Define. * elfxx-target.h (elf_backend_compact_eh_encoding): Provide default. (elf_backend_cant_unwind_opcode): Provide default. (elf_backend_data elfNN_bed): Add elf_backend_compact_eh_encoding and elf_backend_cant_unwind_opcode. * section.c (SEC_INFO_TYPE_EH_FRAME_ENTRY): Add definition. gas/ * config/tc-alpha.c (all_cfi_sections): Declare. (s_alpha_ent): Initialize all_cfi_sections. (alpha_elf_md_end): Invoke cfi_set_sections. * config/tc-mips.c (md_apply_fix): Handle BFD_RELOC_NONE. (s_ehword): Use BFD_RELOC_32_PCREL. (mips_fix_adjustable): Handle BFD_RELOC_32_PCREL. (mips_cfi_reloc_for_encoding): New function. * tc-mips.h (DWARF2_FDE_RELOC_SIZE): Redefine. (DWARF2_FDE_RELOC_ENCODING): Define. (tc_cfi_reloc_for_encoding): Define. (mips_cfi_reloc_for_encoding): Define. (tc_compact_eh_opcode_stop): Define. (tc_compact_eh_opcode_pad): Define. * doc/as.texinfo: Document Compact EH extensions. * doc/internals.texi: Likewise. * dw2gencfi.c (EH_FRAME_LINKONCE): Redefine. (tc_cfi_reloc_for_encoding): Provide default. (compact_eh): Declare. (emit_expr_encoded): New function. (get_debugseg_name): Add Compact EH support. (alloc_debugseg_item): Likewise. (cfi_set_sections): New function. (dot_cfi_fde_data): New function. (dot_cfi_personality_id): New function. (dot_cfi_inline_lsda): New function. (cfi_pseudo_table): Add cfi_fde_data, cfi_personality_id, and cfi_inline_lsda. (dot_cfi_personality): Add Compact EH support. (dot_cfi_lsda): Likewise. (dot_cfi_sections): Likewise. (dot_cfi_startproc): Likewise. (get_cfi_seg): Likewise. (output_compact_unwind_data): New function. (output_cfi_insn): Add Compact EH support. (output_cie): Likewise. (output_fde): Likewise. (cfi_finish): Likewise. (cfi_emit_eh_header): New function. (output_eh_header): New function. * dw2gencfi.h (cfi_set_sections): Declare. (SUPPORT_COMPACT_EH): Define. (MULTIPLE_FRAME_SECTIONS): Define. New enumeration to describe the Compact EH header format. (fde_entry): Add new fields personality_id, eh_header_type, eh_data_size, eh_data, eh_loc and sections. (CFI_EMIT_eh_frame, CFI_EMIT_debug_frame, CFI_EMIT_target, CFI_EMIT_eh_frame_compact): Define. 2015-05-22 Catherine Moore <clm@codesourcery.com> Bernd Schmidt <bernds@codesourcery.com> gas/testsuite/ * gas/mips/mips.exp: Run new tests. * gas/mips/compact-eh-1.s: New file. * gas/mips/compact-eh-2.s: New file. * gas/mips/compact-eh-3.s: New file. * gas/mips/compact-eh-4.s: New file. * gas/mips/compact-eh-5.s: New file. * gas/mips/compact-eh-6.s: New file. * gas/mips/compact-eh-7.s: New file. * gas/mips/compact-eh-eb-1.d: New file. * gas/mips/compact-eh-eb-2.d: New file. * gas/mips/compact-eh-eb-3.d: New file. * gas/mips/compact-eh-eb-4.d: New file. * gas/mips/compact-eh-eb-5.d: New file. * gas/mips/compact-eh-eb-6.d: New file. * gas/mips/compact-eh-eb-7.d: New file. * gas/mips/compact-eh-el-1.d: New file. * gas/mips/compact-eh-el-2.d: New file. * gas/mips/compact-eh-el-3.d: New file. * gas/mips/compact-eh-el-4.d: New file. * gas/mips/compact-eh-el-5.d: New file. * gas/mips/compact-eh-el-6.d: New file. * gas/mips/compact-eh-el-7.d: New file. * gas/mips/compact-eh-err1.l: New file. * gas/mips/compact-eh-err1.s: New file. * gas/mips/compact-eh-err2.l: New file. * gas/mips/compact-eh-err2.s: New file. 2015-05-22 Catherine Moore <clm@codesourcery.com> include/ * bfdlink.h: Rename eh_frame_hdr to eh_frame_hdr_type. 2015-05-22 Catherine Moore <clm@codesourcery.com> Paul Brook <paul@codesourcery.com> ld/ * emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Add Compact EH support. * scripttempl/elf.sc: Handle .eh_frame_entry and .gnu_extab sections. 2015-05-22 Catherine Moore <clm@codesourcery.com> ld/testsuite/ * ld-mips-elf/compact-eh.ld: New linker script. * ld-mips-elf/compact-eh1.d: New. * ld-mips-elf/compact-eh1.s: New. * ld-mips-elf/compact-eh1a.s: New. * ld-mips-elf/compact-eh1b.s: New. * ld-mips-elf/compact-eh2.d: New. * ld-mips-elf/compact-eh2.s: New. * ld-mips-elf/compact-eh3.d: New. * ld-mips-elf/compact-eh3.s: New. * ld-mips-elf/compact-eh3a.s: New. * ld-mips-elf/compact-eh4.d: New. * ld-mips-elf/compact-eh5.d: New. * ld-mips-elf/compact-eh6.d: New. * ld-mips-elf/mips-elf.exp: Run new tests.
2015-05-28 21:50:36 +00:00
2015-05-28 Catherine Moore <clm@codesourcery.com>
Bernd Schmidt <bernds@codesourcery.com>
gas/testsuite/
* gas/mips/mips.exp: Run new tests.
* gas/mips/compact-eh-1.s: New file.
* gas/mips/compact-eh-2.s: New file.
* gas/mips/compact-eh-3.s: New file.
* gas/mips/compact-eh-4.s: New file.
* gas/mips/compact-eh-5.s: New file.
* gas/mips/compact-eh-6.s: New file.
* gas/mips/compact-eh-7.s: New file.
* gas/mips/compact-eh-eb-1.d: New file.
* gas/mips/compact-eh-eb-2.d: New file.
* gas/mips/compact-eh-eb-3.d: New file.
* gas/mips/compact-eh-eb-4.d: New file.
* gas/mips/compact-eh-eb-5.d: New file.
* gas/mips/compact-eh-eb-6.d: New file.
* gas/mips/compact-eh-eb-7.d: New file.
* gas/mips/compact-eh-el-1.d: New file.
* gas/mips/compact-eh-el-2.d: New file.
* gas/mips/compact-eh-el-3.d: New file.
* gas/mips/compact-eh-el-4.d: New file.
* gas/mips/compact-eh-el-5.d: New file.
* gas/mips/compact-eh-el-6.d: New file.
* gas/mips/compact-eh-el-7.d: New file.
* gas/mips/compact-eh-err1.l: New file.
* gas/mips/compact-eh-err1.s: New file.
* gas/mips/compact-eh-err2.l: New file.
* gas/mips/compact-eh-err2.s: New file.
Support AMD64/Intel ISAs in assembler/disassembler AMD64 spec and Intel64 spec differ in direct unconditional branches in 64-bit mode. AMD64 supports direct unconditional branches with 16-bit offset via the data size prefix, which truncates RIP to 16 bits, while the data size prefix is ignored by Intel64. This patch adds -mamd64/-mintel64 option to x86-64 assembler and -Mamd64/-Mintel64 option to x86-64 disassembler. The most permissive ISA, which is AMD64, is the default. GDB can add an option, similar to (gdb) help set disassembly-flavor Set the disassembly flavor. The valid values are "att" and "intel", and the default value is "att". to select which ISA to disassemble. binutils/ PR binutis/18386 * doc/binutils.texi: Document -Mamd64 and -Mintel64. gas/ PR binutis/18386 * config/tc-i386.c (OPTION_MAMD64): New. (OPTION_MINTEL64): Likewise. (md_longopts): Add -mamd64 and -mintel64. (md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64. (md_show_usage): Add -mamd64 and -mintel64. * doc/c-i386.texi: Document -mamd64 and -mintel64. gas/testsuite/ PR binutis/18386 * gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3. * gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump. * gas/i386/ilp32/x86-64-branch.d: Likewise. * gas/i386/x86-64-branch-2.d: New file. * gas/i386/x86-64-branch-2.s: Likewise. * gas/i386/x86-64-branch-3.l: Likewise. * gas/i386/x86-64-branch-3.s: Likewise. ld/testsuite/ PR binutis/18386 * ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump. * ld-x86-64/tlspic.dd: Likewise. * ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to objdump for tlspic.dd and tlsgdesc.dd. opcodes/ PR binutis/18386 * i386-dis.c: Add comments for '@'. (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9. (enum x86_64_isa): New. (isa64): Likewise. (print_i386_disassembler_options): Add amd64 and intel64. (print_insn): Handle amd64 and intel64. (putop): Handle '@'. (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit. * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64. * i386-opc.h (AMD64): New. (CpuIntel64): Likewise. (i386_cpu_flags): Add cpuamd64 and cpuintel64. * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64. Mark direct call/jmp without Disp16|Disp32 as Intel64. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2015-05-15 16:47:39 +00:00
2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
PR binutis/18386
* gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3.
* gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump.
* gas/i386/ilp32/x86-64-branch.d: Likewise.
* gas/i386/x86-64-branch-2.d: New file.
* gas/i386/x86-64-branch-2.s: Likewise.
* gas/i386/x86-64-branch-3.l: Likewise.
* gas/i386/x86-64-branch-3.s: Likewise.
Add -mshared option to x86 ELF assembler This patch adds -mshared option to x86 ELF assembler. By default, assembler will optimize out non-PLT relocations against defined non-weak global branch targets with default visibility. The -mshared option tells the assembler to generate code which may go into a shared library where all non-weak global branch targets with default visibility can be preempted. The resulting code is slightly bigger. This option only affects the handling of branch instructions. This Linux kernel patch is needed to create a working x86 Linux kernel if it hasn't been applied: diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index ae6588b..b91a00c 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -339,8 +339,8 @@ early_idt_handlers: i = i + 1 .endr -/* This is global to keep gas from relaxing the jumps */ -ENTRY(early_idt_handler) +/* This is weak to keep gas from relaxing the jumps */ +WEAK(early_idt_handler) cld cmpl $2,(%rsp) # X86_TRAP_NMI -- gas/ * config/tc-i386.c (shared): New. (OPTION_MSHARED): Likewise. (elf_symbol_resolved_in_segment_p): Add relocation argument. Check PLT relocations and shared. (md_estimate_size_before_relax): Pass fragP->fr_var to elf_symbol_resolved_in_segment_p. (md_longopts): Add -mshared. (md_show_usage): Likewise. (md_parse_option): Handle OPTION_MSHARED. * doc/c-i386.texi: Document -mshared. gas/testsuite/ * gas/i386/i386.exp: Don't run pcrel for ELF targets. Run pcrel-elf, relax-4 and x86-64-relax-3 for ELF targets. * gas/i386/pcrel-elf.d: New file. * gas/i386/relax-4.d: Likewise. * gas/i386/x86-64-relax-3.d: Likewise. * gas/i386/relax-3.d: Pass -mshared to assembler. Updated. * gas/i386/x86-64-relax-2.d: Likewise. * gas/i386/relax-3.s: Add test for PLT relocation.
2015-05-15 10:17:31 +00:00
2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Don't run pcrel for ELF targets. Run
pcrel-elf, relax-4 and x86-64-relax-3 for ELF targets.
* gas/i386/pcrel-elf.d: New file.
* gas/i386/relax-4.d: Likewise.
* gas/i386/x86-64-relax-3.d: Likewise.
* gas/i386/relax-3.d: Pass -mshared to assembler. Updated.
* gas/i386/x86-64-relax-2.d: Likewise.
* gas/i386/relax-3.s: Add test for PLT relocation.
Fix some PPC assembler errors. Remove the wait instructions for server processors, since they were never implemented. Also add the extra operands added to the tlbie and slbia instructions with ISA 2.06 and ISA 2.05 respectively. binutils/ * MAINTAINERS: Add myself as PPC maintainer. opcodes/ * ppc-opc.c (IH) New define. (powerpc_opcodes) <wait>: Do not enable for POWER7. <tlbie>: Add RS operand for POWER7. <slbia>: Add IH operand for POWER6. gas/testsuite/ * gas/ppc/power4.d: Add a slbia test. * gas/ppc/power4.s: Likewise. * gas/ppc/power6.d: Add slbia and tlbie tests. * gas/ppc/power6.s: Likewise. * gas/ppc/power7.d: Remove wait tests. Add a tlbie test. * gas/ppc/power7.s: Likewise.
2015-05-15 01:57:50 +00:00
2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
* gas/ppc/power4.d: Add a slbia test.
* gas/ppc/power4.s: Likewise.
* gas/ppc/power6.d: Add slbia and tlbie tests.
* gas/ppc/power6.s: Likewise.
* gas/ppc/power7.d: Remove wait tests. Add a tlbie test.
* gas/ppc/power7.s: Likewise.
xtensa: fix gas trampolines regression Extra condition 'abs (addr - trampaddr) < J_RANGE / 2' for trampoline selection results in regressions: when relaxable jump is little longer than J_RANGE so that single trampoline makes two new jumps, one longer than J_RANGE / 2 and one shorter, correct trampoline cannot be found. Drop that condition. 2015-05-13 Max Filippov <jcmvbkbc@gmail.com> gas/ * config/tc-xtensa.c (xtensa_relax_frag): Allow trampoline to be closer than J_RANGE / 2 to jump frag. gas/testsuite/ * gas/xtensa/trampoline.s: Add regression testcase.
2015-05-09 22:02:31 +00:00
2015-05-13 Max Filippov <jcmvbkbc@gmail.com>
* gas/xtensa/trampoline.s: Add regression testcase.
Add Intel MCU support to gas -march=iamcu must be passed to i386 assembler to generate Intel MCU object file. gas/ * config/tc-i386.c (cpu_arch): Add iamcu. (i386_align_code): Handle PROCESSOR_IAMCU. (i386_arch): Likewise. (i386_mach): Likewise. (i386_target_format): Likewise. (valid_iamcu_cpu_flags): New function. (check_cpu_arch_compatible): Only allow Intel MCU instructions when targeting Intel MCU. (set_cpu_arch): Call valid_iamcu_cpu_flags to check if CPU flags are valid for Intel MCU. (md_parse_option): Likewise. * tc-i386.h (ELF_TARGET_IAMCU_FORMAT): New. (processor_type): Add PROCESSOR_IAMCU. * doc/c-i386.texi: Document iamcu. gas/testsuite/ * gas/i386/i386.exp: Run iamcu-1, iamcu-2, iamcu-3, iamcu-inval-1, iamcu-inval-2 and iamcu-inval-3. * gas/i386/iamcu-1.d: New file. * gas/i386/iamcu-1.s: Likewise. * gas/i386/iamcu-2.d: Likewise. * gas/i386/iamcu-2.s: Likewise. * gas/i386/iamcu-3.d: Likewise. * gas/i386/iamcu-3.s: Likewise. * gas/i386/iamcu-inval-1.l: Likewise. * gas/i386/iamcu-inval-1.s: Likewise. * gas/i386/iamcu-inval-2.l: Likewise. * gas/i386/iamcu-inval-2.s: Likewise. * gas/i386/iamcu-inval-3.l: Likewise. * gas/i386/iamcu-inval-3.s: Likewise.
2015-05-11 18:11:19 +00:00
2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run iamcu-1, iamcu-2, iamcu-3, iamcu-inval-1,
iamcu-inval-2 and iamcu-inval-3.
* gas/i386/iamcu-1.d: New file.
* gas/i386/iamcu-1.s: Likewise.
* gas/i386/iamcu-2.d: Likewise.
* gas/i386/iamcu-2.s: Likewise.
* gas/i386/iamcu-3.d: Likewise.
* gas/i386/iamcu-3.s: Likewise.
* gas/i386/iamcu-inval-1.l: Likewise.
* gas/i386/iamcu-inval-1.s: Likewise.
* gas/i386/iamcu-inval-2.l: Likewise.
* gas/i386/iamcu-inval-2.s: Likewise.
* gas/i386/iamcu-inval-3.l: Likewise.
* gas/i386/iamcu-inval-3.s: Likewise.
Add missing ChangeLog entries for PR binutis/18386
2015-05-13 11:33:45 +00:00
2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
PR binutis/18386
* gas/i386/i386.exp: Run x86-64-jump.
* gas/i386/x86-64-branch.d: Updated.
* gas/i386/ilp32/x86-64-branch.d: Likewise.
* gas/i386/x86-64-branch.s: Add tests for the operand size prefix
with call, jmp and jb.
* gas/i386/x86-64-jump.d: New file.
* gas/i386/x86-64-jump.s: Likewise.
Change ARM symbol name verification code so that it only triggers when the form "name = val" is used. PR gas/18347 * config/tc-arm.h (TC_EQUAL_IN_INSN): Define. * config/tc-arm.c (arm_tc_equal_in_insn): New function. Move the symbol name checking code to here from... (md_undefined_symbo): ... here.
2015-05-08 16:28:26 +00:00
2015-05-08 Nick Clifton <nickc@redhat.com>
PR gas/18347
* gas/arm/pr18347.s: Add tests of other symbol assignments which
should not generate the warning.
* gas/arm/pr18347.l: Update expected output.
Optimize branches to non-weak symbols with visibility Branches to global non-weak symbols defined in the same segment with non-default visibility can be optimized the same way as branches to local symbols. gas/ * config/tc-i386.c (elf_symbol_resolved_in_segment_p): New. (md_estimate_size_before_relax): Use it. gas/testsuite/ * gas/i386/i386.exp: Run relax-3 and x86-64-relax-2. * gas/i386/relax-3.d: New file. * gas/i386/relax-3.s: Likewise. * gas/i386/x86-64-relax-2.d: Likewise.
2015-05-07 16:13:39 +00:00
2015-05-07 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run relax-3 and x86-64-relax-2.
* gas/i386/relax-3.d: New file.
* gas/i386/relax-3.s: Likewise.
* gas/i386/x86-64-relax-2.d: Likewise.
gas: added tests for the sparc natural instructions. gas/ChangeLog: 2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com> * gas/sparc/natural-32.d: Test ldn, ldna, stn, stna, slln, srln, sran, casn, casna and clrn. * gas/sparc/natural-32.s: Likewise. * gas/sparc/natural.s: Likewise. * gas/sparc/natural.d: Likewise.
2015-05-01 17:14:11 +00:00
2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
* gas/sparc/natural-32.d: Test ldn, ldna, stn, stna, slln, srln,
sran, casn, casna and clrn.
* gas/sparc/natural-32.s: Likewise.
* gas/sparc/natural.s: Likewise.
* gas/sparc/natural.d: Likewise.
gas: support for the sparc %ncc condition codes register. gas/ChangeLog: 2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_ip): Support the %ncc "natural" condition codes * doc/c-sparc.texi (Sparc-Regs): Document %ncc. gas/testsuite/ChangeLog: 2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com> * gas/sparc/natural.s: New file. * gas/sparc/natural-32.s: Likewise. * gas/sparc/natural.d: Likewise. * gas/sparc/natural-32.d: Likewise. * gas/sparc/sparc.exp (sparc_elf_setup): Run the tests natural and natural-32.
2015-05-01 00:17:20 +00:00
2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
* gas/sparc/natural.s: New file.
* gas/sparc/natural-32.s: Likewise.
* gas/sparc/natural.d: Likewise.
* gas/sparc/natural-32.d: Likewise.
* gas/sparc/sparc.exp (sparc_elf_setup): Run the tests natural and
natural-32.
[AArch64] Record instruction alignment for .inst directive 2015-05-06 Renlin Li <renlin.li@arm.com> gas/ * config/tc-aarch64.c (mapping_state): Recording alignment before exit. gas/testsuite/ * gas/aarch64/codealign_1.s: New. * gas/aarch64/codealign_1.d: New.
2015-05-06 11:18:19 +00:00
2015-05-06 Renlin Li <renlin.li@arm.com>
* gas/aarch64/codealign_1.s: New.
* gas/aarch64/codealign_1.d: New.
[AARCH64] Positively emit symbols for alignment 2015-05-05 Renlin Li <renlin.li@arm.com> gas/ * config/tc-aarch64.c (aarch64_init_frag): Always generate mapping symbols. gas/testsuite/ * gas/aarch64/mapping_5.d: New. * gas/aarch64/mapping_5.s: New. * gas/aarch64/mapping_6.d: New. * gas/aarch64/mapping_6.s: New.
2015-05-05 16:48:18 +00:00
2015-05-05 Renlin Li <renlin.li@arm.com>
* gas/aarch64/mapping_5.d: New.
* gas/aarch64/mapping_5.s: New.
* gas/aarch64/mapping_6.d: New.
* gas/aarch64/mapping_6.s: New.
Remove i386_elf_emit_arch_note This x86 assembler patch: https://sourceware.org/ml/binutils/2001-11/msg00344.html generates a .note section for .arch directive so that GDB can tell which architecture an i386 binary belongs: https://sourceware.org/ml/binutils/2001-11/msg00271.html However, x86 assembly code can have any instructions. A .note section doesn't help. This patch removes it. gas/ * config/tc-i386.c (i386_elf_emit_arch_note): Removed. * config/tc-i386.h (md_end): Likewise. (i386_elf_emit_arch_note): Likewise. gas/testsuite/ * gas/i386/i386.exp: Run note. * gas/i386/note.d: New file. * gas/i386/note.s: Likewise.
2015-05-01 15:29:16 +00:00
2015-05-01 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run note.
* gas/i386/note.d: New file.
* gas/i386/note.s: Likewise.
GAS ARM: Warn if the user creates a symbol with the same name as an instruction. PR gas/18347 gas * config/tc-arm.c (md_undefined_symbol): Issue a warning message (if enabled) when the user creates a symbol with the same name as an ARM instruction. (flag_warn_syms): New static variable. (arm_opts): Add mwarn-syms and mno-warn-syms. * doc/c-arm.texi (ARM Options): Document the -m[no-]warn-syms options. tests * gas/arm/pr18347.s: New file: Test case. * gas/arm/pr18347.l: New file: Expected assembler output. * gas/arm/pr18347.d: New file: Test driver.
2015-04-30 10:17:55 +00:00
2015-04-30 Nick Clifton <nickc@redhat.com>
PR gas/18347
* gas/arm/pr18347.s: New file: Test case.
* gas/arm/pr18347.l: New file: Expected assembler output.
* gas/arm/pr18347.d: New file: Test driver.
Fix an internal error in GAS when assembling a bogus piece of source code. gas PR 18256 * config/tc-arm.c (encode_arm_cp_address): Issue an error message if the operand is neither a register nor a vector. tests * gas/arm/pr18256.s: New file: Test case. * gas/arm/pr18256.l: New file: Expected assembler output. * gas/arm/pr18256.d: New file: Test driver.
2015-04-29 16:09:05 +00:00
2015-04-29 Nick Clifton <nickc@redhat.com>
PR gas/18265
* gas/arm/pr18256.s: New file: Test case.
* gas/arm/pr18256.l: New file: Expected assembler output.
* gas/arm/pr18256.d: New file: Test driver.
[ARM]Positively emit symbols for alignment 2015-04-28 Renlin Li <renlin.li@arm.com> gas/ * config/tc-arm.c (arm_init_frag): Always emit mapping symbols. gas/testsuite/ * gas/arm/thumb2_vpool_be.d: Adjust the desired output. * gas/arm/vldconst_be.d: Ditto.
2015-04-28 16:10:26 +00:00
2015-04-28 Renlin Li <renlin.li@arm.com>
* gas/arm/thumb2_vpool_be.d: Adjust the desired output.
* gas/arm/vldconst_be.d: Ditto.
opcodes/ * ppc-opc.c (DCBT_EO): New define. (powerpc_opcodes) <lbarx>: Enable for POWER8 and later. <lharx>: Likewise. <stbcx.>: Likewise. <sthcx.>: Likewise. <waitrsv>: Do not enable for POWER7 and later. <waitimpl>: Likewise. <dcbt>: Default to the two operand form of the instruction for all "old" cpus. For "new" cpus, use the operand ordering that matches whether the cpu is server or embedded. <dcbtst>: Likewise. gas/testsuite/ * gas/ppc/a2.s: Fixup test case due to dcbt/dcbtst embedded operand ordering change. * gas/ppc/a2.d: Likewise. * gas/ppc/476.d: Likewise. * gas/ppc/booke.s: Remove invalid 3 operand dcbt tests. * gas/ppc/booke.d: Likewise. * gas/ppc/power7.s: Remove lbarx, lharx, stbcx., sthcx., waitrsv and waitimpl tests. * gas/ppc/power7.d: Likewise.
2015-04-27 16:06:54 +00:00
2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
* gas/ppc/a2.s: Fixup test case due to dcbt/dcbtst embedded operand
ordering change.
* gas/ppc/a2.d: Likewise.
* gas/ppc/476.d: Likewise.
* gas/ppc/booke.s: Remove invalid 3 operand dcbt tests.
* gas/ppc/booke.d: Likewise.
* gas/ppc/power7.s: Remove lbarx, lharx, stbcx., sthcx., waitrsv
and waitimpl tests.
* gas/ppc/power7.d: Likewise.
S/390: z13 use GNU attribute to indicate vector ABI bfd/ * elf-s390-common.c (elf_s390_merge_obj_attributes): New function. * elf32-s390.c (elf32_s390_merge_private_bfd_data): Call elf_s390_merge_obj_attributes. * elf64-s390.c (elf64_s390_merge_private_bfd_data): New function. binutils/ * readelf.c (display_s390_gnu_attribute): New function. (process_s390_specific): New function. (process_arch_specific): Call process_s390_specific. gas/ * doc/as.texinfo: Document Tag_GNU_S390_ABI_Vector. include/elf/ * s390.h: Define Tag_GNU_S390_ABI_Vector.
2015-04-27 08:32:23 +00:00
2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* doc/as.texinfo: Document Tag_GNU_S390_ABI_Vector.
S/390: Fixes for z13 instructions. opcodes/ * s390-opc.c: New instruction type VV0UU2. * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK, and WFC. gas/testsuite/ * gas/s390/zarch-z13.d: Fix tests for VFCE, VLDE, VFSQ, WFK, and WFC. * gas/s390/zarch-z13.s: Likewise.
2015-04-27 08:29:16 +00:00
2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gas/s390/zarch-z13.d: Fix tests for VFCE, VLDE, VFSQ, WFK, and
WFC.
* gas/s390/zarch-z13.s: Likewise.
[ARM]: Don't tail-pad over-aligned functions to the alignment boundary. 2015-04/24 Richard Earnshaw <rearnsha@arm.com> gas/ * config/tc-arm.h (arm_min): New function. (SUB_SEGMENT_ALIGN): Define. gas/testsuite/ * gas/arm/align64.d: Delete trailing padding NOPs. ld/testsuite/ * ld-arm/armthumb-lib.d: Regenerate expected output. * ld-arm/armthumb-lib.d: Likewise. * ld-arm/armthumb-lib.sym: Likewise. * ld-arm/cortex-a8-fix-b-rel-arm.d: Likewise. * ld-arm/cortex-a8-fix-b-rel-thumb.d: Likewise. * ld-arm/cortex-a8-fix-b.d: Likewise. * ld-arm/cortex-a8-fix-bcc-rel-thumb.d: Likewise. * ld-arm/cortex-a8-fix-bcc.d: Likewise. * ld-arm/cortex-a8-fix-bl-rel-arm.d: Likewise. * ld-arm/cortex-a8-fix-bl-rel-plt.d: Likewise. * ld-arm/cortex-a8-fix-bl-rel-thumb.d: Likewise. * ld-arm/cortex-a8-fix-bl.d: Likewise. * ld-arm/cortex-a8-fix-blx-bcond.d: Likewise. * ld-arm/cortex-a8-fix-blx-rel-arm.d: Likewise. * ld-arm/cortex-a8-fix-blx-rel-thumb.d: Likewise. * ld-arm/cortex-a8-fix-blx.d: Likewise. * ld-arm/cortex-a8-fix-hdr.d: Likewise. * ld-arm/farcall-mixed-app-v5.d: Likewise. * ld-arm/farcall-mixed-app.d: Likewise. * ld-arm/farcall-mixed-lib-v4t.d: Likewise. * ld-arm/farcall-mixed-lib.d: Likewise. * ld-arm/mixed-app-v5.d: Likewise. * ld-arm/mixed-app.d: Likewise. * ld-arm/mixed-lib.d: Likewise.
2015-04-24 14:51:49 +00:00
2015-04-24 Richard Earnshaw <rearnsha@arm.com>
* gas/arm/align64.d: Delete trailing padding NOPs.
Improve warning messages for la/dla gas/ * config/tc-mips.c (macro): State the recommended way of creating 32-bit or 64-bit addresses. gas/testsuite/ * gas/mips/dla-warn.l: New file. * gas/mips/dla-warn.s: New file. * gas/mips/la-warn.l: New file. * gas/mips/la-warn.s: New file. * gas/mips/mips.exp: Run new tests.
2015-04-23 19:09:13 +00:00
2015-04-23 Matthew Fortune <matthew.fortune@imgtec.com>
* gas/mips/dla-warn.l: New file.
* gas/mips/dla-warn.s: New file.
* gas/mips/la-warn.l: New file.
* gas/mips/la-warn.s: New file.
* gas/mips/mips.exp: Run new tests.
Fix r6-branch-constraints test when run with n64 as default ABI gas/testsuite/ * gas/mips/mips.exp: Require o32 for r6-branch-constraints.
2015-04-23 19:10:50 +00:00
2015-04-23 Matthew Fortune <matthew.fortune@imgtec.com>
* gas/mips/mips.exp: Require o32 for r6-branch-constraints.
x86: disambiguate disassembly of certain AVX512 insns Certain conversion operations as well as vfpclassp{d,s} are ambiguous when the input operand is in memory and no broadcast is being used. While in Intel mode this gets resolved by printing suitable operand size modifiers, AT&T mode need mnemonic suffixes to be added. gas/testsuite/ 2015-04-23 Jan Beulich <jbeulich@suse.com> * gas/i386/avx512dq.d: Add 'z' suffix to vfpclassp{d,s} non- register, non-broadcast cases. * gas/i386/x86-64-avx512dq.d: Likewise. * gas/i386/avx512dq_vl.d: Add 'x' and 'y' suffixes to vcvt{,u}qq2ps and vfpclassp{d,s} non-register, non-broadcast cases. * gas/i386/x86-64-avx512dq_vl.d: Likewise. * gas/i386/avx512f_vl.d: Add 'x' and 'y' suffixes to vcvt{,t}pd2{,u}dq and vcvtpd2ps non-register, non-broadcast cases. * gas/i386/x86-64-avx512f_vl.d: Likewise. opcodes/ 2015-04-23 Jan Beulich <jbeulich@suse.com> * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ". * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq, vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY. (vfpclasspd, vfpclassps): Add %XZ.
2015-04-23 14:42:40 +00:00
2015-04-23 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512dq.d: Add 'z' suffix to vfpclassp{d,s} non-
register, non-broadcast cases.
* gas/i386/x86-64-avx512dq.d: Likewise.
* gas/i386/avx512dq_vl.d: Add 'x' and 'y' suffixes to
vcvt{,u}qq2ps and vfpclassp{d,s} non-register, non-broadcast
cases.
* gas/i386/x86-64-avx512dq_vl.d: Likewise.
* gas/i386/avx512f_vl.d: Add 'x' and 'y' suffixes to
vcvt{,t}pd2{,u}dq and vcvtpd2ps non-register, non-broadcast
cases.
* gas/i386/x86-64-avx512f_vl.d: Likewise.
x86: don't require operand size specification for AVX512 broadcasts Certain conversion operations as well as vfpclassp{d,s} are ambiguous when the input operand is in memory. That ambiguity, however, doesn't apply when using broadcasts (the destination operand size can be induced from the broadcast specifier). gas/ 2015-04-23 Jan Beulich <jbeulich@suse.com> * config/tc-i386.c (match_mem_size): Also allow no size specification when broadcasting. gas/testsuite/ 2015-04-23 Jan Beulich <jbeulich@suse.com> * gas/i386/avx512dq.s: Drop 'z' suffix from vfpclassp{d,s} in some AT&T and all Intel cases. * gas/i386/x86-64-avx512dq.s: Likewise. * gas/i386/avx512dq_vl.s: Drop 'x' and 'y' suffixes from vcvt{,u}qq2ps and vfpclassp{d,s} in some AT&T and all Intel cases. * gas/i386/x86-64-avx512dq_vl.s: Likewise. * gas/i386/avx512f_vl.s: Drop 'x' and 'y' suffixes from vcvt{,t}pd2{,u}dq and vcvtpd2ps in some AT&T and all Intel cases. * gas/i386/x86-64-avx512f_vl.s: Likewise.
2015-04-23 14:41:21 +00:00
2015-04-23 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512dq.s: Drop 'z' suffix from vfpclassp{d,s} in
some AT&T and all Intel cases.
* gas/i386/x86-64-avx512dq.s: Likewise.
* gas/i386/avx512dq_vl.s: Drop 'x' and 'y' suffixes from
vcvt{,u}qq2ps and vfpclassp{d,s} in some AT&T and all Intel
cases.
* gas/i386/x86-64-avx512dq_vl.s: Likewise.
* gas/i386/avx512f_vl.s: Drop 'x' and 'y' suffixes from
vcvt{,t}pd2{,u}dq and vcvtpd2ps in some AT&T and all Intel
cases.
* gas/i386/x86-64-avx512f_vl.s: Likewise.
Don't hardcode offset of .shstrtab section There is no requirement on placement of section name section, .shstrtab. This patch removes hardcoded offsets of .shstrtab sections. binutils/testsuite/ * binutils-all/i386/compressed-1b.d: Don't hardcode offset of .shstrtab section. * binutils-all/i386/compressed-1c.d: Likewise. * binutils-all/readelf.s-64: Likewise. * binutils-all/x86-64/compressed-1b.d: Likewise. * binutils-all/x86-64/compressed-1c.d: Likewise. gas/testsuite/ * gas/i386/ilp32/x86-64-unwind.d: Don't hardcode offset of .shstrtab section. * gas/i386/x86-64-unwind.d: Likewise. * gas/ia64/alias-ilp32.d: Likewise. * gas/ia64/alias.d: Likewise. * gas/ia64/group-1.d: Likewise. * gas/ia64/group-2.d: Likewise. * gas/ia64/secname-ilp32.d: Likewise. * gas/ia64/secname.d: Likewise. * gas/ia64/unwind-ilp32.d: Likewise. * gas/ia64/unwind.d: Likewise. * gas/mmix/bspec-1.d: Likewise. * gas/mmix/byte-1.d: Likewise. * gas/mmix/loc-1.d: Likewise. * gas/mmix/loc-2.d: Likewise. * gas/mmix/loc-3.d: Likewise. * gas/mmix/loc-4.d: Likewise. * gas/mmix/loc-5.d: Likewise. * gas/tic6x/scomm-directive-4.d: Likewise. ld/testsuite/ * ld-mmix/bspec1.d: Don't hardcode offset of .shstrtab section. * ld-mmix/bspec2.d: Likewise. * ld-mmix/local1.d: Likewise. * ld-mmix/local3.d: Likewise. * ld-mmix/local5.d: Likewise. * ld-mmix/local7.d: Likewise. * ld-mmix/undef-3.d: Likewise. * ld-sh/sh64/crangerel1.rd: Likewise. * ld-sh/sh64/crangerel2.rd: Likewise. * ld-tic6x/common.d: Likewise. * ld-tic6x/shlib-1.rd: Likewise. * ld-tic6x/shlib-1b.rd: Likewise. * ld-tic6x/shlib-1r.rd: Likewise. * ld-tic6x/shlib-1rb.rd: Likewise. * ld-tic6x/shlib-app-1.rd: Likewise. * ld-tic6x/shlib-app-1b.rd: Likewise. * ld-tic6x/shlib-app-1r.rd: Likewise. * ld-tic6x/shlib-app-1rb.rd: Likewise. * ld-tic6x/shlib-noindex.rd: Likewise. * ld-tic6x/static-app-1.rd: Likewise. * ld-tic6x/static-app-1b.rd: Likewise. * ld-tic6x/static-app-1r.rd: Likewise. * ld-tic6x/static-app-1rb.rd: Likewise. * ld-x86-64/ilp32-4.d: Likewise. * ld-x86-64/split-by-file-nacl.rd: Likewise. * ld-x86-64/split-by-file.rd: Likewise.
2015-04-20 16:55:34 +00:00
2015-04-20 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/ilp32/x86-64-unwind.d: Don't hardcode offset of
.shstrtab section.
* gas/i386/x86-64-unwind.d: Likewise.
* gas/ia64/alias-ilp32.d: Likewise.
* gas/ia64/alias.d: Likewise.
* gas/ia64/group-1.d: Likewise.
* gas/ia64/group-2.d: Likewise.
* gas/ia64/secname-ilp32.d: Likewise.
* gas/ia64/secname.d: Likewise.
* gas/ia64/unwind-ilp32.d: Likewise.
* gas/ia64/unwind.d: Likewise.
* gas/mmix/bspec-1.d: Likewise.
* gas/mmix/byte-1.d: Likewise.
* gas/mmix/loc-1.d: Likewise.
* gas/mmix/loc-2.d: Likewise.
* gas/mmix/loc-3.d: Likewise.
* gas/mmix/loc-4.d: Likewise.
* gas/mmix/loc-5.d: Likewise.
* gas/tic6x/scomm-directive-4.d: Likewise.
Handle invalid prefixes for rdrand and rdseed This patch puts rdrand and rdseed in prefix_table so that invalid prefixes for rdrand and rdseed are handled properly. gas/testsuite/ PR binutils/17898 * gas/i386/prefix.s: Add rdrand/rdseed prefix tests. * gas/i386/prefix.d: Updated. opcodes/ PR binutils/17898 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ... (PREFIX_MOD_0_0FC7_REG_6): This. (PREFIX_MOD_3_0FC7_REG_6): New. (PREFIX_MOD_3_0FC7_REG_7): Likewise. (prefix_table): Replace PREFIX_0FC7_REG_6 with PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and PREFIX_MOD_3_0FC7_REG_7. (mod_table): Replace PREFIX_0FC7_REG_6 with PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and PREFIX_MOD_3_0FC7_REG_7.
2015-04-15 16:53:13 +00:00
2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/17898
* gas/i386/prefix.s: Add rdrand/rdseed prefix tests.
* gas/i386/prefix.d: Updated.
[ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2 2015-04-15 Renlin Li <renlin.li@arm.com> opcodes/: * arm-dis.c (thumb32_opcodes): Define 'D' format control code, use it for ssat and ssat16. (print_insn_thumb32): Add handle case for 'D' control code. gas/testsuite/: * gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field. * gas/arm/thumb32.d: Likewise.
2015-04-15 16:44:03 +00:00
2015-04-15 Renlin Li <renlin.li@arm.com>
* gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field.
* gas/arm/thumb32.d: Likewise.
Adds support to the RL78 port for linker relaxation affecting .debug sections. gas * config/tc-rl78.h (TC_LINKRELAX_FIXUP): Define. (TC_FORCE_RELOCATION_SUB_SAME): Define. (DWARF2_USE_FIXED_ADVANCE_PC): Define. * gas/lns/lns.exp: Add RL78 to list of targets using DW_LNS_fixed_advance_pc. bfd * elf32-rl78.c (RL78_OP_REL): New macro. (rl78_elf_howto_table): Use it for complex relocs. (get_symbol_value): Handle the cases when the info or status arguments are NULL. (get_romstart): Cache the status returned by get_symbol_value. (get_ramstart): Likewise. (RL78_STACK_PUSH): Generate an error message if the stack overflows. (RL78_STACK_POP): Likewise for underflows. (rl78_compute_complex_reloc): New function. Contains the basic processing code for all RL78 complex relocs. (rl78_special_reloc): New function. Provides special reloc handling for complex relocs. (rl78_elf_relocate_section): Use rl78_compute_complex_reloc. (rl78_offset_for_reloc): Likewise. binutils* readelf.c (target_specific_reloc_handling): Add code to handle RL78 complex relocs.
2015-04-14 15:23:33 +00:00
2015-04-14 Nick Clifton <nickc@redhat.com>
* gas/lns/lns.exp: Add RL78 to list of targets using
DW_LNS_fixed_advance_pc.
Add SHF_COMPRESSED support to gas and objcopy This patch adds --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi} options to gas and objcopy for ELF files. They control how DWARF debug sections are compressed. --compress-debug-sections=none is equivalent to --nocompress-debug-sections. --compress-debug-sections=zlib and --compress-debug-sections=zlib-gnu are equivalent to --compress-debug-sections. --compress-debug-sections=zlib-gabi compresses DWARF debug sections with SHF_COMPRESSED from the ELF ABI. No linker changes are required to support SHF_COMPRESSED. bfd/ * archive.c (_bfd_get_elt_at_filepos): Also copy BFD_COMPRESS_GABI bit. * bfd.c (bfd::flags): Increase size to 18 bits. (BFD_COMPRESS_GABI): New. (BFD_FLAGS_SAVED): Add BFD_COMPRESS_GABI. (BFD_FLAGS_FOR_BFD_USE_MASK): Likewise. (bfd_update_compression_header): New fuction. (bfd_check_compression_header): Likewise. (bfd_get_compression_header_size): Likewise. (bfd_is_section_compressed_with_header): Likewise. * compress.c (MAX_COMPRESSION_HEADER_SIZE): New. (bfd_compress_section_contents): Return the uncompressed size if the full section contents is compressed successfully. Support converting from/to .zdebug* sections. (bfd_get_full_section_contents): Call bfd_get_compression_header_size to get compression header size. (bfd_is_section_compressed): Renamed to ... (bfd_is_section_compressed_with_header): This. Add a pointer argument to return compression header size. (bfd_is_section_compressed): Use it. (bfd_init_section_decompress_status): Call bfd_get_compression_header_size to get compression header size. Return FALSE if uncompressed section size is 0. * elf.c (_bfd_elf_make_section_from_shdr): Support converting from/to .zdebug* sections. * bfd-in2.h: Regenerated. binutils/ * objcopy.c (do_debug_sections): Add compress_zlib, compress_gnu_zlib and compress_gabi_zlib. (copy_options): Use optional_argument on compress-debug-sections. (copy_usage): Update --compress-debug-sections. (copy_file): Handle compress_zlib, compress_gnu_zlib and compress_gabi_zlib. (copy_main): Handle --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}. * doc/binutils.texi: Document --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}. binutils/testsuite/ * compress.exp: Add tests for --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}. * binutils-all/dw2-3.rS: New file. * binutils-all/dw2-3.rt: Likewise. * binutils-all/libdw2-compressedgabi.out: Likewise. gas/ * as.c (show_usage): Update --compress-debug-sections. (std_longopts): Use optional_argument on compress-debug-sections. (parse_args): Handle --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}. * as.h (compressed_debug_section_type): New. (flag_compress_debug): Change type to compressed_debug_section_type. --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}. * write.c (compress_debug): Set BFD_COMPRESS_GABI for --compress-debug-sections=zlib-gabi. Call bfd_get_compression_header_size to get compression header size. Don't rename section name for --compress-debug-sections=zlib-gabi. * config/tc-i386.c (compressed_debug_section_type): Set to COMPRESS_DEBUG_ZLIB. * doc/as.texinfo: Document --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}. gas/testsuite/ * gas/i386/dw2-compressed-1.d: New file. * gas/i386/dw2-compressed-2.d: Likewise. * gas/i386/dw2-compressed-3.d: Likewise. * gas/i386/x86-64-dw2-compressed-2.d: Likewise. * gas/i386/i386.exp: Run dw2-compressed-2, dw2-compressed-1, dw2-compressed-3 and x86-64-dw2-compressed-2. ld/testsuite/ * ld-elf/compress.exp: Add a test for --compress-debug-sections=zlib-gabi. (build_tests): Add 2 tests for --compress-debug-sections=zlib-gabi. (run_tests): Likewise. Verify linker output with zlib-gabi compressed debug input. * ld-elf/compressed1a.d: New file. * ld-elf/compressed1b.d: Likewise. * ld-elf/compressed1c.d: Likewise.
2015-04-08 14:53:54 +00:00
2015-04-08 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/dw2-compressed-1.d: New file.
* gas/i386/dw2-compressed-2.d: Likewise.
* gas/i386/dw2-compressed-3.d: Likewise.
* gas/i386/x86-64-dw2-compressed-2.d: Likewise.
* gas/i386/i386.exp: Run dw2-compressed-2, dw2-compressed-1,
dw2-compressed-3 and x86-64-dw2-compressed-2.
Remove is_zlib_supported Since zlib is always supported, there is no need for is_zlib_supported. binutils/testsuite/ * binutils-all/compress.exp: Remove is_zlib_supported check. * binutils-all/objdump.exp: Likewise. * binutils-all/readelf.exp (readelf_compressed_wa_test): Likewise. * lib/utils-lib.exp (run_dump_test): Likewise. * lib/binutils-common.exp (is_zlib_supported): Removed. gas/testsuite/ * lib/gas-defs.exp (run_dump_test): Remove is_zlib_supported check. ld/testsuite/ * ld-elf/compress.exp: Remove is_zlib_supported check. Fail if --compress-debug-sections doesn't work. * lib/ld-lib.exp (run_dump_test): Remove is_zlib_supported check.
2015-04-06 19:19:13 +00:00
2015-04-06 H.J. Lu <hongjiu.lu@intel.com>
* lib/gas-defs.exp (run_dump_test): Remove is_zlib_supported check.
Limit multi-byte nop instructions to 10 bytes There is no performance advantage to use multi-byte nop instructions greater than 10 bytes. This patch limits multi-byte nop instructions to 10 bytes. Since there is only one way to encode multi-byte nop instructions now, it also removed redundant nop tests. gas/ * config/tc-i386.c (i386_align_code): Limit multi-byte nop instructions to 10 bytes. gas/testsuite/ * gas/i386/i386.exp: Don't run nops-1-bdver1, nops-1-bdver2, nops-1-bdver3, nops-1-bdver4, nops-1-znver1, nops-1-btver1 nops-1-btver2, x86-64-nops-1-nocona, x86-64-nops-1-bdver1, x86-64-nops-1-bdver2, x86-64-nops-1-bdver3, x86-64-nops-1-bdver4, x86-64-nops-1-znver1, x86-64-nops-1-btver1 nor x86-64-nops-1-btver2. * gas/i386/nops-1-core2.d: Updated. * gas/i386/nops-1-k8.d: Likewise. * gas/i386/nops-4a-i686.d: Likewise. * gas/i386/nops-5-i686.d: Likewise. * gas/i386/nops-5.d: Likewise. * gas/i386/nops-6.d: Likewise. * gas/i386/x86-64-nops-1-core2.d: Likewise. * gas/i386/x86-64-nops-1-g64.d: Likewise. * gas/i386/x86-64-nops-1-k8.d: Likewise. * gas/i386/x86-64-nops-1.d: Likewise. * gas/i386/x86-64-nops-2.d: Likewise. * gas/i386/x86-64-nops-3.d: Likewise. * gas/i386/x86-64-nops-4-core2.d: Likewise. * gas/i386/x86-64-nops-4-k8.d: Likewise. * gas/i386/x86-64-nops-4.d: Likewise. * gas/i386/x86-64-nops-5-k8.d: Likewise. * gas/i386/x86-64-nops-5.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise. * gas/i386/ilp32/x86-64-nops-1.d: Likewise. * gas/i386/ilp32/x86-64-nops-2.d: Likewise. * gas/i386/ilp32/x86-64-nops-3.d: Likewise. * gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise. * gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise. * gas/i386/ilp32/x86-64-nops-4.d: Likewise. * gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise. * gas/i386/ilp32/x86-64-nops-5.d: Likewise. * gas/i386/nops-1-bdver1.d: Removed. * gas/i386/nops-1-bdver2.d: Likewise. * gas/i386/nops-1-bdver3.d: Likewise. * gas/i386/nops-1-bdver4.d: Likewise. * gas/i386/nops-1-btver1.d: Likewise. * gas/i386/nops-1-btver2.d: Likewise. * gas/i386/nops-1-znver1.d: Likewise. * gas/i386/x86-64-nops-1-bdver1.d: Likewise. * gas/i386/x86-64-nops-1-bdver2.d: Likewise. * gas/i386/x86-64-nops-1-bdver3.d: Likewise. * gas/i386/x86-64-nops-1-bdver4.d: Likewise. * gas/i386/x86-64-nops-1-btver1.d: Likewise. * gas/i386/x86-64-nops-1-btver2.d: Likewise. * gas/i386/x86-64-nops-1-nocona.d: Likewise. * gas/i386/x86-64-nops-1-znver1.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-nocona.d: Likewise.
2015-03-20 11:39:04 +00:00
2015-03-20 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Don't run nops-1-bdver1, nops-1-bdver2,
nops-1-bdver3, nops-1-bdver4, nops-1-znver1, nops-1-btver1
nops-1-btver2, x86-64-nops-1-nocona, x86-64-nops-1-bdver1,
x86-64-nops-1-bdver2, x86-64-nops-1-bdver3, x86-64-nops-1-bdver4,
x86-64-nops-1-znver1, x86-64-nops-1-btver1 nor
x86-64-nops-1-btver2.
* gas/i386/nops-1-core2.d: Updated.
* gas/i386/nops-1-k8.d: Likewise.
* gas/i386/nops-4a-i686.d: Likewise.
* gas/i386/nops-5-i686.d: Likewise.
* gas/i386/nops-5.d: Likewise.
* gas/i386/nops-6.d: Likewise.
* gas/i386/x86-64-nops-1-core2.d: Likewise.
* gas/i386/x86-64-nops-1-g64.d: Likewise.
* gas/i386/x86-64-nops-1-k8.d: Likewise.
* gas/i386/x86-64-nops-1.d: Likewise.
* gas/i386/x86-64-nops-2.d: Likewise.
* gas/i386/x86-64-nops-3.d: Likewise.
* gas/i386/x86-64-nops-4-core2.d: Likewise.
* gas/i386/x86-64-nops-4-k8.d: Likewise.
* gas/i386/x86-64-nops-4.d: Likewise.
* gas/i386/x86-64-nops-5-k8.d: Likewise.
* gas/i386/x86-64-nops-5.d: Likewise.
* gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise.
* gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise.
* gas/i386/ilp32/x86-64-nops-1.d: Likewise.
* gas/i386/ilp32/x86-64-nops-2.d: Likewise.
* gas/i386/ilp32/x86-64-nops-3.d: Likewise.
* gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise.
* gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise.
* gas/i386/ilp32/x86-64-nops-4.d: Likewise.
* gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise.
* gas/i386/ilp32/x86-64-nops-5.d: Likewise.
* gas/i386/nops-1-bdver1.d: Removed.
* gas/i386/nops-1-bdver2.d: Likewise.
* gas/i386/nops-1-bdver3.d: Likewise.
* gas/i386/nops-1-bdver4.d: Likewise.
* gas/i386/nops-1-btver1.d: Likewise.
* gas/i386/nops-1-btver2.d: Likewise.
* gas/i386/nops-1-znver1.d: Likewise.
* gas/i386/x86-64-nops-1-bdver1.d: Likewise.
* gas/i386/x86-64-nops-1-bdver2.d: Likewise.
* gas/i386/x86-64-nops-1-bdver3.d: Likewise.
* gas/i386/x86-64-nops-1-bdver4.d: Likewise.
* gas/i386/x86-64-nops-1-btver1.d: Likewise.
* gas/i386/x86-64-nops-1-btver2.d: Likewise.
* gas/i386/x86-64-nops-1-nocona.d: Likewise.
* gas/i386/x86-64-nops-1-znver1.d: Likewise.
* gas/i386/ilp32/x86-64-nops-1-nocona.d: Likewise.
Fix building and testing dwarf debug section compression feature when zlib is not available. PR gas/18087 gas/test * gas/i386/dw2-compress-1.d: Allow the test to pass regardless of whether the .debug_info section was compressed on not. bfd * compress.c (bfd_compress_section_contents): Do not define this function if it is not used.
2015-03-19 12:14:56 +00:00
2015-03-19 Nick Clifton <nickc@redhat.com>
PR gas/18087
* gas/i386/dw2-compress-1.d: Allow the test to pass regardless of
whether the .debug_info section was compressed on not.
Add a testcase for PR gas/18087 PR gas/18087 * gas/i386/dw2-compress-1.d: Revert the last change. * gas/i386/dw2-compress-3.d: New. * gas/i386/dw2-compress-3.s: Likewise. * gas/i386/i386.exp: Run dw2-compress-3 for ELF targets.
2015-03-18 16:20:38 +00:00
2015-03-18 H.J. Lu <hongjiu.lu@intel.com>
PR gas/18087
* gas/i386/dw2-compress-1.d: Revert the last change.
* gas/i386/dw2-compress-3.d: New.
* gas/i386/dw2-compress-3.s: Likewise.
* gas/i386/i386.exp: Run dw2-compress-3 for ELF targets.
Fix debug section compression so that it is only performed if it would make the section smaller. PR binutils/18087 gas * doc/as.texinfo: Note that when gas compresses debug sections the compression is only performed if it makes the section smaller. * write.c (compress_debug): Do not compress a debug section if doing so would make it larger. tests * gas/i386/dw2-compress-1.d: Do not expect the .debug_abbrev or .debug_info sections to be compressed. binu * doc/binutils.texi: Note that when objcopy compresses debug sections the compression is only performed if it makes the section smaller. bfd * coffgen.c (make_a_section_from_file): Only prepend a z to a debug section's name if the section was actually compressed. * elf.c (_bfd_elf_make_section_from_shdr): Likewise. * compress.c (bfd_init_section_compress_status): Do not compress the section if doing so would make it bigger. In such cases leave the section alone and return COMPRESS_SECTION_NONE.
2015-03-18 15:47:13 +00:00
2015-03-18 Jon Turney <jon.turney@dronecode.org.uk>
Nick Clifton <nickc@redhat.com>
PR binutils/18087
* gas/i386/dw2-compress-1.d: Do not expect the .debug_abbrev or
.debug_info sections to be compressed.
Add znver1 processor
2015-03-17 16:19:15 +00:00
2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
* gas/i386/i386.exp: Add new znver1 test cases.
* gas/i386/arch-13-znver1.d: New.
* gas/i386/arch-13.d: New.
* gas/i386/arch-13.s: New.
* gas/i386/clzero.d: New.
* gas/i386/clzero.s: New.
* gas/i386/nops-1-znver1.d: New.
* gas/i386/x86-64-arch-3-znver1.d: New.
* gas/i386/x86-64-arch-3.d: New.
* gas/i386/x86-64-arch-3.s: New.
* gas/i386/x86-64-clzero.d: New.
* gas/i386/x86-64-nops-1-znver1.d: New.
MIPS: Fix constraint issues with the R6 beqc and bnec instructions opcodes/ * mips-opc.c (decode_mips_operand): Fix constraint issues with u and y operands. gas/testsuite/ * gas/mips/mips.exp: Added branch constraints testcase. * gas/mips/r6-branch-constraints.s: New test. * gas/mips/r6-branch-constraints.l: New test.
2015-03-13 22:42:55 +00:00
2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
* gas/mips/mips.exp: Added branch constraints testcase.
* gas/mips/r6-branch-constraints.s: New test.
* gas/mips/r6-branch-constraints.l: New test.
Add support for MIPS R6 evp and dvp instructions. opcodes/ * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions. gas/testsuite/ * gas/mips/r6.s: Add evp and dvp instructions. * gas/mips/r6.d: Likewise. * gas/mips/r6-n32.d: Likewise. * gas/mips/r6-n64.d: Likewise.
2015-03-13 22:02:16 +00:00
2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
* gas/mips/r6.s: Add evp and dvp instructions.
* gas/mips/r6.d: Likewise.
* gas/mips/r6-n32.d: Likewise.
* gas/mips/r6-n64.d: Likewise.
[AArch64] Don't warn on XZR/SP overlapping when it's in load/store 2015-03-13 Jiong Wang <jiong.wang@arm.com> gas/ * config/tc-aarch64.c (warn_unpredictable_ldst): Don't warn on reg number 31. gas/testsuite/ * gas/aarch64/diagnostic.s: New testcases. * gas/aarch64/diagnostic.l: New error match.
2015-03-13 12:02:23 +00:00
2015-03-13 Jiong Wang <jiong.wang@arm.com>
* gas/aarch64/diagnostic.s: New testcases.
* gas/aarch64/diagnostic.l: New error match.
[AArch64] Don't tail-pads sections to the alignment 2015-03-13 Jiong Wang <jiong.wang@arm.com> gas/ * config/tc-aarch64.h (SUB_SEGMENT_ALIGN): Define to be zero. gas/testsuite/ * gas/aarch64/tail_padding.s: New testcase. * gas/aarch64/tail_padding.d: New expectation file.
2015-03-13 12:00:37 +00:00
2015-03-13 Jiong Wang <jiong.wang@arm.com>
* gas/aarch64/tail_padding.s: New testcase.
* gas/aarch64/tail_padding.d: New expectation file.
S/390: Add more IBM z13 instructions opcodes/ 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.c: Add new IBM z13 instructions. * s390-opc.txt: Likewise. gas/testsuite/ 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * gas/s390/zarch-z13.d: Add more z13 instructions. * gas/s390/zarch-z13.s: Likewise.
2015-03-10 11:44:54 +00:00
2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gas/s390/zarch-z13.d: Add more z13 instructions.
* gas/s390/zarch-z13.s: Likewise.
[ARM]Fix "align directive causes MAP_DATA symbol to be lost" gas/ 2015-03-10 Renlin Li <renlin.li@arm.com> * config/tc-arm.c (mapping_state): Remove first MAP_DATA emitting code. (mapping_state_2): Emit first MAP_DATA symbol here. gas/testsuite/ 2015-03-05 Renlin Li <renlin.li@arm.com> * gas/arm/dis-data.d: Adjust the desired output. * gas/arm/dis-data2.d: Ditto.
2015-03-10 11:34:50 +00:00
2015-03-05 Renlin Li <renlin.li@arm.com>
* gas/arm/dis-data.d: Adjust the desired output.
* gas/arm/dis-data2.d: Ditto.
[AARCH64] Remove Load/Store register (unscaled immediate) alias. opcodes/ChangeLog: 2015-03-10 Renlin Li <renlin.li@arm.com> * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb, stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and related alias. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/testsuite/ChangeLog: 2015-03-10 Renlin Li <renlin.li@arm.com> * gas/aarch64/ldst-reg-uns-imm.d: Adjust expected output. * gas/aarch64/ldst-reg-unscaled-imm.d: Likewise. * gas/aarch64/reloc-insn.d: Likewise.
2015-03-10 11:27:56 +00:00
2015-03-10 Renlin Li <renlin.li@arm.com>
* gas/aarch64/ldst-reg-uns-imm.d: Adjust expected output.
* gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
[ARM]Fix "align directive causes MAP_DATA symbol to be lost" gas/ 2015-03-10 Renlin Li <renlin.li@arm.com> * config/tc-arm.c (mapping_state): Remove first MAP_DATA emitting code. (mapping_state_2): Emit first MAP_DATA symbol here. gas/testsuite/ 2015-03-05 Renlin Li <renlin.li@arm.com> * gas/arm/dis-data.d: Adjust the desired output. * gas/arm/dis-data2.d: Ditto.
2015-03-10 11:34:50 +00:00
* gas/aarch64/reloc-insn.d: Likewise.
2015-03-10 Matthew Wahab <matthew.wahab@arm.com>
[AArch64] Set the minimum alignment on code segments gas/ 2015-03-10 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (mapping_state): Set minimum alignment for code sections. gas/testsuite 2015-03-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/codealign.d: Add test for code section alignment. * gas/aarch64/codealign.s: New file.
2015-03-10 11:20:57 +00:00
* gas/aarch64/codealign.d: Add test for code section alignment.
* gas/aarch64/codealign.s: New file.
Allow MOVK for R_AARCH64_TLSLE_MOVW_TPREL_G{0,1}NC bfd/ PR gas/17843 * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Expect R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC to be used with MOVK rather than MOVZ. gas/ PR gas/17843 * config/tc-aarch64.c (process_movw_reloc_info): Allow R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC for MOVK. gas/testsuite/ PR gas/17843 * gas/aarch64/tls.s, gas/aarch64/tls.d: Add test for R_AARCH64_TLSLE_MOVW_TPREL_G0/R_AARCH64_TLSLE_MOVW_TPREL_G1_NC sequence. ld/testsuite/ PR gas/17843 * ld-aarch64/tlsle.s, ld-aarch64/tlsle.d: New test. * ld-aarch64/aarch64-elf.exp: Run it.
2015-03-04 09:08:49 +00:00
2015-03-04 Richard Sandiford <richard.sandiford@arm.com>
PR gas/17843
* gas/aarch64/tls.s, gas/aarch64/tls.d: Add test for
R_AARCH64_TLSLE_MOVW_TPREL_G0/R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
sequence.
Pad only text sections at end by default gas/ * write.c (SUB_SEGMENT_ALIGN): Don't pad non-code sections at end to their alignment. gas/testsuite/ * gas/sparc/pcrel.d: Update for changed padding in data sections. * gas/sparc/pcrel64.d: Likewise. ld/testsuite/ * ld-sparc/gotop32.rd: Update for changed padding in data sections. * ld-sparc/gotop32.td: Likewise. * ld-sparc/gotop64.rd: Likewise. * ld-sparc/gotop64.td: Likewise. * ld-tilegx/external.s: Align .data. * ld-tilepro/external.s: Likewise.
2015-02-24 23:06:36 +00:00
2015-02-28 Alan Modra <amodra@gmail.com>
* gas/sparc/pcrel.d: Update for changed padding in data sections.
* gas/sparc/pcrel64.d: Likewise.
Adding test case for abuse of :got: in offset load The :got: modifier is not meaningful in a register offset load store instruction and should result in a diagnostic.
2015-02-18 18:32:43 +00:00
2015-02-26 Marcus Shawcroft <marcus.shawcroft@arm.com>
* gas/aarch64/diagnostic.s: Add LDR test.
* gas/aarch64/diagnostic.l: Likewise.
Add test case for ADR :got:foo The modifier :got: does not make sense on an ADR instruction. Add a test case to ensure we gripe.
2015-02-05 13:16:33 +00:00
2015-02-26 Marcus Shawcroft <marcus.shawcroft@arm.com>
* gas/aarch64/diagnostic.s: Add ADR test.
* gas/aarch64/diagnostic.l: Likewise.
avr/objdump: Support dumping .avr.prop section. Add support to objdump for dumping the .avr.prop section in a structured way. binutils/ChangeLog: * od-elf32_avr.c: Add elf32-avr.h include. (OPT_AVRPROP): Define. (options[]): Add 'avr-prop' entry. (elf32_avr_help): Add avr-prop help text. (elf32_avr_dump_avr_prop): New function. (elf32_avr_dump): Add check for avr-prop. bfd/ChangeLog: * elf32-avr.h (struct avr_property_header): New strucure. (avr_elf32_load_property_records): Declare. (avr_elf32_property_record_name): Declare. * elf32-avr.c: Add bfd_stdint.h include. (retrieve_local_syms): New function. (get_elf_r_symndx_section): New function. (get_elf_r_symndx_offset): New function. (internal_reloc_compare): New function. (struct avr_find_section_data): New structure. (avr_is_section_for_address): New function. (avr_find_section_for_address): New function. (avr_elf32_load_records_from_section): New function. (avr_elf32_load_property_records): New function. (avr_elf32_property_record_name): New function. gas/testsuite/ChangeLog: * gas/avr/avr-prop-1.d: New file. * gas/avr/avr-prop-1.s: New file.
2015-01-08 21:55:43 +00:00
2015-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
* gas/avr/avr-prop-1.d: New file.
* gas/avr/avr-prop-1.s: New file.
[SH] Fix clrs, sets, pref insn arch memberships. opcodes/ * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of arch_sh_up. (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of arch_sh2a_nofpu_or_sh4_nommu_nofpu_up. gas/testsuite/ * gas/sh/arch/arch.exp: Replace dead code to generate expected .s files with ... * gas/sh/arch/sh-opc-gen-as.pl: ... this new script. * gas/sh/arch/arch_expected.txt: Regenerate. * gas/sh/arch/sh-dsp.s: Likewise. * gas/sh/arch/sh-opc-gen-as.pl: Likewise. * gas/sh/arch/sh.s: Likewise. * gas/sh/arch/sh2.s: Likewise. * gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s: Likewise. * gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Likewise. * gas/sh/arch/sh2a-nofpu.s: Likewise. * gas/sh/arch/sh2a-or-sh3e.s: Likewise. * gas/sh/arch/sh2a-or-sh4.s: Likewise. * gas/sh/arch/sh2a.s: Likewise. * gas/sh/arch/sh2e.s: Likewise. * gas/sh/arch/sh3-dsp.s: Likewise. * gas/sh/arch/sh3-nommu.s: Likewise. * gas/sh/arch/sh3.s: Likewise. * gas/sh/arch/sh3e.s: Likewise. * gas/sh/arch/sh4-nofpu.s: Likewise. * gas/sh/arch/sh4-nommu-nofpu.s: Likewise. * gas/sh/arch/sh4.s: Likewise. * gas/sh/arch/sh4a-nofpu.s: Likewise. * gas/sh/arch/sh4a.s: Likewise. * gas/sh/arch/sh4al-dsp.s: Likewise. ld/testsuite/ * ld-sh/arch/arch_expected.txt: Regenerate. * ld-sh/arch/sh-dsp.s: Likewise. * ld-sh/arch/sh.s: Likewise. * ld-sh/arch/sh2.s: Likewise. * ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s: Likewise. * ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Likewise. * ld-sh/arch/sh2a-nofpu.s: Likewise. * ld-sh/arch/sh2a-or-sh3e.s: Likewise. * ld-sh/arch/sh2a-or-sh4.s: Likewise. * ld-sh/arch/sh2a.s: Likewise. * ld-sh/arch/sh2e.s: Likewise. * ld-sh/arch/sh3-dsp.s: Likewise. * ld-sh/arch/sh3-nommu.s: Likewise. * ld-sh/arch/sh3.s: Likewise. * ld-sh/arch/sh3e.s: Likewise. * ld-sh/arch/sh4-nofpu.s: Likewise. * ld-sh/arch/sh4-nommu-nofpu.s: Likewise. * ld-sh/arch/sh4.s: Likewise. * ld-sh/arch/sh4a-nofpu.s: Likewise. * ld-sh/arch/sh4a.s: Likewise. * ld-sh/arch/sh4al-dsp.s: Likewise.
2015-02-25 20:22:54 +00:00
2015-02-25 Kaz Kojima <kkojima@rr.iij4u.or.jp>
Oleg Endo <olegendo@gcc.gnu.org>
* gas/sh/arch/arch.exp: Replace dead code to generate expected .s files
with ...
* gas/sh/arch/sh-opc-gen-as.pl: ... this new script.
* gas/sh/arch/arch_expected.txt: Regenerate.
* gas/sh/arch/sh-dsp.s: Likewise.
* gas/sh/arch/sh-opc-gen-as.pl: Likewise.
* gas/sh/arch/sh.s: Likewise.
* gas/sh/arch/sh2.s: Likewise.
* gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s: Likewise.
* gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Likewise.
* gas/sh/arch/sh2a-nofpu.s: Likewise.
* gas/sh/arch/sh2a-or-sh3e.s: Likewise.
* gas/sh/arch/sh2a-or-sh4.s: Likewise.
* gas/sh/arch/sh2a.s: Likewise.
* gas/sh/arch/sh2e.s: Likewise.
* gas/sh/arch/sh3-dsp.s: Likewise.
* gas/sh/arch/sh3-nommu.s: Likewise.
* gas/sh/arch/sh3.s: Likewise.
* gas/sh/arch/sh3e.s: Likewise.
* gas/sh/arch/sh4-nofpu.s: Likewise.
* gas/sh/arch/sh4-nommu-nofpu.s: Likewise.
* gas/sh/arch/sh4.s: Likewise.
* gas/sh/arch/sh4a-nofpu.s: Likewise.
* gas/sh/arch/sh4a.s: Likewise.
* gas/sh/arch/sh4al-dsp.s: Likewise.
Adds support for generating notes in V850 binaries. bfd * elf32-v850.c (v850_set_note): New function. Creates a Renesas style note entry. (v850_elf_make_note_section): New function. Creates a note section. (v850_elf_create_sections): New function. Create a note section if one is not already present. (v850_elf_set_note): New function. Adds a note to a bfd. (v850_elf_copy_private_bfd_data): New function. Copies V850 notes. (v850_elf_merge_notes): New function. Merges V850 notes. (print_v850_note): New function. Displays a V850 note. (v850_elf_print_notes): New function. Displays all notes attached to a bfd. (v850_elf_merge_private_bfd_data): Call v850_elf_merge_notes. (v850_elf_print_private_bfd_data): Call v850_elf_print_notes. (v850_elf_fake_sections): Set the type of the V850 note section. * bfd-in.h (v850_elf_create_sections): Add prototype. (v850_elf_set_note): Add prototype. * bfd-in2.h: Regenerate. binutils* readelf.c (get_machine_flags): Remove deprecated V850 machine flags. (get_v850_section_type_name): New function. Handles V850 special sections. (get_section_type_name): Add support for V850. (get_v850_elf_note_type): New function. Returns the name of a V850 note. (print_v850_note): New function. Prints a V850 note. (process_v850_notes): New function. Prints V850 notes. (process_note_sections): Add support for V850. binutils/testsute * binutils-all/objcopy.exp: Skip the strip-10 test for the V850. gas * config/tc-v850.c (soft_float): New variable. (v850_data_8): New variable. (md_show_usage): Add -msoft-float/-mhard-float. (md_parse_option): Likewise. (md_begin): Set the default value of soft_float. (v850_md_end): New function. Creates a note section. * config/tc-v850.h (md_end): Define. * doc/c-v850.texi: Document -msoft-float/-mhard-float. gas/testsuite * gas/elf/elf.exp: Add special version of the section2 test for the V850. * gas/elf/section2.e-v850: New file. include/elf * v850.h (EF_RH850_SIMD): Delete deprecated flag. (EF_RH850_CACHE): Likewise. (EF_RH850_MMU): Likewise. (EF_RH850_DATA_ALIGN8): Likewise. (SHT_RENESAS_IOP): Fix typo in name. (SHT_RENESAS_INFO): Define. (V850_NOTE_SECNAME): Define. (SIZEOF_V850_NOTE): Define. (V850_NOTE_NAME): Define. (enum v850_notes): New enum. (NUM_V850_NOTES): Define. ld/ChangeLog 2015-02-24 Nick Clifton <nickc@redhat.com> * Makefile.am (ev850.c): Add dependency upon $(srcdir)/emultempl/v850elf.em. (ev850_rh850.c): Likewise. * Makefile.in: Regenerate. * emultempl/v850elf.em: New file. * emulparams/v850.sh (EXTRA_EM_FILE): Define. * emulparams/v850_rh850.sh (EXTRA_EM_FILE): Define. * scripttempl/v850.sc: Add .note.renesas section. * scripttempl/v850_rh850.sc: Likewise. ld/testsuite * ld-elf/extract-symbol-1sec.d: Expect to fail on the V850.
2015-02-24 17:54:09 +00:00
2015-02-24 Nick Clifton <nickc@redhat.com>
* gas/elf/elf.exp: Add special version of the section2 test for
the V850.
* gas/elf/section2.e-v850: New file.
[ARM][gas] Use as_tsktsk instead of as_warn for deprecation messages. * config/tc-arm.c (warn_deprecated_sp): Use as_tsktsk instead of as_warn for deprecation messages. (encode_arm_addr_mode_2): Likewise. (check_obsolete): Likewise. (do_rd_rm_rn): Likewise. (do_co_reg): Likewise. (do_setend): Likewise. (do_t_mov_cmp): Likewise. (do_neon_ldr_str): Likewise. (opcode_lookup): Likewise. (if_fsm_post_encode): Likewise. (md_assemble): Likewise. * gas/arm/armv1.l: Remove 'Warning: ' from expected messages for deprecations. * gas/arm/armv8-a-bad.l: Likewise. * gas/arm/armv8-a-it-bad.l: Likewise. * gas/arm/depr-swp.l: Likewise. * gas/arm/ldsgeb.l: Likewise. * gas/arm/ldsgeh.l: Likewise. * gas/arm/thumb2_bad_reg.l: Likewise. * gas/arm/thumb32.l: Likewise. * gas/arm/udf.l: Likewise. * gas/arm/vstr-arm-bad.l: Likewise.
2015-02-09 11:20:30 +00:00
2015-02-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gas/arm/armv1.l: Remove 'Warning: ' from expected messages
for deprecations.
* gas/arm/armv8-a-bad.l: Likewise.
* gas/arm/armv8-a-it-bad.l: Likewise.
* gas/arm/depr-swp.l: Likewise.
* gas/arm/ldsgeb.l: Likewise.
* gas/arm/ldsgeh.l: Likewise.
* gas/arm/thumb2_bad_reg.l: Likewise.
* gas/arm/thumb32.l: Likewise.
* gas/arm/udf.l: Likewise.
* gas/arm/vstr-arm-bad.l: Likewise.
FT32 initial support FT32 is a new 32-bit RISC core developed by FTDI for embedded applications. * configure.ac: Add FT32 support. * configure: Regenerate. bfd/ * Makefile.am: Add FT32 files. * archures.c (enum bfd_architecture): Add bfd_arch_ft32. (bfd_mach_ft32): Define. (bfd_ft32_arch): Declare. (bfd_archures_list): Add bfd_ft32_arch. * config.bfd: Handle FT32. * configure.ac: Likewise. * cpu-ft32.c: New file. * elf32-ft32.c: New file. * reloc.c (BFD_RELOC_FT32_10, BFD_RELOC_FT32_20, BFD_RELOC_FT32_17, BFD_RELOC_FT32_18): Define. * targets.c (_bfd_target_vector): Add ft32_elf32_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * Makefile.in: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * readelf.c: Add FT32 support. gas/ * Makefile.am: Add FT32 files. * config/tc-ft32.c: New file. * config/tc-ft32.h: New file. * configure.tgt: Add FT32 support. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. gas/testsuite/ * gas/ft32/ft32.exp: New file. * gas/ft32/insn.d: New file. * gas/ft32/insn.s: New file. include/ * dis-asm.h (print_insn_ft32): Declare. include/elf/ * common.h (EM_FT32): Define. * ft32.h: New file. include/opcode/ * ft32.h: New file. ld/ * Makefile.am: Add FT32 files. * configure.tgt: Handle FT32 target. * emulparams/elf32ft32.sh: New file. * scripttempl/ft32.sc: New file. * Makefile.in: Regenerate. opcodes/ * Makefile.am: Add FT32 files. * configure.ac: Handle FT32. * disassemble.c (disassembler): Call print_insn_ft32. * ft32-dis.c: New file. * ft32-opc.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2015-01-28 05:06:43 +00:00
2015-01-28 James Bowman <james.bowman@ftdichip.com>
* gas/ft32/ft32.exp: New file.
* gas/ft32/insn.d: New file.
* gas/ft32/insn.s: New file.
Extend .reloc to accept some BFD_RELOCs Tests that bfd_perform_reloc doesn't freak over a NONE reloc at end of section. gas/ * read.c (s_reloc): Match BFD_RELOC_NONE, BFD_RELOC{8,16,32,64}. * write.c (get_frag_for_reloc): Allow match just past end of frag. gas/testsuite/ * gas/all/none.s, * gas/all/none.d: New test. * gas/all/gas.exp: Run it.
2015-01-19 08:27:04 +00:00
2015-01-19 Alan Modra <amodra@gmail.com>
* gas/all/none.s,
* gas/all/none.d: New test.
* gas/all/gas.exp: Run it.
S/390: Add support for IBM z13. - 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-16 11:19:21 +00:00
2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gas/s390/esa-g5.d: Add a variant without the optional operand.
* gas/s390/esa-g5.s: Likewise.
* gas/s390/esa-z9-109.d: Likewise.
* gas/s390/esa-z9-109.s: Likewise.
* gas/s390/zarch-z9-109.d: Likewise.
* gas/s390/zarch-z9-109.s: Likewise.
* gas/s390/zarch-z10.d: For variants with a zero optional argument
it is not dumped by objdump anymore.
* gas/s390/zarch-zEC12.d: Likewise.
* gas/s390/zarch-z13.d: New file.
* gas/s390/zarch-z13.s: New file.
* gas/s390/s390.exp: Run the test for the z13 files.
[ARM] vcmp/vcmpe should accept #0x0 as an operand gas/ 2015-01-13 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (parse_ifimm_zero): Accept #0x0 as a synonym for #0, restoring previous behaviour. gas/testsuite/ 2015-01-13 Matthew Wahab <matthew.wahab@arm.com> * gas/arm/ual-vcmp.s: Add vcmp, vcmpe with #0x0 operand. * gas/ual/vcmp.d: Update expected output. * gas/ual/vcmp-zero-bad.l: Likewise
2015-01-13 15:44:47 +00:00
2015-01-13 Matthew Wahab <matthew.wahab@arm.com>
* gas/arm/ual-vcmp.s: Add vcmp, vcmpe with #0x0 operand.
* gas/ual/vcmp.d: Update expected output.
* gas/ual/vcmp-zero-bad.l: Likewise
gas: allow labeling of CFI instructions When runtime patching code (like e.g. done by the Linux kernel) there may be cases where the set of stack frame alterations differs between unpatched and patched code. Consequently the corresponding unwind data needs patching too. Locating the right places within an FDE, however, is rather cumbersome without a way to insert labels in the resulting section. Hence this patch introduces a new directive, .cfi_label. Note that with the way CFI data gets emitted currently (at the end of the assembly process) this can't support local FB- and dollar-labels. gas/ 2015-01-12 Jan Beulich <jbeulich@suse.com> * gas/dw2gencfi.c (cfi_add_label, dot_cfi_label): New. (cfi_pseudo_table): Add "cfi_label". (output_cfi_insn): Handle CFI_label. (select_cie_for_fde): Als terminate CIE when encountering CFI_label. * dw2gencfi.h (cfi_add_label): Declare. (struct cfi_insn_data): New member "sym_name". (CFI_label): New. * read.c (read_symbol_name): Drop "static". * read.h (read_symbol_name): Declare. gas/testsuite/ 2015-01-12 Jan Beulich <jbeulich@suse.com> gas/cfi/cfi-label.d, gas/cfi/cfi-label.s: New. gas/cfi/cfi.exp: Run new tests.
2015-01-12 14:24:20 +00:00
2015-01-12 Jan Beulich <jbeulich@suse.com>
gas/cfi/cfi-label.d, gas/cfi/cfi-label.s: New.
gas/cfi/cfi.exp: Run new tests.
arm: properly range check immediate operands of VSHL and VQSHL These two, other than VQSHLU, didn't have their immediates properly range checked so far. (Re-sending unchanged from the original v2 due to never having got an answer to https://sourceware.org/ml/binutils/2013-04/msg00121.html.) gas/ 2015-01-12 Jan Beulich <jbeulich@suse.com> * gas/config/tc-arm.c (do_neon_shl_imm): Check immediate range. (do_neon_qshl_imm): Likewise. gas/testsuite/ 2015-01-12 Jan Beulich <jbeulich@suse.com> * gas/arm/neon-addressing-bad.s: Add test for invalid VSHL, VQSHL, and VQSHLU immediates. * gas/arm/neon-addressing-bad.l: Update accordingly.
2015-01-12 08:05:19 +00:00
2015-01-12 Jan Beulich <jbeulich@suse.com>
* gas/arm/neon-addressing-bad.s: Add test for invalid VSHL,
VQSHL, and VQSHLU immediates.
* gas/arm/neon-addressing-bad.l: Update accordingly.
gas/avr: Prevent incorrect overflow errors for diff fixups. When fixups are converted to a difference type within md_apply_fix, we previously left the contents of VALP (the value that was initially computed within write.c:fixup_segment) unchanged. This is harmless, except that this value is used within write.c:fixup_segment once we return from md_apply_fix to perform an overflow check. In some cases, the value computed in write.c:fixup_segment is so wrong that an overflow error can be triggered. These errors are incorrect. This patch avoids the overflow errors by adjusting the value in write.c:fixup_segment using the VALP pointer in md_apply_fix. A test for this issue is included. gas/ChangeLog: * config/tc-avr.c (md_apply_fix): Update the contents of VALP for diff fixups. gas/testsuite/ChangeLog: * gas/avr/large-debug-line-table.d: New file. * gas/avr/large-debug-line-table.s: New file.
2015-01-04 00:03:16 +00:00
2015-01-10 Andrew Burgess <andrew.burgess@embecosm.com>
* gas/avr/large-debug-line-table.d: New file.
* gas/avr/large-debug-line-table.s: New file.
ChangeLog rotatation and copyright year update
2015-01-01 14:15:26 +00:00
2015-01-01 Alan Modra <amodra@gmail.com>
AVR: Assembler now prepares for linker relaxation by default. Have the assembler prepare for linker relaxation by default. This means that users will be able to make use of linker relaxation without having to adjust the assembler flags, this can make life easier when compiling libraries. Having this on by default in the assembler should make no difference to the assembler code produced, however, some of the debug information will be slightly less compressed. A few tests needed to be updated as a result of this change as they relied on linker relaxation support being off by default. I've tightened up the definition of which sections can be relaxed on AVR as part of this commit, the assembler used to think that all non-debugging sections could be relaxed, when in reality only code sections can be relaxed for AVR. The previous definition was not dangerous, just over cautious. The new tighter definition allows an extra test (gas/testsuite/gas/all/forward.d) to continue to pass. gas/ChangeLog: * config/tc-avr.c (struct avr_opt_s): Change link_relax to no_link_relax, extend comment. (enum options): Add new OPTION_NO_LINK_RELAX. (md_longopts): Add entry for -mno-link-relax. (md_parse_option): Handle OPTION_NO_LINK_RELAX, and update OPTION_LINK_RELAX. (md_begin): Initialise linkrelax from no_link_relax. (md_show_usage): Include -mno-link-relax option. (relaxable_section): Only allocatable code sections can be relaxed. * config/tc-avr.h (TC_LINKRELAX_FIXUP): Define. gas/testsuite/ChangeLog: * gas/all/gas.exp: Test will not pass on AVR due to linker relaxation support. * gas/avr/noreloc_withoutrelax.d: Add -mno-link-relax option. * gas/avr/link-relax-elf-flag-clear.d: Likewise. ld/testsuite/ChangeLog: * ld/testsuite/ld-avr/relax-elf-flags-02.d: Add -mno-link-relax option. * ld/testsuite/ld-avr/relax-elf-flags-03.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-04.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-05.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-06.d: Likewise.
2014-10-27 10:51:17 +00:00
ChangeLog rotatation and copyright year update
2015-01-01 14:15:26 +00:00
Update year range in copyright notice of all files.
AVR: Assembler now prepares for linker relaxation by default. Have the assembler prepare for linker relaxation by default. This means that users will be able to make use of linker relaxation without having to adjust the assembler flags, this can make life easier when compiling libraries. Having this on by default in the assembler should make no difference to the assembler code produced, however, some of the debug information will be slightly less compressed. A few tests needed to be updated as a result of this change as they relied on linker relaxation support being off by default. I've tightened up the definition of which sections can be relaxed on AVR as part of this commit, the assembler used to think that all non-debugging sections could be relaxed, when in reality only code sections can be relaxed for AVR. The previous definition was not dangerous, just over cautious. The new tighter definition allows an extra test (gas/testsuite/gas/all/forward.d) to continue to pass. gas/ChangeLog: * config/tc-avr.c (struct avr_opt_s): Change link_relax to no_link_relax, extend comment. (enum options): Add new OPTION_NO_LINK_RELAX. (md_longopts): Add entry for -mno-link-relax. (md_parse_option): Handle OPTION_NO_LINK_RELAX, and update OPTION_LINK_RELAX. (md_begin): Initialise linkrelax from no_link_relax. (md_show_usage): Include -mno-link-relax option. (relaxable_section): Only allocatable code sections can be relaxed. * config/tc-avr.h (TC_LINKRELAX_FIXUP): Define. gas/testsuite/ChangeLog: * gas/all/gas.exp: Test will not pass on AVR due to linker relaxation support. * gas/avr/noreloc_withoutrelax.d: Add -mno-link-relax option. * gas/avr/link-relax-elf-flag-clear.d: Likewise. ld/testsuite/ChangeLog: * ld/testsuite/ld-avr/relax-elf-flags-02.d: Add -mno-link-relax option. * ld/testsuite/ld-avr/relax-elf-flags-03.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-04.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-05.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-06.d: Likewise.
2014-10-27 10:51:17 +00:00
ChangeLog rotatation and copyright year update
2015-01-01 14:15:26 +00:00
For older changes see ChangeLog-2014
Split ChangeLog files.
2004-01-02 11:16:21 +00:00
ChangeLog rotatation and copyright year update
2015-01-01 14:15:26 +00:00
Copyright (C) 2015 Free Software Foundation, Inc.
Add copyright notices
2012-12-10 12:48:03 +00:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Split ChangeLog files.
2004-01-02 11:16:21 +00:00
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
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