2012-09-18 14:52:43 +00:00
|
|
|
|
2012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c: Changed ldra and strl-form mnemonics
|
|
|
|
|
|
to lda and stl-form.
|
|
|
|
|
|
|
2012-09-18 14:19:04 +00:00
|
|
|
|
2012-09-18 Chao-ying Fu <fu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* micromips-opc.c (micromips_opcodes): Correct the encoding of
|
|
|
|
|
|
the "swxc1" instruction.
|
|
|
|
|
|
|
2012-09-17 17:43:42 +00:00
|
|
|
|
2012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
|
|
|
|
|
|
the parameter 'inst'.
|
|
|
|
|
|
(aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
|
|
|
|
|
|
(convert_mov_to_movewide): Change to assert (0) when
|
|
|
|
|
|
aarch64_wide_constant_p returns FALSE.
|
|
|
|
|
|
|
2012-09-15 00:07:05 +00:00
|
|
|
|
2012-09-14 David Edelsohn <dje.gcc@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2012-09-14 10:49:03 +00:00
|
|
|
|
2012-09-14 Anthony Green <green@moxielogic.com>
|
|
|
|
|
|
|
|
|
|
|
|
* moxie-dis.c (print_insn_moxie): Branch targets are relative to
|
|
|
|
|
|
the address after the branch instruction.
|
|
|
|
|
|
|
2012-09-13 22:24:51 +00:00
|
|
|
|
2012-09-13 Anthony Green <green@moxielogic.com>
|
|
|
|
|
|
|
|
|
|
|
|
* moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
|
|
|
|
|
|
|
2012-09-10 22:30:57 +00:00
|
|
|
|
2012-09-10 Matthias Klose <doko@ubuntu.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config.in: Disable sanity check for kfreebsd.
|
|
|
|
|
|
|
2012-09-10 17:00:44 +00:00
|
|
|
|
2012-09-10 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
|
2012-09-04 13:52:06 +00:00
|
|
|
|
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ia64-asmtab.h (completer_index): Extend bitfield to full uint.
|
|
|
|
|
|
* ia64-gen.c: Promote completer index type to longlong.
|
|
|
|
|
|
(irf_operand): Add new register recognition.
|
|
|
|
|
|
(in_iclass_mov_x): Add an entry for the new mov_* instruction type.
|
|
|
|
|
|
(lookup_specifier): Add new resource recognition.
|
|
|
|
|
|
(insert_bit_table_ent): Relax abort condition according to the
|
|
|
|
|
|
changed completer index type.
|
|
|
|
|
|
(print_dis_table): Fix printf format for completer index.
|
|
|
|
|
|
* ia64-ic.tbl: Add a new instruction class.
|
|
|
|
|
|
* ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
|
|
|
|
|
|
* ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
|
|
|
|
|
|
* ia64-opc.h: Define short names for new operand types.
|
|
|
|
|
|
* ia64-raw.tbl: Add new RAW resource for DAHR register.
|
|
|
|
|
|
* ia64-waw.tbl: Add new WAW resource for DAHR register.
|
|
|
|
|
|
* ia64-asmtab.c: Regenerate.
|
|
|
|
|
|
|
2012-08-29 22:34:04 +00:00
|
|
|
|
2012-08-29 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (VXASHB_MASK): New define.
|
|
|
|
|
|
(powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
|
|
|
|
|
|
|
* ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
(powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
vupklsh>: Use VXVA_MASK.
<vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
<mfvscr>: Use VXVAVB_MASK.
<mtvscr>: Use VXVDVA_MASK.
<vspltb>: Use VXUIMM4_MASK.
<vsplth>: Use VXUIMM3_MASK.
<vspltw>: Use VXUIMM2_MASK.
2012-08-28 16:41:07 +00:00
|
|
|
|
2012-08-28 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
|
|
|
|
|
|
VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
|
|
|
|
|
|
(powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
|
|
|
|
|
|
vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
|
|
|
|
|
|
vupklsh>: Use VXVA_MASK.
|
|
|
|
|
|
<vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
|
|
|
|
|
|
<mfvscr>: Use VXVAVB_MASK.
|
|
|
|
|
|
<mtvscr>: Use VXVDVA_MASK.
|
|
|
|
|
|
<vspltb>: Use VXUIMM4_MASK.
|
|
|
|
|
|
<vsplth>: Use VXUIMM3_MASK.
|
|
|
|
|
|
<vspltw>: Use VXUIMM2_MASK.
|
|
|
|
|
|
|
2012-08-24 08:14:40 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
|
|
|
|
|
|
|
2012-08-24 08:14:04 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
|
|
|
|
|
|
|
2012-08-24 08:13:24 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (neon_opcodes): Handle VMULL.P64.
|
|
|
|
|
|
|
2012-08-24 08:12:45 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (neon_opcodes): Add support for AES instructions.
|
|
|
|
|
|
|
2012-08-24 08:11:44 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (coprocessor_opcodes): Add support for HP/DP
|
|
|
|
|
|
conversions.
|
|
|
|
|
|
|
2012-08-24 08:11:13 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (coprocessor_opcodes): Add VRINT.
|
|
|
|
|
|
(neon_opcodes): Likewise.
|
|
|
|
|
|
|
2012-08-24 08:09:50 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (coprocessor_opcodes): Add support for new VCVT
|
|
|
|
|
|
variants.
|
|
|
|
|
|
(neon_opcodes): Likewise.
|
|
|
|
|
|
|
2012-08-24 08:07:36 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
|
|
|
|
|
|
(neon_opcodes): Likewise.
|
|
|
|
|
|
|
2012-08-24 08:06:36 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (coprocessor_opcodes): Add VSEL.
|
|
|
|
|
|
(print_insn_coprocessor): Add new %<>c bitfield format
|
|
|
|
|
|
specifier.
|
|
|
|
|
|
|
2012-08-24 08:03:39 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
|
|
|
|
|
|
(thumb32_opcodes): Likewise.
|
|
|
|
|
|
(print_arm_insn): Add support for %<>T formatter.
|
|
|
|
|
|
|
2012-08-24 08:02:51 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Add HLT.
|
|
|
|
|
|
(thumb_opcodes): Likewise.
|
|
|
|
|
|
|
2012-08-24 08:02:09 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb32_opcodes): Add DCPS instruction.
|
|
|
|
|
|
|
2012-08-24 08:01:18 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Add SEVL.
|
|
|
|
|
|
(thumb_opcodes): Likewise.
|
|
|
|
|
|
(thumb32_opcodes): Likewise.
|
|
|
|
|
|
|
2012-08-24 08:00:20 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (data_barrier_option): New function.
|
|
|
|
|
|
(print_insn_arm): Use data_barrier_option.
|
|
|
|
|
|
(print_insn_thumb32): Use data_barrier_option.
|
|
|
|
|
|
|
2012-08-24 07:59:05 +00:00
|
|
|
|
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (COND_UNCOND): New constant.
|
|
|
|
|
|
(print_insn_coprocessor): Add support for %u format specifier.
|
|
|
|
|
|
(print_insn_neon): Likewise.
|
|
|
|
|
|
|
2012-08-21 23:00:36 +00:00
|
|
|
|
2012-08-21 David S. Miller <davem@davemloft.net>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc-opc.c (4-argument crypto instructions): Fix encoding using
|
|
|
|
|
|
F3F4 macro.
|
|
|
|
|
|
|
2012-08-20 03:20:24 +00:00
|
|
|
|
2012-08-20 Edmar Wienskoski <edmar@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
|
|
|
|
|
|
vabsduh, vabsduw, mviwsplt.
|
|
|
|
|
|
|
2012-08-17 17:12:36 +00:00
|
|
|
|
2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
|
|
|
|
|
|
CPU_BTVER2_FLAGS.
|
|
|
|
|
|
|
2012-08-20 03:20:24 +00:00
|
|
|
|
* i386-opc.h: Update CpuPRFCHW comment.
|
2012-08-17 17:12:36 +00:00
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2012-08-17 14:33:27 +00:00
|
|
|
|
2012-08-17 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/uk.po: New Ukranian translation.
|
|
|
|
|
|
* configure.in (ALL_LINGUAS): Add uk.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2012-08-16 18:12:38 +00:00
|
|
|
|
2012-08-16 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
|
|
|
|
|
|
RBX for the third operand.
|
|
|
|
|
|
<"lswi">: Use RAX for second and NBI for the third operand.
|
|
|
|
|
|
|
2012-08-15 22:37:56 +00:00
|
|
|
|
2012-08-15 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
|
|
|
|
|
|
operands, so that data addresses can be corrected when not
|
|
|
|
|
|
ES-overridden.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
* rl78-dis.c (print_insn_rl78): Make order of modifiers
|
|
|
|
|
|
irrelevent. When the 'e' specifier is used on an operand and no
|
|
|
|
|
|
ES prefix is provided, adjust address to make it absolute.
|
|
|
|
|
|
|
2012-08-15 21:25:21 +00:00
|
|
|
|
2012-08-15 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
|
|
|
|
|
|
|
2012-08-15 15:33:25 +00:00
|
|
|
|
2012-08-15 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
|
|
|
|
|
|
|
2012-08-14 22:00:05 +00:00
|
|
|
|
2012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
|
|
|
|
|
|
macros, use local variables for info struct member accesses,
|
|
|
|
|
|
update the type of the variable used to hold the instruction
|
|
|
|
|
|
word.
|
|
|
|
|
|
(print_insn_mips, print_mips16_insn_arg): Likewise.
|
|
|
|
|
|
(print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
|
|
|
|
|
|
local variables for info struct member accesses.
|
|
|
|
|
|
(print_insn_micromips): Add GET_OP_S local macro.
|
|
|
|
|
|
(_print_insn_mips): Update the type of the variable used to hold
|
|
|
|
|
|
the instruction word.
|
|
|
|
|
|
|
2012-08-13 14:52:54 +00:00
|
|
|
|
2012-08-13 Ian Bolton <ian.bolton@arm.com>
|
2012-08-20 03:20:24 +00:00
|
|
|
|
Laurent Desnogues <laurent.desnogues@arm.com>
|
|
|
|
|
|
Jim MacArthur <jim.macarthur@arm.com>
|
|
|
|
|
|
Marcus Shawcroft <marcus.shawcroft@arm.com>
|
|
|
|
|
|
Nigel Stephens <nigel.stephens@arm.com>
|
|
|
|
|
|
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
|
|
|
|
|
|
Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
Sofiane Naci <sofiane.naci@arm.com>
|
|
|
|
|
|
Tejas Belagod <tejas.belagod@arm.com>
|
|
|
|
|
|
Yufeng Zhang <yufeng.zhang@arm.com>
|
2012-08-13 14:52:54 +00:00
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Add AArch64.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* aarch64-asm.c: New file.
|
|
|
|
|
|
* aarch64-asm.h: New file.
|
|
|
|
|
|
* aarch64-dis.c: New file.
|
|
|
|
|
|
* aarch64-dis.h: New file.
|
|
|
|
|
|
* aarch64-gen.c: New file.
|
|
|
|
|
|
* aarch64-opc.c: New file.
|
|
|
|
|
|
* aarch64-opc.h: New file.
|
|
|
|
|
|
* aarch64-tbl.h: New file.
|
|
|
|
|
|
* configure.in: Add AArch64.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* disassemble.c: Add AArch64.
|
|
|
|
|
|
* aarch64-asm-2.c: New file (automatically generated).
|
|
|
|
|
|
* aarch64-dis-2.c: New file (automatically generated).
|
|
|
|
|
|
* aarch64-opc-2.c: New file (automatically generated).
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2012-08-13 14:26:14 +00:00
|
|
|
|
2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* micromips-opc.c (micromips_opcodes): Update comment.
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
|
|
|
|
|
|
instructions for IOCT as appropriate.
|
|
|
|
|
|
* mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
|
|
|
|
|
|
opcode_is_member.
|
|
|
|
|
|
* configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
|
|
|
|
|
|
the result of a check for the -Wno-missing-field-initializers
|
|
|
|
|
|
GCC option.
|
|
|
|
|
|
* Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
|
|
|
|
|
|
(mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
|
|
|
|
|
|
compilation.
|
|
|
|
|
|
(mips16-opc.lo): Likewise.
|
|
|
|
|
|
(micromips-opc.lo): Likewise.
|
|
|
|
|
|
* aclocal.m4: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
|
2012-08-10 21:19:40 +00:00
|
|
|
|
2012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/14423
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
|
2012-08-09 14:46:44 +00:00
|
|
|
|
2012-08-09 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/vi.po: Updated Vietnamese translation.
|
|
|
|
|
|
|
2012-08-07 18:22:04 +00:00
|
|
|
|
2012-08-07 Roland McGrath <mcgrathr@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (reg_table): Fill out REG_0F0D table with
|
|
|
|
|
|
AMD-reserved cases as "prefetch".
|
|
|
|
|
|
(MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
|
|
|
|
|
|
(MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
|
|
|
|
|
|
(reg_table): Use those under REG_0F18.
|
|
|
|
|
|
(mod_table): Add those cases as "nop/reserved".
|
|
|
|
|
|
|
2012-08-07 16:51:34 +00:00
|
|
|
|
2012-08-07 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
|
|
|
|
|
|
|
2012-08-06 22:08:25 +00:00
|
|
|
|
2012-08-06 Roland McGrath <mcgrathr@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (print_insn): Print spaces between multiple excess
|
|
|
|
|
|
prefixes. Return actual number of excess prefixes consumed,
|
|
|
|
|
|
not always one.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
|
|
|
|
|
|
|
2012-08-06 20:19:34 +00:00
|
|
|
|
2012-08-06 Roland McGrath <mcgrathr@google.com>
|
|
|
|
|
|
Victor Khimenko <khim@google.com>
|
|
|
|
|
|
H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
|
|
|
|
|
|
(putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
|
|
|
|
|
|
(intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
|
|
|
|
|
|
(OP_E_register): Likewise.
|
|
|
|
|
|
(OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
|
|
|
|
|
|
|
2012-08-02 08:13:48 +00:00
|
|
|
|
2012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in: Formatting.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2012-08-01 00:41:35 +00:00
|
|
|
|
2012-08-01 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* h8300-dis.c: Fix printf arg warnings.
|
|
|
|
|
|
* i960-dis.c: Likewise.
|
|
|
|
|
|
* mips-dis.c: Likewise.
|
|
|
|
|
|
* pdp11-dis.c: Likewise.
|
|
|
|
|
|
* sh-dis.c: Likewise.
|
|
|
|
|
|
* v850-dis.c: Likewise.
|
|
|
|
|
|
* configure.in: Formatting.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
include/opcode/
* mips.h: Document microMIPS DSP ASE usage.
(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
microMIPS DSP ASE support.
(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
gas/
* config/tc-mips.c (macro_build) <'2'>: Handle microMIPS.
(macro) <M_BALIGN>: Update error handling.
(validate_micromips_insn) <'2', '3', '4', '5', '6'>: New cases.
<'7', '8', '0', '@', '^'>: Likewise.
(mips_ip) <'2', '3', '4', '5', '6', '7', '8'>: Handle microMIPS.
<'9'>: Fix formatting.
<'0', '@'>: Handle microMIPS.
<'^'>: New case.
gas/testsuite/
* gas/mips/micromips@mips32-dsp.d: New.
* gas/mips/micromips@mips32-dspr2.d: New.
* gas/mips/mips32-dsp.d: Remove -mips32r2.
* gas/mips/mips32-dspr2.d: Likewise.
* gas/mips/mips.exp: (mips_create_arch): Use -mips64r2
for micromips. Use run_dump_test_arches to run dsp tests.
opcodes/
* micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
(DSP_VOLA): Likewise.
(D32, D33): Likewise.
(micromips_opcodes): Add DSP ASE instructions.
* micromips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
<'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
2012-07-31 21:38:54 +00:00
|
|
|
|
2012-07-31 Chao-Ying Fu <fu@mips.com>
|
2012-08-20 03:20:24 +00:00
|
|
|
|
Catherine Moore <clm@codesourcery.com>
|
|
|
|
|
|
Maciej W. Rozycki <macro@codesourcery.com>
|
include/opcode/
* mips.h: Document microMIPS DSP ASE usage.
(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
microMIPS DSP ASE support.
(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
gas/
* config/tc-mips.c (macro_build) <'2'>: Handle microMIPS.
(macro) <M_BALIGN>: Update error handling.
(validate_micromips_insn) <'2', '3', '4', '5', '6'>: New cases.
<'7', '8', '0', '@', '^'>: Likewise.
(mips_ip) <'2', '3', '4', '5', '6', '7', '8'>: Handle microMIPS.
<'9'>: Fix formatting.
<'0', '@'>: Handle microMIPS.
<'^'>: New case.
gas/testsuite/
* gas/mips/micromips@mips32-dsp.d: New.
* gas/mips/micromips@mips32-dspr2.d: New.
* gas/mips/mips32-dsp.d: Remove -mips32r2.
* gas/mips/mips32-dspr2.d: Likewise.
* gas/mips/mips.exp: (mips_create_arch): Use -mips64r2
for micromips. Use run_dump_test_arches to run dsp tests.
opcodes/
* micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
(DSP_VOLA): Likewise.
(D32, D33): Likewise.
(micromips_opcodes): Add DSP ASE instructions.
* micromips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
<'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
2012-07-31 21:38:54 +00:00
|
|
|
|
|
|
|
|
|
|
* micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
|
|
|
|
|
|
(DSP_VOLA): Likewise.
|
|
|
|
|
|
(D32, D33): Likewise.
|
|
|
|
|
|
(micromips_opcodes): Add DSP ASE instructions.
|
2012-08-01 00:41:35 +00:00
|
|
|
|
* mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
|
include/opcode/
* mips.h: Document microMIPS DSP ASE usage.
(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
microMIPS DSP ASE support.
(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
gas/
* config/tc-mips.c (macro_build) <'2'>: Handle microMIPS.
(macro) <M_BALIGN>: Update error handling.
(validate_micromips_insn) <'2', '3', '4', '5', '6'>: New cases.
<'7', '8', '0', '@', '^'>: Likewise.
(mips_ip) <'2', '3', '4', '5', '6', '7', '8'>: Handle microMIPS.
<'9'>: Fix formatting.
<'0', '@'>: Handle microMIPS.
<'^'>: New case.
gas/testsuite/
* gas/mips/micromips@mips32-dsp.d: New.
* gas/mips/micromips@mips32-dspr2.d: New.
* gas/mips/mips32-dsp.d: Remove -mips32r2.
* gas/mips/mips32-dspr2.d: Likewise.
* gas/mips/mips.exp: (mips_create_arch): Use -mips64r2
for micromips. Use run_dump_test_arches to run dsp tests.
opcodes/
* micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
(DSP_VOLA): Likewise.
(D32, D33): Likewise.
(micromips_opcodes): Add DSP ASE instructions.
* micromips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
<'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
2012-07-31 21:38:54 +00:00
|
|
|
|
<'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
|
|
|
|
|
|
|
2012-07-31 07:38:42 +00:00
|
|
|
|
2012-07-31 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
|
|
|
|
|
|
instruction group. Mark as requiring AVX2.
|
|
|
|
|
|
* i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
2012-07-30 08:43:46 +00:00
|
|
|
|
2012-07-30 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/opcodes.pot: Updated template.
|
|
|
|
|
|
* po/es.po: Updated Spanish translation.
|
|
|
|
|
|
* po/fi.po: Updated Finnish translation.
|
|
|
|
|
|
|
2012-07-27 16:30:57 +00:00
|
|
|
|
2012-07-27 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in (BFD_VERSION): Run bfd/configure --version and
|
|
|
|
|
|
parse the output of that.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2012-07-25 13:08:55 +00:00
|
|
|
|
2012-07-25 James Lemke <jwlemke@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
|
|
|
|
|
|
|
2012-07-26 14:05:38 +00:00
|
|
|
|
2012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
|
|
|
|
|
|
Dr David Alan Gilbert <dave@treblig.org>
|
2012-07-24 12:56:47 +00:00
|
|
|
|
|
|
|
|
|
|
PR binutils/13135
|
|
|
|
|
|
* arm-dis.c: Add necessary casts for printing integer values.
|
|
|
|
|
|
Use %s when printing string values.
|
|
|
|
|
|
* hppa-dis.c: Likewise.
|
|
|
|
|
|
* m68k-dis.c: Likewise.
|
|
|
|
|
|
* microblaze-dis.c: Likewise.
|
|
|
|
|
|
* mips-dis.c: Likewise.
|
|
|
|
|
|
* sparc-dis.c: Likewise.
|
|
|
|
|
|
|
Use vex_len_table in xop_table
PR binutils/14355
* i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
(VEX_LEN_0FXOP_08_CD): Likewise.
(VEX_LEN_0FXOP_08_CE): Likewise.
(VEX_LEN_0FXOP_08_CF): Likewise.
(VEX_LEN_0FXOP_08_EC): Likewise.
(VEX_LEN_0FXOP_08_ED): Likewise.
(VEX_LEN_0FXOP_08_EE): Likewise.
(VEX_LEN_0FXOP_08_EF): Likewise.
(xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
vpcomub, vpcomuw, vpcomud, vpcomuq.
(vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
VEX_LEN_0FXOP_08_EF.
2012-07-19 13:41:03 +00:00
|
|
|
|
2012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/14355
|
|
|
|
|
|
* i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
|
|
|
|
|
|
(VEX_LEN_0FXOP_08_CD): Likewise.
|
|
|
|
|
|
(VEX_LEN_0FXOP_08_CE): Likewise.
|
|
|
|
|
|
(VEX_LEN_0FXOP_08_CF): Likewise.
|
|
|
|
|
|
(VEX_LEN_0FXOP_08_EC): Likewise.
|
|
|
|
|
|
(VEX_LEN_0FXOP_08_ED): Likewise.
|
|
|
|
|
|
(VEX_LEN_0FXOP_08_EE): Likewise.
|
|
|
|
|
|
(VEX_LEN_0FXOP_08_EF): Likewise.
|
|
|
|
|
|
(xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
|
|
|
|
|
|
vpcomub, vpcomuw, vpcomud, vpcomuq.
|
|
|
|
|
|
(vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
|
|
|
|
|
|
VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
|
|
|
|
|
|
VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
|
|
|
|
|
|
VEX_LEN_0FXOP_08_EF.
|
|
|
|
|
|
|
Implement RDRSEED, ADX and PRFCHW instructions
gas/
* config/tc-i386.c: Add ADX, RDSEED and PRFCHW asm directives.
* doc/c-i386.texi: Document the new directives.
gas/testsuite/
* gas/i386/i386.exp: Run adx, rdseed and prefetchw tests.
* gas/i386/x86-64-arch-2.s: Use prefetchw as 3dnow and Prfchw tests.
* gas/i386/arch-10.s: Likewise.
* gas/i386/arch-10-1.l: Changed correspondingly.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-lzcnt.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
* gas/i386/ilp32/x86-64-arch-2.d: Likewise.
* gas/i386/arch-10-prefetchw.d: New file.
* gas/i386/x86-64-arch-2-prefetchw.d: Likewise.
* gas/i386/rdseed.s: Likewise.
* gas/i386/rdseed.d: Likewise.
* gas/i386/rdseed-intel.d: Likewise.
* gas/i386/adx.s: Likewise.
* gas/i386/adx.d: Likewise.
* gas/i386/adx-intel.d: Likewise.
* gas/i386/x86-64-rdseed.s: Likewise.
* gas/i386/x86-64-rdseed.d: Likewise.
* gas/i386/x86-64-rdseed-intel.d: Likewise.
* gas/i386/x86-64-adx.s: Likewise.
* gas/i386/x86-64-adx.d: Likewise.
* gas/i386/x86-64-adx-intel.d: Likewise.
opcodes/
* i386-dis.c (PREFIX_0F38F6): New.
(prefix_table): Add adcx, adox instructions.
(three_byte_table): Use PREFIX_0F38F6.
(mod_table): Add rdseed instruction.
* i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
(cpu_flags): Likewise.
* i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
(i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
* i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
prefetchw.
* i386-tbl.h: Regenerate.
* i386-init.h: Likewise.
2012-07-16 12:58:29 +00:00
|
|
|
|
2012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (PREFIX_0F38F6): New.
|
|
|
|
|
|
(prefix_table): Add adcx, adox instructions.
|
|
|
|
|
|
(three_byte_table): Use PREFIX_0F38F6.
|
|
|
|
|
|
(mod_table): Add rdseed instruction.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
|
|
|
|
|
|
(cpu_flags): Likewise.
|
|
|
|
|
|
* i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
|
|
|
|
|
|
(i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
|
|
|
|
|
|
* i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
|
|
|
|
|
|
prefetchw.
|
|
|
|
|
|
* i386-tbl.h: Regenerate.
|
|
|
|
|
|
* i386-init.h: Likewise.
|
|
|
|
|
|
|
2012-07-05 08:18:43 +00:00
|
|
|
|
2012-07-05 Thomas Schwinge <thomas@codesourcery.com>
|
|
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|
|
|
|
2012-07-05 08:28:22 +00:00
|
|
|
|
* mips-dis.c: Remove gratuitous newline.
|
2012-07-05 08:18:43 +00:00
|
|
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|
|
2012-07-30 21:49:06 +00:00
|
|
|
|
2012-07-05 Sean Keys <skeys@ipdatasys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* xgate-dis.c: Removed an IF statement that will
|
2012-08-20 03:20:24 +00:00
|
|
|
|
always be false due to overlapping operand masks.
|
|
|
|
|
|
* xgate-opc.c: Corrected 'com' opcode entry and
|
|
|
|
|
|
fixed spacing.
|
2012-07-30 21:49:06 +00:00
|
|
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|
|
2012-07-02 18:12:28 +00:00
|
|
|
|
2012-07-02 Roland McGrath <mcgrathr@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add RepPrefixOk to nop.
|
|
|
|
|
|
* i386-tbl.h: Regenerate.
|
|
|
|
|
|
|
2012-06-28 14:36:01 +00:00
|
|
|
|
2012-06-28 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/vi.po: Updated Vietnamese translation.
|
|
|
|
|
|
|
2012-06-22 16:42:08 +00:00
|
|
|
|
2012-06-22 Roland McGrath <mcgrathr@google.com>
|
|
|
|
|
|
|
2012-06-22 21:54:06 +00:00
|
|
|
|
* i386-opc.tbl: Add RepPrefixOk to ret.
|
|
|
|
|
|
* i386-tbl.h: Regenerate.
|
|
|
|
|
|
|
2012-06-22 16:42:08 +00:00
|
|
|
|
* i386-opc.h (RepPrefixOk): New enum constant.
|
|
|
|
|
|
(i386_opcode_modifier): New bitfield 'repprefixok'.
|
|
|
|
|
|
* i386-gen.c (opcode_modifiers): Add RepPrefixOk.
|
|
|
|
|
|
* i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
|
|
|
|
|
|
instructions that have IsString.
|
|
|
|
|
|
* i386-tbl.h: Regenerate.
|
|
|
|
|
|
|
opcodes/
* ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
(iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
(lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
(stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
(dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
(dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
(stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
(tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
(stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
gas/testsuite/
* gas/ppc/e500mc.d: Update.
* gas/ppc/476.d: Update.
2012-06-11 08:20:43 +00:00
|
|
|
|
2012-06-11 Andreas Schwab <schwab@linux-m68k.org>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
|
|
|
|
|
|
(iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
|
|
|
|
|
|
(lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
|
|
|
|
|
|
(stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
|
|
|
|
|
|
(dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
|
|
|
|
|
|
(dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
|
|
|
|
|
|
(stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
|
|
|
|
|
|
(tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
|
|
|
|
|
|
(stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
|
|
|
|
|
|
|
2012-05-19 06:58:48 +00:00
|
|
|
|
2012-05-19 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
|
|
|
|
|
|
(get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
|
|
|
|
|
|
|
2012-05-18 01:59:38 +00:00
|
|
|
|
2012-05-18 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
2012-05-18 05:31:15 +00:00
|
|
|
|
* ia64-opc.c: Remove #include "ansidecl.h".
|
|
|
|
|
|
* z8kgen.c: Include sysdep.h first.
|
|
|
|
|
|
|
2012-05-18 01:59:38 +00:00
|
|
|
|
* arc-dis.c: Include sysdep.h first, remove some redundant includes.
|
|
|
|
|
|
* bfin-dis.c: Likewise.
|
|
|
|
|
|
* i860-dis.c: Likewise.
|
|
|
|
|
|
* ia64-dis.c: Likewise.
|
|
|
|
|
|
* ia64-gen.c: Likewise.
|
|
|
|
|
|
* m68hc11-dis.c: Likewise.
|
|
|
|
|
|
* mmix-dis.c: Likewise.
|
|
|
|
|
|
* msp430-dis.c: Likewise.
|
|
|
|
|
|
* or32-dis.c: Likewise.
|
|
|
|
|
|
* rl78-dis.c: Likewise.
|
|
|
|
|
|
* rx-dis.c: Likewise.
|
|
|
|
|
|
* tic4x-dis.c: Likewise.
|
|
|
|
|
|
* tilegx-opc.c: Likewise.
|
|
|
|
|
|
* tilepro-opc.c: Likewise.
|
|
|
|
|
|
* rx-decode.c: Regenerate.
|
|
|
|
|
|
|
2012-05-18 00:39:28 +00:00
|
|
|
|
2012-05-17 James Lemke <jwlemke@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
|
|
|
|
|
|
|
2012-05-18 00:30:47 +00:00
|
|
|
|
2012-05-17 James Lemke <jwlemke@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
|
|
|
|
|
|
|
2012-05-17 15:13:28 +00:00
|
|
|
|
2012-05-17 Daniel Richard G. <skunk@iskunk.org>
|
|
|
|
|
|
Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 14072
|
|
|
|
|
|
* configure.in: Add check that sysdep.h has been included before
|
|
|
|
|
|
any system header files.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* config.in: Regenerate.
|
|
|
|
|
|
* sysdep.h: Generate an error if included before config.h.
|
|
|
|
|
|
* alpha-opc.c: Include sysdep.h before any other header file.
|
|
|
|
|
|
* alpha-dis.c: Likewise.
|
|
|
|
|
|
* avr-dis.c: Likewise.
|
|
|
|
|
|
* cgen-opc.c: Likewise.
|
|
|
|
|
|
* cr16-dis.c: Likewise.
|
|
|
|
|
|
* cris-dis.c: Likewise.
|
|
|
|
|
|
* crx-dis.c: Likewise.
|
|
|
|
|
|
* d10v-dis.c: Likewise.
|
|
|
|
|
|
* d10v-opc.c: Likewise.
|
|
|
|
|
|
* d30v-dis.c: Likewise.
|
|
|
|
|
|
* d30v-opc.c: Likewise.
|
|
|
|
|
|
* h8500-dis.c: Likewise.
|
|
|
|
|
|
* i370-dis.c: Likewise.
|
|
|
|
|
|
* i370-opc.c: Likewise.
|
|
|
|
|
|
* m10200-dis.c: Likewise.
|
|
|
|
|
|
* m10300-dis.c: Likewise.
|
|
|
|
|
|
* micromips-opc.c: Likewise.
|
|
|
|
|
|
* mips-opc.c: Likewise.
|
|
|
|
|
|
* mips61-opc.c: Likewise.
|
|
|
|
|
|
* moxie-dis.c: Likewise.
|
|
|
|
|
|
* or32-opc.c: Likewise.
|
|
|
|
|
|
* pj-dis.c: Likewise.
|
|
|
|
|
|
* ppc-dis.c: Likewise.
|
|
|
|
|
|
* ppc-opc.c: Likewise.
|
|
|
|
|
|
* s390-dis.c: Likewise.
|
|
|
|
|
|
* sh-dis.c: Likewise.
|
|
|
|
|
|
* sh64-dis.c: Likewise.
|
|
|
|
|
|
* sparc-dis.c: Likewise.
|
|
|
|
|
|
* sparc-opc.c: Likewise.
|
|
|
|
|
|
* spu-dis.c: Likewise.
|
|
|
|
|
|
* tic30-dis.c: Likewise.
|
|
|
|
|
|
* tic54x-dis.c: Likewise.
|
|
|
|
|
|
* tic80-dis.c: Likewise.
|
|
|
|
|
|
* tic80-opc.c: Likewise.
|
|
|
|
|
|
* tilegx-dis.c: Likewise.
|
|
|
|
|
|
* tilepro-dis.c: Likewise.
|
|
|
|
|
|
* v850-dis.c: Likewise.
|
|
|
|
|
|
* v850-opc.c: Likewise.
|
|
|
|
|
|
* vax-dis.c: Likewise.
|
|
|
|
|
|
* w65-dis.c: Likewise.
|
|
|
|
|
|
* xgate-dis.c: Likewise.
|
|
|
|
|
|
* xtensa-dis.c: Likewise.
|
|
|
|
|
|
* rl78-decode.opc: Likewise.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
* rx-decode.opc: Likewise.
|
|
|
|
|
|
* rx-decode.c: Regenerate.
|
|
|
|
|
|
|
2012-05-17 02:24:50 +00:00
|
|
|
|
2012-05-17 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc_dis.c: Don't include elf/ppc.h.
|
|
|
|
|
|
|
2012-05-16 10:53:49 +00:00
|
|
|
|
2012-05-16 Meador Inge <meadori@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
|
|
|
|
|
|
to PUSH/POP {reg}.
|
|
|
|
|
|
|
2012-05-15 12:55:51 +00:00
|
|
|
|
2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
|
|
|
|
|
|
Stephane Carrez <stcarrez@nerim.fr>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in: Add S12X and XGATE co-processor support to m68hc11
|
|
|
|
|
|
target.
|
|
|
|
|
|
* disassemble.c: Likewise.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* m68hc11-dis.c: Make objdump output more consistent, use hex
|
|
|
|
|
|
instead of decimal and use 0x prefix for hex.
|
|
|
|
|
|
* m68hc11-opc.c: Add S12X and XGATE opcodes.
|
|
|
|
|
|
|
Add support for PowerPC VLE.
2012-05-14 Catherine Moore <clm@codesourcery.com>
* NEWS: Mention PowerPC VLE port.
2012-05-14 James Lemke <jwlemke@codesourcery.com>
Catherine Moore <clm@codesourcery.com>
bfd/
* bfd.c (bfd_lookup_section_flags): Add section parm.
* ecoff.c (bfd_debug_section): Remove flag_info initializer.
* elf-bfd.h (bfd_elf_section_data): Move in section_flag_info.
(bfd_elf_lookup_section_flags): Add section parm.
* elf32-ppc.c (is_ppc_vle): New function.
(ppc_elf_modify_segment_map): New function.
(elf_backend_modify_segment_map): Define.
(has_vle_insns): New define.
* elf32-ppc.h (ppc_elf_modify_segment_map): Declare.
* elflink.c (bfd_elf_lookup_section_flags): Add return value & parm.
Move in logic to omit / include a section.
* libbfd-in.h (bfd_link_info): Add section parm.
(bfd_generic_lookup_section_flags): Likewise.
* reloc.c (bfd_generic_lookup_section_flags): Likewise.
* section.c (bfd_section): Move out section_flag_info.
(BFD_FAKE_SECTION): Remove flag_info initializer.
* targets.c (_bfd_lookup_section_flags): Add section parm.
2012-05-14 Catherine Moore <clm@codesourcery.com>
bfd/
* archures.c (bfd_mach_ppc_vle): New.
* bfd-in2.h: Regenerated.
* cpu-powerpc.c (bfd_powerpc_archs): New entry for vle.
* elf32-ppc.c (split16_format_type): New enumeration.
(ppc_elf_vle_split16): New function.
(HOWTO): Add entries for R_PPC_VLE relocations.
(ppc_elf_reloc_type_lookup): Handle PPC_VLE relocations.
(ppc_elf_section_flags): New function.
(ppc_elf_lookup_section_flags): New function.
(ppc_elf_section_processing): New function.
(ppc_elf_check_relocs): Handle PPC_VLE relocations.
(ppc_elf_relocation_section): Likewise.
(elf_backend_lookup_section_flags_hook): Define.
(elf_backend_section_flags): Define.
(elf_backend_section_processing): Define.
* elf32-ppc.h (ppc_elf_section_processing): Declare.
* libbfd.h: Regenerated.
* reloc.c (BFD_RELOC_PPC_VLE_REL8, BFD_RELOC_PPC_VLE_REL15,
BFD_RELOC_PPC_VLE_REL24, BFD_RELOC_PPC_VLE_LO16A,
BFD_RELOC_PPC_VLE_LO16D, BFD_RELOC_PPC_VLE_HI16A,
BFD_RELOC_PPC_VLE_HI16D, BFD_RELOC_PPC_VLE_HA16A,
BFD_RELOC_PPC_VLE_HA16D, BFD_RELOC_PPC_VLE_SDA21,
BFD_RELOC_PPC_VLE_SDA21_LO, BFD_RELOC_PPC_VLE_SDAREL_LO16A,
BFD_RELOC_PPC_VLE_SDAREL_LO16D, BFD_RELOC_PPC_VLE_SDAREL_HI16A,
BFD_RELOC_PPC_VLE_SDAREL_HI16D, BFD_RELOC_PPC_VLE_SDAREL_HA16A,
BFD_RELOC_PPC_VLE_SDAREL_HA16D): New bfd relocations.
2012-05-14 James Lemke <jwlemke@codesourcery.com>
gas/
* config/tc-ppc.c (insn_validate): New func of existing code to call..
(ppc_setup_opcodes): ..from 2 places here.
Revise for second (VLE) opcode table.
Add #ifdef'd code to print opcode tables.
2012-05-14 James Lemke <jwlemke@codesourcery.com>
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Allow out-of-order
for the VLE conditional branches.
2012-05-14 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Rhonda Wittels <rhonda@codesourcery.com>
gas/
* config/tc-ppc.c (PPC_VLE_SPLIT16A): New macro.
(PPC_VLE_SPLIT16D): New macro.
(PPC_VLE_LO16A): New macro.
(PPC_VLE_LO16D): New macro.
(PPC_VLE_HI16A): New macro.
(PPC_VLE_HI16D): New macro.
(PPC_VLE_HA16A): New macro.
(PPC_VLE_HA16D): New macro.
(PPC_APUINFO_VLE): New definition.
(md_chars_to_number): New function.
(md_parse_option): Check for combinations of little
endian and -mvle.
(md_show_usage): Document -mvle.
(ppc_arch): Recognize VLE.
(ppc_mach): Recognize bfd_mach_ppc_vle.
(ppc_setup_opcodes): Print the opcode table if
* config/tc-ppc.h (ppc_frag_check): Declare.
* doc/c-ppc.texi: Document -mvle.
* NEWS: Mention PowerPC VLE port.
2012-05-14 Catherine Moore <clm@codesourcery.com>
gas/
* config/tc-ppc.h (ppc_dw2_line_min_insn_length): Declare.
(DWARF2_LINE_MIN_INSN_LENGTH): Redefine.
* config/tc-ppc.c (ppc_dw2_line_min_insn_length): New.
* dwarf2dbg.c (scale_addr_delta): Handle values of 1
for DWARF2_LINE_MIN_INSN_LENGTH.
2012-05-14 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Rhonda Wittels <rhonda@codesourcery.com>
gas/testsuite/
* gas/ppc/ppc.exp: Run new tests.
* gas/ppc/vle-reloc.d: New test.
* gas/ppc/vle-reloc.s: New test.
* gas/ppc/vle-simple-1.d: New test.
* gas/ppc/vle-simple-1.s: New test.
* gas/ppc/vle-simple-2.d: New test.
* gas/ppc/vle-simple-2.s: New test.
* gas/ppc/vle-simple-3.d: New test.
* gas/ppc/vle-simple-3.s: New test.
* gas/ppc/vle-simple-4.d: New test.
* gas/ppc/vle-simple-4.s: New test.
* gas/ppc/vle-simple-5.d: New test.
* gas/ppc/vle-simple-5.s: New test.
* gas/ppc/vle-simple-6.d: New test.
* gas/ppc/vle-simple-6.s: New test.
* gas/ppc/vle.d: New test.
* gas/ppc/vle.s: New test.
2012-05-14 James Lemke <jwlemke@codesourcery.com>
include/elf/
* ppc.h (SEC_PPC_VLE): Remove.
2012-05-14 Catherine Moore <clm@codesourcery.com>
James Lemke <jwlemke@codesourcery.com>
include/elf/
* ppc.h (R_PPC_VLE_REL8): New reloction.
(R_PPC_VLE_REL15): Likewise.
(R_PPC_VLE_REL24): Likewise.
(R_PPC_VLE_LO16A): Likewise.
(R_PPC_VLE_LO16D): Likewise.
(R_PPC_VLE_HI16A): Likewise.
(R_PPC_VLE_HI16D): Likewise.
(R_PPC_VLE_HA16A): Likewise.
(R_PPC_VLE_HA16D): Likewise.
(R_PPC_VLE_SDA21): Likewise.
(R_PPC_VLE_SDA21_LO): Likewise.
(R_PPC_VLE_SDAREL_LO16A): Likewise.
(R_PPC_VLE_SDAREL_LO16D): Likewise.
(R_PPC_VLE_SDAREL_HI16A): Likewise.
(R_PPC_VLE_SDAREL_HI16D): Likewise.
(R_PPC_VLE_SDAREL_HA16A): Likewise.
(R_PPC_VLE_SDAREL_HA16D): Likewise.
(SEC_PPC_VLE): Remove.
(PF_PPC_VLE): New program header flag.
(SHF_PPC_VLE): New section header flag.
(vle_opcodes, vle_num_opcodes): New.
(VLE_OP): New macro.
(VLE_OP_TO_SEG): New macro.
2012-05-14 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Rhonda Wittels <rhonda@codesourcery.com>
include/opcode/
* ppc.h (PPC_OPCODE_VLE): New definition.
(PPC_OP_SA): New macro.
(PPC_OP_SE_VLE): New macro.
(PPC_OP): Use a variable shift amount.
(powerpc_operand): Update comments.
(PPC_OPSHIFT_INV): New macro.
(PPC_OPERAND_CR): Replace with...
(PPC_OPERAND_CR_BIT): ...this and
(PPC_OPERAND_CR_REG): ...this.
2012-05-14 James Lemke <jwlemke@codesourcery.com>
ld/
* ldlang.c (walk_wild_consider_section): Don't copy section_flag_list.
Pass it to callback.
(walk_wild_section_general): Pass section_flag_list to callback.
(lang_add_section): Add sflag_list parm.
Move out logic to keep / omit a section & call bfd_lookup_section_flags.
(output_section_callback_fast): Add sflag_list parm.
Add new parm to lang_add_section calls.
(output_section_callback): Likewise.
(check_section_callback): Add sflag_list parm.
(lang_place_orphans): Add new parm to lang_add_section calls.
(gc_section_callback): Add sflag_list parm.
(find_relro_section_callback): Likewise.
* ldlang.h (callback_t): Add flag_info parm.
(lang_add_section): Add sflag_list parm.
* emultempl/armelf.em (elf32_arm_add_stub_section):
Add lang_add_section parm.
* emultempl/beos.em (gld*_place_orphan): Likewise.
* emultempl/elf32.em (gld*_place_orphan): Likewise.
* emultempl/hppaelf.em (hppaelf_add_stub_section): Likewise.
* emultempl/m68hc1xelf.em (m68hc11elf_add_stub_section): Likewise.
* emultempl/mipself.em (mips_add_stub_section): Likewise.
* emultempl/mmo.em (mmo_place_orphan): Likewise.
* emultempl/pe.em (gld_*_place_orphan): Likewise.
* emultempl/pep.em (gld_*_place_orphan): Likewise.
* emultempl/ppc64elf.em (ppc_add_stub_section): Likewise.
* emultempl/spuelf.em (spu_place_special_section): Likewise.
* emultempl/vms.em (vms_place_orphan): Likewise.
2012-05-14 James Lemke <jwlemke@codesourcery.com>
ld/testsuite/
* ld-powerpc/powerpc.exp: Create ppceabitests.
* ld-powerpc/vle-multiseg.s: New.
* ld-powerpc/vle-multiseg-1.d: New.
* ld-powerpc/vle-multiseg-1.ld: New.
* ld-powerpc/vle-multiseg-2.d: New.
* ld-powerpc/vle-multiseg-2.ld: New.
* ld-powerpc/vle-multiseg-3.d: New.
* ld-powerpc/vle-multiseg-3.ld: New.
* ld-powerpc/vle-multiseg-4.d: New.
* ld-powerpc/vle-multiseg-4.ld: New.
* ld-powerpc/vle-multiseg-5.d: New.
* ld-powerpc/vle-multiseg-5.ld: New.
* ld-powerpc/vle-multiseg-6.d: New.
* ld-powerpc/vle-multiseg-6.ld: New.
* ld-powerpc/vle-multiseg-6a.s: New.
* ld-powerpc/vle-multiseg-6b.s: New.
* ld-powerpc/vle-multiseg-6c.s: New.
* ld-powerpc/vle-multiseg-6d.s: New.
* ld-powerpc/powerpc.exp: Run new tests.
2012-05-14 Catherine Moore <clm@codesourcery.com>
ld/
* NEWS: Mention PowerPC VLE port.
2012-05-14 Catherine Moore <clm@codesourcery.com>
ld/testsuite/
* ld-powerpc/apuinfo.rd: Update for VLE.
* ld-powerpc/vle-reloc-1.d: New.
* ld-powerpc/vle-reloc-1.s: New.
* ld-powerpc/vle-reloc-2.d: New.
* ld-powerpc/vle-reloc-2.s: New.
* ld-powerpc/vle-reloc-3.d: New.
* ld-powerpc/vle-reloc-3.s: New.
* ld-powerpc/vle-reloc-def-1.s: New.
* ld-powerpc/vle-reloc-def-2.s: New.
* ld-powerpc/vle-reloc-def-3.s: New.
2012-05-14 James Lemke <jwlemke@codesourcery.com>
opcodes/
* ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
(PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
(vle_opcd_indices): New array.
(lookup_vle): New function.
(disassemble_init_powerpc): Revise for second (VLE) opcode table.
(print_insn_powerpc): Likewise.
* ppc-opc.c: Likewise.
2012-05-14 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Rhonda Wittels <rhonda@codesourcery.com>
Nathan Froyd <froydnj@codesourcery.com>
opcodes/
* ppc-opc.c (insert_arx, extract_arx): New functions.
(insert_ary, extract_ary): New functions.
(insert_li20, extract_li20): New functions.
(insert_rx, extract_rx): New functions.
(insert_ry, extract_ry): New functions.
(insert_sci8, extract_sci8): New functions.
(insert_sci8n, extract_sci8n): New functions.
(insert_sd4h, extract_sd4h): New functions.
(insert_sd4w, extract_sd4w): New functions.
(insert_vlesi, extract_vlesi): New functions.
(insert_vlensi, extract_vlensi): New functions.
(insert_vleui, extract_vleui): New functions.
(insert_vleil, extract_vleil): New functions.
(BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
(BI16, BI32, BO32, B8): New.
(B15, B24, CRD32, CRS): New.
(CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
(DB, IMM20, RD, Rx, ARX, RY, RZ): New.
(ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
(SH6_MASK): Use PPC_OPSHIFT_INV.
(SI8, UI5, OIMM5, UI7, BO16): New.
(VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
(XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
(ALLOW8_SPRG): New.
(insert_sprg, extract_sprg): Check ALLOW8_SPRG.
(OPVUP, OPVUP_MASK OPVUP): New
(BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
(EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
(BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
(BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
(IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
(IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
(SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
(SE_IM5, SE_IM5_MASK): New.
(SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
(EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
(BO32DNZ, BO32DZ): New.
(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
(PPCVLE): New.
(powerpc_opcodes): Add new VLE instructions. Update existing
instruction to include PPCVLE if supported.
* ppc-dis.c (ppc_opts): Add vle entry.
(get_powerpc_dialect): New function.
(powerpc_init_dialect): VLE support.
(print_insn_big_powerpc): Call get_powerpc_dialect.
(print_insn_little_powerpc): Likewise.
(operand_value_powerpc): Handle negative shift counts.
(print_insn_powerpc): Handle 2-byte instruction lengths.
2012-05-14 19:45:30 +00:00
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2012-05-14 James Lemke <jwlemke@codesourcery.com>
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* ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
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(PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
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(vle_opcd_indices): New array.
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(lookup_vle): New function.
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(disassemble_init_powerpc): Revise for second (VLE) opcode table.
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(print_insn_powerpc): Likewise.
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* ppc-opc.c: Likewise.
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2012-05-14 Catherine Moore <clm@codesourcery.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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Rhonda Wittels <rhonda@codesourcery.com>
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Nathan Froyd <froydnj@codesourcery.com>
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* ppc-opc.c (insert_arx, extract_arx): New functions.
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(insert_ary, extract_ary): New functions.
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(insert_li20, extract_li20): New functions.
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(insert_rx, extract_rx): New functions.
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(insert_ry, extract_ry): New functions.
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(insert_sci8, extract_sci8): New functions.
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(insert_sci8n, extract_sci8n): New functions.
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(insert_sd4h, extract_sd4h): New functions.
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(insert_sd4w, extract_sd4w): New functions.
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(insert_vlesi, extract_vlesi): New functions.
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(insert_vlensi, extract_vlensi): New functions.
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(insert_vleui, extract_vleui): New functions.
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(insert_vleil, extract_vleil): New functions.
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(BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
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(BI16, BI32, BO32, B8): New.
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(B15, B24, CRD32, CRS): New.
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(CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
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(DB, IMM20, RD, Rx, ARX, RY, RZ): New.
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(ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
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(SH6_MASK): Use PPC_OPSHIFT_INV.
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(SI8, UI5, OIMM5, UI7, BO16): New.
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(VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
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(XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
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(ALLOW8_SPRG): New.
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(insert_sprg, extract_sprg): Check ALLOW8_SPRG.
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(OPVUP, OPVUP_MASK OPVUP): New
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(BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
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(EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
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(BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
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(BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
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(IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
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(IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
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(SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
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(SE_IM5, SE_IM5_MASK): New.
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(SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
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(EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
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(BO32DNZ, BO32DZ): New.
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(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
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(PPCVLE): New.
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(powerpc_opcodes): Add new VLE instructions. Update existing
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instruction to include PPCVLE if supported.
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* ppc-dis.c (ppc_opts): Add vle entry.
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(get_powerpc_dialect): New function.
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(powerpc_init_dialect): VLE support.
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(print_insn_big_powerpc): Call get_powerpc_dialect.
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(print_insn_little_powerpc): Likewise.
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(operand_value_powerpc): Handle negative shift counts.
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(print_insn_powerpc): Handle 2-byte instruction lengths.
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2012-05-11 14:25:30 +00:00
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2012-05-11 Daniel Richard G. <skunk@iskunk.org>
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PR binutils/14028
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* configure.in: Invoke ACX_HEADER_STRING.
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* configure: Regenerate.
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* config.in: Regenerate.
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* sysdep.h: If STRINGS_WITH_STRING is defined then include both
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string.h and strings.h.
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2012-05-11 09:41:21 +00:00
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2012-05-11 Nick Clifton <nickc@redhat.com>
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PR binutils/14006
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* arm-dis.c (print_insn): Fix detection of instruction mode in
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files containing multiple executable sections.
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2012-05-03 13:12:08 +00:00
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2012-05-03 Sean Keys <skeys@ipdatasys.com>
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* Makefile.in, configure: regenerate
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* disassemble.c (disassembler): Recognize ARCH_XGATE.
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* xgate-dis.c (read_memory, print_insn, print_insn_xgate):
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New functions.
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* configure.in: Recognize xgate.
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* xgate-dis.c, xgate-opc.c: New files for support of xgate
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* Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
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and opcode generation for xgate.
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2012-04-30 22:04:22 +00:00
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2012-04-30 DJ Delorie <dj@redhat.com>
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* rx-decode.opc (MOV): Do not sign-extend immediates which are
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already the maximum bit size.
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* rx-decode.c: Regenerate.
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Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 18:01:35 +00:00
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2012-04-27 David S. Miller <davem@davemloft.net>
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2012-04-27 20:43:35 +00:00
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* sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
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* sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
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2012-04-27 18:04:00 +00:00
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* sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
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* sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
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2012-04-27 18:03:13 +00:00
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* sparc-opc.c (CBCOND): New define.
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(CBCOND_XCC): Likewise.
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(cbcond): New helper macro.
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(sparc_opcodes): Add compare-and-branch instructions.
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2012-04-27 18:02:35 +00:00
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* sparc-dis.c (print_insn_sparc): Handle ')'.
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* sparc-opc.c (sparc_opcodes): Add crypto instructions.
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Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 18:01:35 +00:00
|
|
|
|
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
|
|
|
|
|
|
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
|
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|
2012-04-12 16:26:06 +00:00
|
|
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|
2012-04-12 David S. Miller <davem@davemloft.net>
|
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* sparc-dis.c (X_DISP10): Define.
|
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|
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|
(print_insn_sparc): Handle '='.
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2012-04-01 04:15:43 +00:00
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2012-04-01 Mike Frysinger <vapier@gentoo.org>
|
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* bfin-dis.c (fmtconst): Replace decimal handling with a single
|
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|
sprintf call and the '*' field width.
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2012-03-24 01:09:28 +00:00
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2012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
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* mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
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2012-03-16 12:14:32 +00:00
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2012-03-16 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
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(powerpc_opcd_indices): Bump array size.
|
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(disassemble_init_powerpc): Set powerpc_opcd_indices entries
|
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corresponding to unused opcodes to following entry.
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(lookup_powerpc): New function, extracted and optimised from..
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(print_insn_powerpc): ..here.
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2012-03-15 12:58:48 +00:00
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2012-03-15 Alan Modra <amodra@gmail.com>
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|
James Lemke <jwlemke@codesourcery.com>
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* disassemble.c (disassemble_init_for_target): Handle ppc init.
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* ppc-dis.c (private): New var.
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(powerpc_init_dialect): Don't return calloc failure, instead use
|
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|
private.
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(PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
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|
(powerpc_opcd_indices): New array.
|
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(disassemble_init_powerpc): New function.
|
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(print_insn_big_powerpc): Don't init dialect here.
|
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(print_insn_little_powerpc): Likewise.
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(print_insn_powerpc): Start search using powerpc_opcd_indices.
|
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include/opcode/
* ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
opcodes/
* ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
* ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
(PPCVEC2, PPCTMR, E6500): New short names.
(powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
optional operands on sync instruction for E6500 target.
bfd/
* archures.c: Add bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500.
* bfd-in2.h: Regenerate.
* cpu-powerpc.c (bfd_powerpc_archs): Add entryies for
bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500.
gas/
* config/tc-ppc.c (md_show_usage): Document -me5500 and -me6500.
(ppc_handle_align): Add termination nop opcode for e500mc family.
* doc/as.texinfo: Document options -me5500 and -me6500.
* doc/c-ppc.texi: Likewise.
gas/testsuite/
* gas/ppc/e500mc64_nop.s: New test case for e500mc family
termination nops.
* gas/ppc/e500mc64_nop.d: Likewise.
* gas/ppc/e5500_nop.s: Likewise.
* gas/ppc/e5500_nop.d: Likewise.
* gas/ppc/e6500_nop.s: Likewise.
* gas/ppc/e6500_nop.d: Likewise.
* gas/ppc/e6500.s: New.
* gas/ppc/e6500.d: Likewise.
* gas/ppc/ppc.exp: Run e6500, e500mc64_nop, e5500_nop, and e6500_nop.
2012-03-09 23:39:06 +00:00
|
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|
2012-03-10 Edmar Wienskoski <edmar@freescale.com>
|
|
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|
|
|
|
|
|
|
|
* ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
|
|
|
|
|
|
* ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
|
|
|
|
|
|
(PPCVEC2, PPCTMR, E6500): New short names.
|
|
|
|
|
|
(powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
|
|
|
|
|
|
mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
|
|
|
|
|
|
lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
|
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|
|
lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
|
|
|
|
|
|
lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
|
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|
|
optional operands on sync instruction for E6500 target.
|
|
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|
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2012-03-08 17:22:18 +00:00
|
|
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|
2012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
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|
|
* s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
|
|
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|
2012-02-27 06:57:57 +00:00
|
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|
2012-02-27 Alan Modra <amodra@gmail.com>
|
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|
* mt-dis.c: Regenerate.
|
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|
2012-02-27 06:55:39 +00:00
|
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|
2012-02-27 Alan Modra <amodra@gmail.com>
|
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|
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|
|
* v850-opc.c (extract_v8): Rearrange to make it obvious this
|
|
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|
|
is the inverse of corresponding insert function.
|
|
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|
|
(extract_d22, extract_u9, extract_r4): Likewise.
|
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|
|
(extract_d9): Correct sign extension.
|
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|
(extract_d16_15): Don't assume "long" is 32 bits, and don't
|
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|
rely on implementation defined behaviour for shift right of
|
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|
signed types.
|
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|
(extract_d16_16, extract_d17_16, extract_i9): Likewise.
|
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|
(extract_d23): Likewise, and correct mask.
|
|
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|
2012-02-27 06:37:40 +00:00
|
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|
2012-02-27 Alan Modra <amodra@gmail.com>
|
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|
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|
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|
|
* crx-dis.c (print_arg): Mask constant to 32 bits.
|
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|
* crx-opc.c (cst4_map): Use int array.
|
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|
2012-02-27 06:31:57 +00:00
|
|
|
|
2012-02-27 Alan Modra <amodra@gmail.com>
|
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|
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|
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|
|
* arc-dis.c (BITS): Don't use shifts to mask off bits.
|
|
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|
|
(FIELDD): Sign extend with xor,sub.
|
|
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|
|
Improve TLS support on TILE-Gx/TILEPro:
- Add support for TLS LE references.
- Support linker optimization of TLS references.
- Delete relocations of GOT/tp relative offsets beyond 32-bits.
This brings binutils in line with the support expected in gcc 4.7, for
TILE-Gx/TILEPro.
bfd/
* reloc.c: Add BFD_RELOC_TILEPRO_TLS_GD_CALL,
BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD,
BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD,
BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD,
BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD,
BFD_RELOC_TILEPRO_TLS_IE_LOAD, BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE,
BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE,
BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO,
BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO,
BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI,
BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI,
BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA,
BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA,
BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE,
BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE,
BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE,
BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE,
BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE,
BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE,
BFD_RELOC_TILEGX_TLS_GD_CALL, BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD,
BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD,
BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD,
BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD, BFD_RELOC_TILEGX_TLS_IE_LOAD,
BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD,
BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD,
BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD, BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD.
Delete BFD_RELOC_TILEGX_IMM16_X0_HW1_GOT,
BFD_RELOC_TILEGX_IMM16_X1_HW1_GOT,
BFD_RELOC_TILEGX_IMM16_X0_HW2_GOT,
BFD_RELOC_TILEGX_IMM16_X1_HW2_GOT,
BFD_RELOC_TILEGX_IMM16_X0_HW3_GOT,
BFD_RELOC_TILEGX_IMM16_X1_HW3_GOT,
BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_GOT,
BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_GOT,
BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_IE.
* elf32-tilepro.c (tilepro_elf_howto_table): Update tilepro
relocations.
(tilepro_reloc_map): Ditto.
(tilepro_info_to_howto_rela): Ditto.
(reloc_to_create_func): Ditto.
(tilepro_tls_translate_to_le): New.
(tilepro_tls_translate_to_ie): New.
(tilepro_elf_tls_transition): New.
(tilepro_elf_check_relocs): Handle new tls relocations.
(tilepro_elf_gc_sweep_hook): Ditto.
(allocate_dynrelocs): Ditto.
(tilepro_elf_relocate_section): Ditto.
(tilepro_replace_insn): New.
(insn_mask_X1): New.
(insn_mask_X0_no_dest_no_srca): New
(insn_mask_X1_no_dest_no_srca): New
(insn_mask_Y0_no_dest_no_srca): New
(insn_mask_Y1_no_dest_no_srca): New
(srca_mask_X0): New
(srca_mask_X1): New
(insn_tls_le_move_X1): New
(insn_tls_le_move_zero_X0X1): New
(insn_tls_ie_lw_X1): New
(insn_tls_ie_add_X0X1): New
(insn_tls_ie_add_Y0Y1): New
(insn_tls_gd_add_X0X1): New
(insn_tls_gd_add_Y0Y1): New
* elfxx-tilegx.c (tilegx_elf_howto_table): Update tilegx
relocations.
(tilegx_reloc_map): Ditto.
(tilegx_info_to_howto_rela): Ditto.
(reloc_to_create_func): Ditto.
(tilegx_elf_link_hash_table): New field disable_le_transition.
(tilegx_tls_translate_to_le): New.
(tilegx_tls_translate_to_ie): New.
(tilegx_elf_tls_transition): New.
(tilegx_elf_check_relocs): Handle new tls relocations.
(tilegx_elf_gc_sweep_hook): Ditto.
(allocate_dynrelocs): Ditto.
(tilegx_elf_relocate_section): Ditto.
(tilegx_copy_bits): New.
(tilegx_replace_insn): New.
(insn_mask_X1): New.
(insn_mask_X0_no_dest_no_srca): New.
(insn_mask_X1_no_dest_no_srca): New.
(insn_mask_Y0_no_dest_no_srca): New.
(insn_mask_Y1_no_dest_no_srca): New.
(insn_mask_X0_no_operand): New.
(insn_mask_X1_no_operand): New.
(insn_mask_Y0_no_operand): New.
(insn_mask_Y1_no_operand): New.
(insn_tls_ie_ld_X1): New.
(insn_tls_ie_ld4s_X1): New.
(insn_tls_ie_add_X0X1): New.
(insn_tls_ie_add_Y0Y1): New.
(insn_tls_ie_addx_X0X1): New.
(insn_tls_ie_addx_Y0Y1): New.
(insn_tls_gd_add_X0X1): New.
(insn_tls_gd_add_Y0Y1): New.
(insn_move_X0X1): New.
(insn_move_Y0Y1): New.
(insn_add_X0X1): New.
(insn_add_Y0Y1): New.
(insn_addx_X0X1): New.
(insn_addx_Y0Y1): New.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* tc-tilepro.c (O_tls_le): Define operator.
(O_tls_le_lo16): Ditto.
(O_tls_le_hi16): Ditto.
(O_tls_le_ha16): Ditto.
(O_tls_gd_call): Ditto.
(O_tls_gd_add): Ditto.
(O_tls_ie_load): Ditto.
(md_begin): Delete old operators; handle new operators.
(emit_tilepro_instruction): Ditto.
(md_apply_fix): Ditto.
* tc-tilegx.c (O_hw1_got): Delete operator.
(O_hw2_got): Ditto.
(O_hw3_got): Ditto.
(O_hw2_last_got): Ditto.
(O_hw1_tls_gd): Ditto.
(O_hw2_tls_gd): Ditto.
(O_hw3_tls_gd): Ditto.
(O_hw2_last_tls_gd): Ditto.
(O_hw1_tls_ie): Ditto.
(O_hw2_tls_ie): Ditto.
(O_hw3_tls_ie): Ditto.
(O_hw2_last_tls_ie): Ditto.
(O_hw0_tls_le): Define operator.
(O_hw0_last_tls_le): Ditto.
(O_hw1_last_tls_le): Ditto.
(O_tls_gd_call): Ditto.
(O_tls_gd_add): Ditto.
(O_tls_ie_load): Ditto.
(O_tls_add): Ditto.
(md_begin): Delete old operators; handle new operators.
(emit_tilegx_instruction): Ditto.
(md_apply_fix): Ditto.
* doc/c-tilegx.texi: Delete old operators; document new operators.
* doc/c-tilepro.texi: Ditto.
include/elf/
* tilegx.h (R_TILEGX_IMM16_X0_HW1_GOT): Delete.
(R_TILEGX_IMM16_X1_HW1_GOT): Ditto.
(R_TILEGX_IMM16_X0_HW2_GOT): Ditto.
(R_TILEGX_IMM16_X1_HW2_GOT): Ditto.
(R_TILEGX_IMM16_X0_HW3_GOT): Ditto.
(R_TILEGX_IMM16_X1_HW3_GOT): Ditto.
(R_TILEGX_IMM16_X0_HW2_LAST_GOT): Ditto.
(R_TILEGX_IMM16_X1_HW2_LAST_GOT): Ditto.
(R_TILEGX_IMM16_X0_HW1_TLS_GD): Ditto.
(R_TILEGX_IMM16_X1_HW1_TLS_GD): Ditto.
(R_TILEGX_IMM16_X0_HW2_TLS_GD): Ditto.
(R_TILEGX_IMM16_X1_HW2_TLS_GD): Ditto.
(R_TILEGX_IMM16_X0_HW3_TLS_GD): Ditto.
(R_TILEGX_IMM16_X1_HW3_TLS_GD): Ditto.
(R_TILEGX_IMM16_X0_HW2_LAST_TLS_GD): Ditto.
(R_TILEGX_IMM16_X1_HW2_LAST_TLS_GD): Ditto.
(R_TILEGX_IMM16_X0_HW1_TLS_IE): Ditto.
(R_TILEGX_IMM16_X1_HW1_TLS_IE): Ditto.
(R_TILEGX_IMM16_X0_HW2_TLS_IE): Ditto.
(R_TILEGX_IMM16_X1_HW2_TLS_IE): Ditto.
(R_TILEGX_IMM16_X0_HW3_TLS_IE): Ditto.
(R_TILEGX_IMM16_X1_HW3_TLS_IE): Ditto.
(R_TILEGX_IMM16_X0_HW2_LAST_TLS_IE): Ditto.
(R_TILEGX_IMM16_X1_HW2_LAST_TLS_IE): Ditto.
(R_TILEGX_IMM16_X0_HW0_TLS_LE): New relocation.
(R_TILEGX_IMM16_X1_HW0_TLS_LE): Ditto.
(R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE): Ditto.
(R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE): Ditto.
(R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE): Ditto.
(R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE): Ditto.
(R_TILEGX_TLS_GD_CALL): Ditto.
(R_TILEGX_IMM8_X0_TLS_GD_ADD): Ditto.
(R_TILEGX_IMM8_X1_TLS_GD_ADD): Ditto.
(R_TILEGX_IMM8_Y0_TLS_GD_ADD): Ditto.
(R_TILEGX_IMM8_Y1_TLS_GD_ADD): Ditto.
(R_TILEGX_TLS_IE_LOAD): Ditto.
(R_TILEGX_IMM8_X0_TLS_ADD): Ditto.
(R_TILEGX_IMM8_X1_TLS_ADD): Ditto.
(R_TILEGX_IMM8_Y0_TLS_ADD): Ditto.
(R_TILEGX_IMM8_Y1_TLS_ADD): Ditto.
* tilepro.h (R_TILEPRO_TLS_GD_CALL): New relocation.
(R_TILEPRO_IMM8_X0_TLS_GD_ADD): Ditto.
(R_TILEPRO_IMM8_X1_TLS_GD_ADD): Ditto.
(R_TILEPRO_IMM8_Y0_TLS_GD_ADD): Ditto.
(R_TILEPRO_IMM8_Y1_TLS_GD_ADD): Ditto.
(R_TILEPRO_TLS_IE_LOAD): Ditto.
(R_TILEPRO_IMM16_X0_TLS_LE): Ditto.
(R_TILEPRO_IMM16_X1_TLS_LE): Ditto.
(R_TILEPRO_IMM16_X0_TLS_LE_LO): Ditto.
(R_TILEPRO_IMM16_X1_TLS_LE_LO): Ditto.
(R_TILEPRO_IMM16_X0_TLS_LE_HI): Ditto.
(R_TILEPRO_IMM16_X1_TLS_LE_HI): Ditto.
(R_TILEPRO_IMM16_X0_TLS_LE_HA): Ditto.
(R_TILEPRO_IMM16_X1_TLS_LE_HA): Ditto.
include/opcode/
* tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
TILEGX_OPC_LD_TLS.
* tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
TILEPRO_OPC_LW_TLS_SN.
opcodes/
* tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
* tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
TILEPRO_OPC_LW_TLS_SN.
2012-02-25 22:24:21 +00:00
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2012-02-25 Walter Lee <walt@tilera.com>
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* tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
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* tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
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TILEPRO_OPC_LW_TLS_SN.
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2012-02-21 18:09:48 +00:00
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2012-02-21 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.h (HLEPrefixNone): New.
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(HLEPrefixLock): Likewise.
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(HLEPrefixAny): Likewise.
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(HLEPrefixRelease): Likewise.
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Implement Intel Transactional Synchronization Extensions
gas/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (HLE_PREFIX): New.
(check_hle): Likewise.
(_i386_insn): Add have_hle.
(cpu_arch): Add .hle and .rtm.
(md_assemble): Call check_hle if i.have_hle isn't zero.
(parse_insn): Set i.have_hle to 1 for HLE prefix.
(output_jump): Support up to 2 byte opcode.
* doc/c-i386.texi: Document hle/.hle and rtm/.rtm.
gas/testsuite/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/hle-intel.d: New.
* gas/i386/hle.d: Likewise.
* gas/i386/hle.s: Likewise.
* gas/i386/hlebad.l: Likewise.
* gas/i386/hlebad.s: Likewise.
* gas/i386/rtm-intel.d: Likewise.
* gas/i386/rtm.d: Likewise.
* gas/i386/rtm.s: Likewise.
* gas/i386/x86-64-hle-intel.d: Likewise.
* gas/i386/x86-64-hle.d: Likewise.
* gas/i386/x86-64-hle.s: Likewise.
* gas/i386/x86-64-hlebad.l: Likewise.
* gas/i386/x86-64-hlebad.s: Likewise.
* gas/i386/x86-64-rtm-intel.d: Likewise.
* gas/i386/x86-64-rtm.d: Likewise.
* gas/i386/x86-64-rtm.s: Likewise.
* gas/i386/i386.exp: Run hle, hle-intel, hlebad x86-64-hle, rtm,
rtm-intel, x86-64-hle-intel, x86-64-hlebad, x86-64-rtm and
x86-64-rtm-intel.
include/opcode/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (XACQUIRE_PREFIX_OPCODE): New.
(XRELEASE_PREFIX_OPCODE): Likewise.
opcodes/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (HLE_Fixup1): New.
(HLE_Fixup2): Likewise.
(HLE_Fixup3): Likewise.
(Ebh1): Likewise.
(Evh1): Likewise.
(Ebh2): Likewise.
(Evh2): Likewise.
(Ebh3): Likewise.
(Evh3): Likewise.
(MOD_C6_REG_7): Likewise.
(MOD_C7_REG_7): Likewise.
(RM_C6_REG_7): Likewise.
(RM_C7_REG_7): Likewise.
(XACQUIRE_PREFIX): Likewise.
(XRELEASE_PREFIX): Likewise.
(dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
(reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
MOD_C6_REG_7 and MOD_C7_REG_7.
(mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
(rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
xtest.
(prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
(CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
* i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
CPU_RTM_FLAGS.
(cpu_flags): Add CpuHLE and CpuRTM.
(opcode_modifiers): Add HLEPrefixOk.
* i386-opc.h (CpuHLE): New.
(CpuRTM): Likewise.
(HLEPrefixOk): Likewise.
(i386_cpu_flags): Add cpuhle and cpurtm.
(i386_opcode_modifier): Add hleprefixok.
* i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
operand. Add xacquire, xrelease, xabort, xbegin, xend and
xtest.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2012-02-08 18:20:41 +00:00
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2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (HLE_Fixup1): New.
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(HLE_Fixup2): Likewise.
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(HLE_Fixup3): Likewise.
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(Ebh1): Likewise.
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(Evh1): Likewise.
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(Ebh2): Likewise.
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(Evh2): Likewise.
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(Ebh3): Likewise.
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(Evh3): Likewise.
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(MOD_C6_REG_7): Likewise.
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(MOD_C7_REG_7): Likewise.
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(RM_C6_REG_7): Likewise.
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(RM_C7_REG_7): Likewise.
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(XACQUIRE_PREFIX): Likewise.
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(XRELEASE_PREFIX): Likewise.
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(dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
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cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
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Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
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(reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
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not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
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MOD_C6_REG_7 and MOD_C7_REG_7.
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(mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
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(rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
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xtest.
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(prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
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(CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
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* i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
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CPU_RTM_FLAGS.
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(cpu_flags): Add CpuHLE and CpuRTM.
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(opcode_modifiers): Add HLEPrefixOk.
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* i386-opc.h (CpuHLE): New.
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(CpuRTM): Likewise.
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(HLEPrefixOk): Likewise.
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(i386_cpu_flags): Add cpuhle and cpurtm.
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(i386_opcode_modifier): Add hleprefixok.
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* i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
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add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
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sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
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operand. Add xacquire, xrelease, xabort, xbegin, xend and
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xtest.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2012-01-25 01:40:11 +00:00
|
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|
2012-01-24 DJ Delorie <dj@redhat.com>
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* rl78-decode.opc (rl78_decode_opcode): Add NOT1.
|
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|
* rl78-decode.c: Regenerate.
|
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|
2012-01-16 23:51:35 +00:00
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|
2012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
|
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PR binutils/10173
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* cr16-dis.c (print_arg): Test symtab_size not num_symbols.
|
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2012-01-16 23:19:20 +00:00
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2012-01-17 Andreas Schwab <schwab@linux-m68k.org>
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* m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
|
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register and move them after pmove with PSR/PCSR register.
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2012-01-13 22:19:32 +00:00
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2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (mod_table): Add vmfunc.
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* i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
|
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|
(cpu_flags): CpuVMFUNC.
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* i386-opc.h (CpuVMFUNC): New.
|
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|
(i386_cpu_flags): Add cpuvmfunc.
|
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|
* i386-opc.tbl: Add vmfunc.
|
|
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|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
2011-12-15 10:21:51 +00:00
|
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|
2012-01-05 10:09:39 +00:00
|
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|
For older changes see ChangeLog-2011
|
1999-05-03 07:29:11 +00:00
|
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Local Variables:
|
2001-01-11 19:01:42 +00:00
|
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mode: change-log
|
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|
left-margin: 8
|
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|
fill-column: 74
|
1999-05-03 07:29:11 +00:00
|
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|
version-control: never
|
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End:
|
