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Add support for PowerPC VLE.

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2012-05-14  Catherine Moore  <clm@codesourcery.com>

	* NEWS:  Mention PowerPC VLE port.

2012-05-14  James Lemke <jwlemke@codesourcery.com>
	    Catherine Moore  <clm@codesourcery.com>

	bfd/
	* bfd.c (bfd_lookup_section_flags): Add section parm.
	* ecoff.c (bfd_debug_section): Remove flag_info initializer.
	* elf-bfd.h (bfd_elf_section_data): Move in section_flag_info.
	(bfd_elf_lookup_section_flags): Add section parm.
	* elf32-ppc.c (is_ppc_vle): New function.
	(ppc_elf_modify_segment_map): New function.
	(elf_backend_modify_segment_map): Define.
	(has_vle_insns): New define.
	* elf32-ppc.h (ppc_elf_modify_segment_map): Declare.
	* elflink.c (bfd_elf_lookup_section_flags): Add return value & parm.
	Move in logic to omit / include a section.
	* libbfd-in.h (bfd_link_info): Add section parm.
	(bfd_generic_lookup_section_flags): Likewise.
	* reloc.c (bfd_generic_lookup_section_flags): Likewise.
	* section.c (bfd_section): Move out section_flag_info.
	(BFD_FAKE_SECTION): Remove flag_info initializer.
	* targets.c (_bfd_lookup_section_flags): Add section parm.

2012-05-14  Catherine Moore  <clm@codesourcery.com>

	bfd/
	* archures.c (bfd_mach_ppc_vle): New.
	* bfd-in2.h: Regenerated.
	* cpu-powerpc.c (bfd_powerpc_archs): New entry for vle.
	* elf32-ppc.c (split16_format_type): New enumeration.
	(ppc_elf_vle_split16): New function.
	(HOWTO): Add entries for R_PPC_VLE relocations.
	(ppc_elf_reloc_type_lookup): Handle PPC_VLE relocations.
	(ppc_elf_section_flags): New function.
	(ppc_elf_lookup_section_flags): New function.
	(ppc_elf_section_processing): New function.
	(ppc_elf_check_relocs): Handle PPC_VLE relocations.
	(ppc_elf_relocation_section): Likewise.
	(elf_backend_lookup_section_flags_hook): Define.
	(elf_backend_section_flags): Define.
	(elf_backend_section_processing): Define.
	* elf32-ppc.h (ppc_elf_section_processing): Declare.
	* libbfd.h: Regenerated.
	* reloc.c (BFD_RELOC_PPC_VLE_REL8, BFD_RELOC_PPC_VLE_REL15,
	BFD_RELOC_PPC_VLE_REL24, BFD_RELOC_PPC_VLE_LO16A,
	BFD_RELOC_PPC_VLE_LO16D, BFD_RELOC_PPC_VLE_HI16A,
	BFD_RELOC_PPC_VLE_HI16D, BFD_RELOC_PPC_VLE_HA16A,
	BFD_RELOC_PPC_VLE_HA16D, BFD_RELOC_PPC_VLE_SDA21,
	BFD_RELOC_PPC_VLE_SDA21_LO, BFD_RELOC_PPC_VLE_SDAREL_LO16A,
	BFD_RELOC_PPC_VLE_SDAREL_LO16D, BFD_RELOC_PPC_VLE_SDAREL_HI16A,
	BFD_RELOC_PPC_VLE_SDAREL_HI16D, BFD_RELOC_PPC_VLE_SDAREL_HA16A,
	BFD_RELOC_PPC_VLE_SDAREL_HA16D): New bfd relocations.

2012-05-14  James Lemke  <jwlemke@codesourcery.com>

	gas/
	* config/tc-ppc.c (insn_validate): New func of existing code to call..
	(ppc_setup_opcodes): ..from 2 places here.
	Revise for second (VLE) opcode table.
	Add #ifdef'd code to print opcode tables.

2012-05-14  James Lemke  <jwlemke@codesourcery.com>

	gas/
	* config/tc-ppc.c (ppc_setup_opcodes): Allow out-of-order
	for the VLE conditional branches.

2012-05-14  Catherine Moore  <clm@codesourcery.com>
            Maciej W. Rozycki  <macro@codesourcery.com>
	    Rhonda Wittels  <rhonda@codesourcery.com>

	gas/
	* config/tc-ppc.c (PPC_VLE_SPLIT16A): New macro.
	(PPC_VLE_SPLIT16D): New macro.
	(PPC_VLE_LO16A): New macro.
	(PPC_VLE_LO16D): New macro.
	(PPC_VLE_HI16A): New macro.
	(PPC_VLE_HI16D): New macro.
	(PPC_VLE_HA16A): New macro.
	(PPC_VLE_HA16D): New macro.
	(PPC_APUINFO_VLE): New definition.
	(md_chars_to_number): New function.
	(md_parse_option): Check for combinations of little
	endian and -mvle.
	(md_show_usage): Document -mvle.
	(ppc_arch): Recognize VLE.
	(ppc_mach): Recognize bfd_mach_ppc_vle.
	(ppc_setup_opcodes): Print the opcode table if
	* config/tc-ppc.h (ppc_frag_check): Declare.
	* doc/c-ppc.texi: Document -mvle.
	* NEWS:  Mention PowerPC VLE port.

2012-05-14  Catherine Moore  <clm@codesourcery.com>

	gas/
	* config/tc-ppc.h (ppc_dw2_line_min_insn_length): Declare.
	(DWARF2_LINE_MIN_INSN_LENGTH): Redefine.
	* config/tc-ppc.c (ppc_dw2_line_min_insn_length): New.
	* dwarf2dbg.c (scale_addr_delta): Handle values of 1
	for DWARF2_LINE_MIN_INSN_LENGTH.

2012-05-14  Catherine Moore  <clm@codesourcery.com>
            Maciej W. Rozycki  <macro@codesourcery.com>
	    Rhonda Wittels  <rhonda@codesourcery.com>

	gas/testsuite/
	* gas/ppc/ppc.exp: Run new tests.
	* gas/ppc/vle-reloc.d: New test.
	* gas/ppc/vle-reloc.s: New test.
	* gas/ppc/vle-simple-1.d: New test.
	* gas/ppc/vle-simple-1.s: New test.
	* gas/ppc/vle-simple-2.d: New test.
	* gas/ppc/vle-simple-2.s: New test.
	* gas/ppc/vle-simple-3.d: New test.
	* gas/ppc/vle-simple-3.s: New test.
	* gas/ppc/vle-simple-4.d: New test.
	* gas/ppc/vle-simple-4.s: New test.
	* gas/ppc/vle-simple-5.d: New test.
	* gas/ppc/vle-simple-5.s: New test.
	* gas/ppc/vle-simple-6.d: New test.
	* gas/ppc/vle-simple-6.s: New test.
	* gas/ppc/vle.d: New test.
	* gas/ppc/vle.s: New test.

2012-05-14  James Lemke  <jwlemke@codesourcery.com>
	include/elf/
	* ppc.h (SEC_PPC_VLE): Remove.

2012-05-14  Catherine Moore  <clm@codesourcery.com>
	    James Lemke  <jwlemke@codesourcery.com>

	include/elf/
	* ppc.h (R_PPC_VLE_REL8): New reloction.
	(R_PPC_VLE_REL15): Likewise.
	(R_PPC_VLE_REL24): Likewise.
	(R_PPC_VLE_LO16A): Likewise.
	(R_PPC_VLE_LO16D): Likewise.
	(R_PPC_VLE_HI16A): Likewise.
	(R_PPC_VLE_HI16D): Likewise.
	(R_PPC_VLE_HA16A): Likewise.
	(R_PPC_VLE_HA16D): Likewise.
	(R_PPC_VLE_SDA21): Likewise.
	(R_PPC_VLE_SDA21_LO): Likewise.
	(R_PPC_VLE_SDAREL_LO16A): Likewise.
	(R_PPC_VLE_SDAREL_LO16D): Likewise.
	(R_PPC_VLE_SDAREL_HI16A): Likewise.
	(R_PPC_VLE_SDAREL_HI16D): Likewise.
	(R_PPC_VLE_SDAREL_HA16A): Likewise.
	(R_PPC_VLE_SDAREL_HA16D): Likewise.
	(SEC_PPC_VLE): Remove.
	(PF_PPC_VLE): New program header flag.
	(SHF_PPC_VLE): New section header flag.
	(vle_opcodes, vle_num_opcodes): New.
	(VLE_OP): New macro.
	(VLE_OP_TO_SEG): New macro.

2012-05-14  Catherine Moore  <clm@codesourcery.com>
            Maciej W. Rozycki  <macro@codesourcery.com>
	    Rhonda Wittels  <rhonda@codesourcery.com>

	include/opcode/
	* ppc.h (PPC_OPCODE_VLE): New definition.
	(PPC_OP_SA): New macro.
	(PPC_OP_SE_VLE): New macro.
	(PPC_OP): Use a variable shift amount.
	(powerpc_operand): Update comments.
	(PPC_OPSHIFT_INV): New macro.
	(PPC_OPERAND_CR): Replace with...
	(PPC_OPERAND_CR_BIT): ...this and
	(PPC_OPERAND_CR_REG): ...this.

2012-05-14  James Lemke  <jwlemke@codesourcery.com>

	ld/
	* ldlang.c (walk_wild_consider_section): Don't copy section_flag_list.
	Pass it to callback.
	(walk_wild_section_general): Pass section_flag_list to callback.
	(lang_add_section): Add sflag_list parm.
	Move out logic to keep / omit a section & call bfd_lookup_section_flags.
	(output_section_callback_fast): Add sflag_list parm.
	Add new parm to lang_add_section calls.
	(output_section_callback): Likewise.
	(check_section_callback): Add sflag_list parm.
	(lang_place_orphans): Add new parm to lang_add_section calls.
	(gc_section_callback): Add sflag_list parm.
	(find_relro_section_callback): Likewise.
	* ldlang.h (callback_t): Add flag_info parm.
	(lang_add_section): Add sflag_list parm.
	* emultempl/armelf.em (elf32_arm_add_stub_section):
	Add lang_add_section parm.
	* emultempl/beos.em (gld*_place_orphan): Likewise.
	* emultempl/elf32.em (gld*_place_orphan): Likewise.
	* emultempl/hppaelf.em (hppaelf_add_stub_section): Likewise.
	* emultempl/m68hc1xelf.em (m68hc11elf_add_stub_section): Likewise.
	* emultempl/mipself.em (mips_add_stub_section): Likewise.
	* emultempl/mmo.em (mmo_place_orphan): Likewise.
	* emultempl/pe.em (gld_*_place_orphan): Likewise.
	* emultempl/pep.em (gld_*_place_orphan): Likewise.
	* emultempl/ppc64elf.em (ppc_add_stub_section): Likewise.
	* emultempl/spuelf.em (spu_place_special_section): Likewise.
	* emultempl/vms.em (vms_place_orphan): Likewise.

2012-05-14  James Lemke  <jwlemke@codesourcery.com>

	ld/testsuite/
	* ld-powerpc/powerpc.exp: Create ppceabitests.
	* ld-powerpc/vle-multiseg.s: New.
	* ld-powerpc/vle-multiseg-1.d: New.
	* ld-powerpc/vle-multiseg-1.ld: New.
	* ld-powerpc/vle-multiseg-2.d: New.
	* ld-powerpc/vle-multiseg-2.ld: New.
	* ld-powerpc/vle-multiseg-3.d: New.
	* ld-powerpc/vle-multiseg-3.ld: New.
	* ld-powerpc/vle-multiseg-4.d: New.
	* ld-powerpc/vle-multiseg-4.ld: New.
	* ld-powerpc/vle-multiseg-5.d: New.
	* ld-powerpc/vle-multiseg-5.ld: New.
	* ld-powerpc/vle-multiseg-6.d: New.
	* ld-powerpc/vle-multiseg-6.ld: New.
	* ld-powerpc/vle-multiseg-6a.s: New.
	* ld-powerpc/vle-multiseg-6b.s: New.
	* ld-powerpc/vle-multiseg-6c.s: New.
	* ld-powerpc/vle-multiseg-6d.s: New.
	* ld-powerpc/powerpc.exp: Run new tests.

2012-05-14  Catherine Moore  <clm@codesourcery.com>

	ld/
	* NEWS:  Mention PowerPC VLE port.

2012-05-14  Catherine Moore  <clm@codesourcery.com>

	ld/testsuite/
	* ld-powerpc/apuinfo.rd: Update for VLE.
	* ld-powerpc/vle-reloc-1.d: New.
	* ld-powerpc/vle-reloc-1.s: New.
	* ld-powerpc/vle-reloc-2.d: New.
	* ld-powerpc/vle-reloc-2.s: New.
	* ld-powerpc/vle-reloc-3.d: New.
	* ld-powerpc/vle-reloc-3.s: New.
	* ld-powerpc/vle-reloc-def-1.s: New.
	* ld-powerpc/vle-reloc-def-2.s: New.
	* ld-powerpc/vle-reloc-def-3.s: New.

2012-05-14  James Lemke  <jwlemke@codesourcery.com>

	opcodes/
	* ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
	(PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
	(vle_opcd_indices): New array.
	(lookup_vle): New function.
	(disassemble_init_powerpc): Revise for second (VLE) opcode table.
	(print_insn_powerpc): Likewise.
	* ppc-opc.c: Likewise.

2012-05-14  Catherine Moore  <clm@codesourcery.com>
            Maciej W. Rozycki  <macro@codesourcery.com>
	    Rhonda Wittels  <rhonda@codesourcery.com>
	    Nathan Froyd <froydnj@codesourcery.com>

	opcodes/
	* ppc-opc.c (insert_arx, extract_arx): New functions.
	(insert_ary, extract_ary): New functions.
	(insert_li20, extract_li20): New functions.
	(insert_rx, extract_rx): New functions.
	(insert_ry, extract_ry): New functions.
	(insert_sci8, extract_sci8): New functions.
	(insert_sci8n, extract_sci8n): New functions.
	(insert_sd4h, extract_sd4h): New functions.
	(insert_sd4w, extract_sd4w): New functions.
	(insert_vlesi, extract_vlesi): New functions.
	(insert_vlensi, extract_vlensi): New functions.
	(insert_vleui, extract_vleui): New functions.
	(insert_vleil, extract_vleil): New functions.
 	(BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
 	(BI16, BI32, BO32, B8): New.
	(B15, B24, CRD32, CRS): New.
 	(CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
	(DB, IMM20, RD, Rx, ARX, RY, RZ): New.
	(ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
	(SH6_MASK): Use PPC_OPSHIFT_INV.
	(SI8, UI5, OIMM5, UI7, BO16): New.
	(VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
	(XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
	(ALLOW8_SPRG): New.
	(insert_sprg, extract_sprg): Check ALLOW8_SPRG.
	(OPVUP, OPVUP_MASK OPVUP): New
	(BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
	(EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
	(BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
	(BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
 	(IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
	(IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
	(SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
	(SE_IM5, SE_IM5_MASK): New.
	(SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
	(EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
	(BO32DNZ, BO32DZ): New.
	(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
	(PPCVLE): New.
	(powerpc_opcodes): Add new VLE instructions.  Update existing
	instruction to include PPCVLE if supported.
	* ppc-dis.c (ppc_opts): Add vle entry.
	(get_powerpc_dialect): New function.
	(powerpc_init_dialect): VLE support.
	(print_insn_big_powerpc): Call get_powerpc_dialect.
	(print_insn_little_powerpc): Likewise.
	(operand_value_powerpc): Handle negative shift counts.
	(print_insn_powerpc): Handle 2-byte instruction lengths.
This commit is contained in:
James Lemke 2012-05-14 19:45:30 +00:00
parent ac1438b5c5
commit b9c361e0ad
92 changed files with 5385 additions and 1139 deletions
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4
ChangeLog
View file

@ -1,3 +1,7 @@
2012-05-14 Catherine Moore <clm@codesourcery.com>
* NEWS: Mention PowerPC VLE port.
2012-05-11 Mike Frysinger <vapier@gentoo.org>
* MAINTAINERS (config/): Move to intl/ section.

50
bfd/ChangeLog
View file

@ -1,3 +1,53 @@
2012-05-14 James Lemke <jwlemke@codesourcery.com>
Catherine Moore <clm@codesourcery.com>
* bfd.c (bfd_lookup_section_flags): Add section parm.
* ecoff.c (bfd_debug_section): Remove flag_info initializer.
* elf-bfd.h (bfd_elf_section_data): Move in section_flag_info.
(bfd_elf_lookup_section_flags): Add section parm.
* elf32-ppc.c (is_ppc_vle): New function.
(ppc_elf_modify_segment_map): New function.
(elf_backend_modify_segment_map): Define.
(has_vle_insns): New define.
* elf32-ppc.h (ppc_elf_modify_segment_map): Declare.
* elflink.c (bfd_elf_lookup_section_flags): Add return value & parm.
Move in logic to omit / include a section.
* libbfd-in.h (bfd_link_info): Add section parm.
(bfd_generic_lookup_section_flags): Likewise.
* reloc.c (bfd_generic_lookup_section_flags): Likewise.
* section.c (bfd_section): Move out section_flag_info.
(BFD_FAKE_SECTION): Remove flag_info initializer.
* targets.c (_bfd_lookup_section_flags): Add section parm.
2012-05-14 Catherine Moore <clm@codesourcery.com>
* archures.c (bfd_mach_ppc_vle): New.
* bfd-in2.h: Regenerated.
* cpu-powerpc.c (bfd_powerpc_archs): New entry for vle.
* elf32-ppc.c (split16_format_type): New enumeration.
(ppc_elf_vle_split16): New function.
(HOWTO): Add entries for R_PPC_VLE relocations.
(ppc_elf_reloc_type_lookup): Handle PPC_VLE relocations.
(ppc_elf_section_flags): New function.
(ppc_elf_lookup_section_flags): New function.
(ppc_elf_section_processing): New function.
(ppc_elf_check_relocs): Handle PPC_VLE relocations.
(ppc_elf_relocation_section): Likewise.
(elf_backend_lookup_section_flags_hook): Define.
(elf_backend_section_flags): Define.
(elf_backend_section_processing): Define.
* elf32-ppc.h (ppc_elf_section_processing): Declare.
* libbfd.h: Regenerated.
* reloc.c (BFD_RELOC_PPC_VLE_REL8, BFD_RELOC_PPC_VLE_REL15,
BFD_RELOC_PPC_VLE_REL24, BFD_RELOC_PPC_VLE_LO16A,
BFD_RELOC_PPC_VLE_LO16D, BFD_RELOC_PPC_VLE_HI16A,
BFD_RELOC_PPC_VLE_HI16D, BFD_RELOC_PPC_VLE_HA16A,
BFD_RELOC_PPC_VLE_HA16D, BFD_RELOC_PPC_VLE_SDA21,
BFD_RELOC_PPC_VLE_SDA21_LO, BFD_RELOC_PPC_VLE_SDAREL_LO16A,
BFD_RELOC_PPC_VLE_SDAREL_LO16D, BFD_RELOC_PPC_VLE_SDAREL_HI16A,
BFD_RELOC_PPC_VLE_SDAREL_HI16D, BFD_RELOC_PPC_VLE_SDAREL_HA16A,
BFD_RELOC_PPC_VLE_SDAREL_HA16D): New bfd relocations.
2012-05-11 Georg-Johann Lay <avr@gjlay.de
PR target/13503

1
bfd/archures.c
View file

@ -244,6 +244,7 @@ DESCRIPTION
.#define bfd_mach_ppc_e5500 5006
.#define bfd_mach_ppc_e6500 5007
.#define bfd_mach_ppc_titan 83
.#define bfd_mach_ppc_vle 84
. bfd_arch_rs6000, {* IBM RS/6000 *}
.#define bfd_mach_rs6k 6000
.#define bfd_mach_rs6k_rs1 6001

33
bfd/bfd-in2.h
View file

@ -1512,9 +1512,6 @@ typedef struct bfd_section
/* The BFD which owns the section. */
bfd *owner;
/* INPUT_SECTION_FLAGS if specified in the linker script. */
struct flag_info *section_flag_info;
/* A symbol which points at this section only. */
struct bfd_symbol *symbol;
struct bfd_symbol **symbol_ptr_ptr;
@ -1690,9 +1687,6 @@ extern asection std_section[4];
/* target_index, used_by_bfd, constructor_chain, owner, */ \
0, NULL, NULL, NULL, \
\
/* flag_info, */ \
NULL, \
\
/* symbol, symbol_ptr_ptr, */ \
(struct bfd_symbol *) SYM, &SEC.symbol, \
\
@ -1942,6 +1936,7 @@ enum bfd_architecture
#define bfd_mach_ppc_e5500 5006
#define bfd_mach_ppc_e6500 5007
#define bfd_mach_ppc_titan 83
#define bfd_mach_ppc_vle 84
bfd_arch_rs6000, /* IBM RS/6000 */
#define bfd_mach_rs6k 6000
#define bfd_mach_rs6k_rs1 6001
@ -3095,6 +3090,23 @@ instruction. */
BFD_RELOC_PPC_EMB_RELST_HA,
BFD_RELOC_PPC_EMB_BIT_FLD,
BFD_RELOC_PPC_EMB_RELSDA,
BFD_RELOC_PPC_VLE_REL8,
BFD_RELOC_PPC_VLE_REL15,
BFD_RELOC_PPC_VLE_REL24,
BFD_RELOC_PPC_VLE_LO16A,
BFD_RELOC_PPC_VLE_LO16D,
BFD_RELOC_PPC_VLE_HI16A,
BFD_RELOC_PPC_VLE_HI16D,
BFD_RELOC_PPC_VLE_HA16A,
BFD_RELOC_PPC_VLE_HA16D,
BFD_RELOC_PPC_VLE_SDA21,
BFD_RELOC_PPC_VLE_SDA21_LO,
BFD_RELOC_PPC_VLE_SDAREL_LO16A,
BFD_RELOC_PPC_VLE_SDAREL_LO16D,
BFD_RELOC_PPC_VLE_SDAREL_HI16A,
BFD_RELOC_PPC_VLE_SDAREL_HI16D,
BFD_RELOC_PPC_VLE_SDAREL_HA16A,
BFD_RELOC_PPC_VLE_SDAREL_HA16D,
BFD_RELOC_PPC64_HIGHER,
BFD_RELOC_PPC64_HIGHER_S,
BFD_RELOC_PPC64_HIGHEST,
@ -5788,8 +5800,8 @@ bfd_boolean bfd_set_private_flags (bfd *abfd, flagword flags);
#define bfd_gc_sections(abfd, link_info) \
BFD_SEND (abfd, _bfd_gc_sections, (abfd, link_info))
#define bfd_lookup_section_flags(link_info, flag_info) \
BFD_SEND (abfd, _bfd_lookup_section_flags, (link_info, flag_info))
#define bfd_lookup_section_flags(link_info, flag_info, section) \
BFD_SEND (abfd, _bfd_lookup_section_flags, (link_info, flag_info, section))
#define bfd_merge_sections(abfd, link_info) \
BFD_SEND (abfd, _bfd_merge_sections, (abfd, link_info))
@ -6265,8 +6277,9 @@ typedef struct bfd_target
bfd_boolean (*_bfd_gc_sections) (bfd *, struct bfd_link_info *);
/* Sets the bitmask of allowed and disallowed section flags. */
void (*_bfd_lookup_section_flags) (struct bfd_link_info *,
struct flag_info *);
bfd_boolean (*_bfd_lookup_section_flags) (struct bfd_link_info *,
struct flag_info *,
asection *);
/* Attempt to merge SEC_MERGE sections. */
bfd_boolean (*_bfd_merge_sections) (bfd *, struct bfd_link_info *);

4
bfd/bfd.c
View file

@ -1456,8 +1456,8 @@ DESCRIPTION
.#define bfd_gc_sections(abfd, link_info) \
. BFD_SEND (abfd, _bfd_gc_sections, (abfd, link_info))
.
.#define bfd_lookup_section_flags(link_info, flag_info) \
. BFD_SEND (abfd, _bfd_lookup_section_flags, (link_info, flag_info))
.#define bfd_lookup_section_flags(link_info, flag_info, section) \
. BFD_SEND (abfd, _bfd_lookup_section_flags, (link_info, flag_info, section))
.
.#define bfd_merge_sections(abfd, link_info) \
. BFD_SEND (abfd, _bfd_merge_sections, (abfd, link_info))

17
bfd/cpu-powerpc.c
View file

@ -375,6 +375,21 @@ const bfd_arch_info_type bfd_powerpc_archs[] =
bfd_arch_default_fill,
&bfd_powerpc_archs[19]
},
{
16, /* 16 or 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_powerpc,
bfd_mach_ppc_vle,
"powerpc",
"powerpc:vle",
3,
FALSE, /* not the default */
powerpc_compatible,
bfd_default_scan,
bfd_arch_default_fill,
&bfd_powerpc_archs[20]
},
{
64, /* 64 bits in a word */
64, /* 64 bits in an address */
@ -388,7 +403,7 @@ const bfd_arch_info_type bfd_powerpc_archs[] =
powerpc_compatible,
bfd_default_scan,
bfd_arch_default_fill,
&bfd_powerpc_archs[20]
&bfd_powerpc_archs[21]
},
{
64, /* 64 bits in a word */

2
bfd/ecoff.c
View file

@ -73,8 +73,6 @@ static asection bfd_debug_section =
0, NULL, 0,
/* target_index, used_by_bfd, constructor_chain, owner, */
0, NULL, NULL, NULL,
/* flag_info, */
NULL,
/* symbol, */
NULL,
/* symbol_ptr_ptr, */

7
bfd/elf-bfd.h
View file

@ -1367,6 +1367,9 @@ struct bfd_elf_section_data
/* The ELF header for this section. */
Elf_Internal_Shdr this_hdr;
/* INPUT_SECTION_FLAGS if specified in the linker script. */
struct flag_info *section_flag_info;
/* Information about the REL and RELA reloc sections associated
with this section, if any. */
struct bfd_elf_section_reloc_data rel, rela;
@ -2207,8 +2210,8 @@ extern bfd_boolean _bfd_elf_maybe_function_sym (const asymbol *,
extern int bfd_elf_get_default_section_type (flagword);
extern void bfd_elf_lookup_section_flags
(struct bfd_link_info *, struct flag_info *);
extern bfd_boolean bfd_elf_lookup_section_flags
(struct bfd_link_info *, struct flag_info *, asection *);
extern Elf_Internal_Phdr * _bfd_elf_find_segment_containing_section
(bfd * abfd, asection * section);

634
bfd/elf32-ppc.c
View file

@ -38,12 +38,21 @@
#include "elf-vxworks.h"
#include "dwarf2.h"
typedef enum split16_format_type
{
split16a_type = 0,
split16d_type
}
split16_format_type;
/* RELA relocations are used here. */
static bfd_reloc_status_type ppc_elf_addr16_ha_reloc
(bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
static bfd_reloc_status_type ppc_elf_unhandled_reloc
(bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
static void ppc_elf_vle_split16
(bfd *, bfd_byte *, bfd_vma, bfd_vma, split16_format_type);
/* Branch prediction bit for branch taken relocs. */
#define BRANCH_PREDICT_BIT 0x200000
@ -1392,6 +1401,262 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A relative 8 bit branch. */
HOWTO (R_PPC_VLE_REL8, /* type */
1, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_REL8", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0xff, /* dst_mask */
TRUE), /* pcrel_offset */
/* A relative 15 bit branch. */
HOWTO (R_PPC_VLE_REL15, /* type */
1, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
15, /* bitsize */
TRUE, /* pc_relative */
1, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_REL15", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0xfe, /* dst_mask */
TRUE), /* pcrel_offset */
/* A relative 24 bit branch. */
HOWTO (R_PPC_VLE_REL24, /* type */
1, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
24, /* bitsize */
TRUE, /* pc_relative */
1, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_REL24", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x1fffffe, /* dst_mask */
TRUE), /* pcrel_offset */
/* The 16 LSBS in split16a format. */
HOWTO (R_PPC_VLE_LO16A, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */ /* FIXME: Does this apply to split relocs? */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_LO16A", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x1f00fff, /* dst_mask */
FALSE), /* pcrel_offset */
/* The 16 LSBS in split16d format. */
HOWTO (R_PPC_VLE_LO16D, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_LO16D", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x1f07ff, /* dst_mask */
FALSE), /* pcrel_offset */
/* Bits 16-31 split16a format. */
HOWTO (R_PPC_VLE_HI16A, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_HI16A", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x1f00fff, /* dst_mask */
FALSE), /* pcrel_offset */
/* Bits 16-31 split16d format. */
HOWTO (R_PPC_VLE_HI16D, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_HI16D", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x1f07ff, /* dst_mask */
FALSE), /* pcrel_offset */
/* Bits 16-31 (High Adjusted) in split16a format. */
HOWTO (R_PPC_VLE_HA16A, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_HA16A", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x1f00fff, /* dst_mask */
FALSE), /* pcrel_offset */
/* Bits 16-31 (High Adjusted) in split16d format. */
HOWTO (R_PPC_VLE_HA16D, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_HA16D", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x1f07ff, /* dst_mask */
FALSE), /* pcrel_offset */
/* This reloc does nothing. */
HOWTO (R_PPC_VLE_SDA21, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_SDA21", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* This reloc does nothing. */
HOWTO (R_PPC_VLE_SDA21_LO, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_SDA21_LO", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* The 16 LSBS relative to _SDA_BASE_ in split16a format. */
HOWTO (R_PPC_VLE_SDAREL_LO16A,/* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_SDAREL_LO16A", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x1f00fff, /* dst_mask */
FALSE), /* pcrel_offset */
/* The 16 LSBS relative to _SDA_BASE_ in split16d format. */
/* This reloc does nothing. */
HOWTO (R_PPC_VLE_SDAREL_LO16D, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_SDAREL_LO16D", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x1f07ff, /* dst_mask */
FALSE), /* pcrel_offset */
/* Bits 16-31 relative to _SDA_BASE_ in split16a format. */
HOWTO (R_PPC_VLE_SDAREL_HI16A, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_SDAREL_HI16A", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x1f00fff, /* dst_mask */
FALSE), /* pcrel_offset */
/* Bits 16-31 relative to _SDA_BASE_ in split16d format. */
HOWTO (R_PPC_VLE_SDAREL_HI16D, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_SDAREL_HI16D", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x1f07ff, /* dst_mask */
FALSE), /* pcrel_offset */
/* Bits 16-31 (HA) relative to _SDA_BASE split16a format. */
HOWTO (R_PPC_VLE_SDAREL_HA16A, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_SDAREL_HA16A", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x1f00fff, /* dst_mask */
FALSE), /* pcrel_offset */
/* Bits 16-31 (HA) relative to _SDA_BASE split16d format. */
HOWTO (R_PPC_VLE_SDAREL_HA16D, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_PPC_VLE_SDAREL_HA16D", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0x1f07ff, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (R_PPC_IRELATIVE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@ -1628,6 +1893,35 @@ ppc_elf_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
case BFD_RELOC_PPC_EMB_RELST_HA: r = R_PPC_EMB_RELST_HA; break;
case BFD_RELOC_PPC_EMB_BIT_FLD: r = R_PPC_EMB_BIT_FLD; break;
case BFD_RELOC_PPC_EMB_RELSDA: r = R_PPC_EMB_RELSDA; break;
case BFD_RELOC_PPC_VLE_REL8: r = R_PPC_VLE_REL8; break;
case BFD_RELOC_PPC_VLE_REL15: r = R_PPC_VLE_REL15; break;
case BFD_RELOC_PPC_VLE_REL24: r = R_PPC_VLE_REL24; break;
case BFD_RELOC_PPC_VLE_LO16A: r = R_PPC_VLE_LO16A; break;
case BFD_RELOC_PPC_VLE_LO16D: r = R_PPC_VLE_LO16D; break;
case BFD_RELOC_PPC_VLE_HI16A: r = R_PPC_VLE_HI16A; break;
case BFD_RELOC_PPC_VLE_HI16D: r = R_PPC_VLE_HI16D; break;
case BFD_RELOC_PPC_VLE_HA16A: r = R_PPC_VLE_HA16A; break;
case BFD_RELOC_PPC_VLE_HA16D: r = R_PPC_VLE_HA16D; break;
case BFD_RELOC_PPC_VLE_SDA21: r = R_PPC_VLE_SDA21; break;
case BFD_RELOC_PPC_VLE_SDA21_LO: r = R_PPC_VLE_SDA21_LO; break;
case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
r = R_PPC_VLE_SDAREL_LO16A;
break;
case BFD_RELOC_PPC_VLE_SDAREL_LO16D:
r = R_PPC_VLE_SDAREL_LO16D;
break;
case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
r = R_PPC_VLE_SDAREL_HI16A;
break;
case BFD_RELOC_PPC_VLE_SDAREL_HI16D:
r = R_PPC_VLE_SDAREL_HI16D;
break;
case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
r = R_PPC_VLE_SDAREL_HA16A;
break;
case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
r = R_PPC_VLE_SDAREL_HA16D;
break;
case BFD_RELOC_16_PCREL: r = R_PPC_REL16; break;
case BFD_RELOC_LO16_PCREL: r = R_PPC_REL16_LO; break;
case BFD_RELOC_HI16_PCREL: r = R_PPC_REL16_HI; break;
@ -1800,6 +2094,26 @@ struct ppc_elf_obj_tdata
(bfd_get_flavour (bfd) == bfd_target_elf_flavour \
&& elf_object_id (bfd) == PPC32_ELF_DATA)
/* Rename some of the generic section flags to better document how they
are used for ppc32. */
/* Nonzero if this section has TLS related relocations. */
#define has_tls_reloc sec_flg0
/* Nonzero if this section has a call to __tls_get_addr. */
#define has_tls_get_addr_call sec_flg1
/* Nonzero if this secs_tls_get_addr_calltion has the VLE bit set. */
#define has_vle_insns sec_flg2
bfd_boolean
is_ppc_vle (asection *sec)
{
return (sec->owner != NULL
&& is_ppc_elf (sec->owner)
&& sec->has_vle_insns);
}
/* Override the generic function because we store some extras. */
static bfd_boolean
@ -1952,6 +2266,37 @@ ppc_elf_write_core_note (bfd *abfd, char *buf, int *bufsiz, int note_type, ...)
}
}
static bfd_boolean
ppc_elf_section_flags (flagword *flags ATTRIBUTE_UNUSED,
const Elf_Internal_Shdr *hdr)
{
if (hdr->sh_flags & SHF_PPC_VLE)
hdr->bfd_section->has_vle_insns = 1;
return TRUE;
}
static flagword
ppc_elf_lookup_section_flags (char *flag_name)
{
if (!strcmp (flag_name, "SHF_PPC_VLE"))
return SHF_PPC_VLE;
return 0;
}
/* Add the VLE flag if required. */
bfd_boolean
ppc_elf_section_processing (bfd *abfd, Elf_Internal_Shdr *shdr)
{
if (bfd_get_mach (abfd) == bfd_mach_ppc_vle
&& (shdr->sh_flags & SHF_EXECINSTR) != 0)
shdr->sh_flags |= SHF_PPC_VLE;
return TRUE;
}
/* Return address for Ith PLT stub in section PLT, for relocation REL
or (bfd_vma) -1 if it should not be included. */
@ -2025,6 +2370,70 @@ ppc_elf_additional_program_headers (bfd *abfd,
return ret;
}
/* Modify the segment map for VLE executables. */
bfd_boolean
ppc_elf_modify_segment_map (bfd *abfd,
struct bfd_link_info *info ATTRIBUTE_UNUSED)
{
struct elf_segment_map *m, *n;
bfd_size_type amt;
unsigned int j, k;
bfd_boolean sect0_vle, sectj_vle;
/* At this point in the link, output sections have already been sorted by
LMA and assigned to segments. All that is left to do is to ensure
there is no mixing of VLE & non-VLE sections in a text segment.
If we find that case, we split the segment.
We maintain the original output section order. */
for (m = elf_tdata (abfd)->segment_map; m != NULL; m = m->next)
{
if (m->count == 0)
continue;
sect0_vle = is_ppc_vle (m->sections[0]);
for (j = 1; j < m->count; ++j)
{
if (is_ppc_vle (m->sections[j]) != sect0_vle)
break;
}
if (j >= m->count)
continue;
sectj_vle = is_ppc_vle (m->sections[j]);
/* sections 0..j-1 stay in this (current) segment,
the remainder are put in a new segment.
The scan resumes with the new segment. */
/* Fix the new segment. */
amt = sizeof (struct elf_segment_map);
amt += (m->count - j - 1) * sizeof (asection *);
n = (struct elf_segment_map *) bfd_zalloc (abfd, amt);
if (n == NULL)
return FALSE;
n->p_type = PT_LOAD;
n->p_flags = PF_X | PF_R;
if (sectj_vle)
n->p_flags |= PF_PPC_VLE;
n->count = m->count - j;
for (k = 0; k < n->count; ++k)
{
n->sections[k] = m->sections[j+k];
m->sections[j+k] = NULL;
}
n->next = m->next;
m->next = n;
/* Fix the current segment */
m->count = j;
}
return TRUE;
}
/* Add extra PPC sections -- Note, for now, make .sbss2 and
.PPC.EMB.sbss0 a normal section, and not a bss section so
that the linker doesn't crater when trying to make more than
@ -2731,15 +3140,6 @@ struct ppc_elf_link_hash_table
struct sym_cache sym_cache;
};
/* Rename some of the generic section flags to better document how they
are used here. */
/* Nonzero if this section has TLS related relocations. */
#define has_tls_reloc sec_flg0
/* Nonzero if this section has a call to __tls_get_addr. */
#define has_tls_get_addr_call sec_flg1
/* Get the PPC ELF linker hash table from a link_info structure. */
#define ppc_elf_hash_table(p) \
@ -3620,10 +4020,21 @@ ppc_elf_check_relocs (bfd *abfd,
}
break;
case R_PPC_VLE_SDAREL_LO16A:
case R_PPC_VLE_SDAREL_LO16D:
case R_PPC_VLE_SDAREL_HI16A:
case R_PPC_VLE_SDAREL_HI16D:
case R_PPC_VLE_SDAREL_HA16A:
case R_PPC_VLE_SDAREL_HA16D:
case R_PPC_SDAREL16:
if (htab->sdata[0].sym == NULL
&& !create_sdata_sym (info, &htab->sdata[0]))
return FALSE;
if (htab->sdata[1].sym == NULL
&& !create_sdata_sym (info, &htab->sdata[1]))
return FALSE;
if (h != NULL)
{
ppc_elf_hash_entry (h)->has_sda_refs = TRUE;
@ -3631,6 +4042,17 @@ ppc_elf_check_relocs (bfd *abfd,
}
break;
case R_PPC_VLE_REL8:
case R_PPC_VLE_REL15:
case R_PPC_VLE_REL24:
case R_PPC_VLE_LO16A:
case R_PPC_VLE_LO16D:
case R_PPC_VLE_HI16A:
case R_PPC_VLE_HI16D:
case R_PPC_VLE_HA16A:
case R_PPC_VLE_HA16D:
break;
case R_PPC_EMB_SDA2REL:
if (info->shared)
{
@ -3647,6 +4069,8 @@ ppc_elf_check_relocs (bfd *abfd,
}
break;
case R_PPC_VLE_SDA21_LO:
case R_PPC_VLE_SDA21:
case R_PPC_EMB_SDA21:
case R_PPC_EMB_RELSDA:
if (info->shared)
@ -4244,6 +4668,24 @@ ppc_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd)
return TRUE;
}
static void
ppc_elf_vle_split16 (bfd *output_bfd, bfd_byte *contents,
bfd_vma offset, bfd_vma relocation,
split16_format_type split16_format)
{
bfd_vma insn, top5, bottom11;
insn = bfd_get_32 (output_bfd, contents + offset);
top5 = relocation >> 11;
top5 = top5 << (split16_format == split16a_type ? 20 : 16);
bottom11 = relocation & 0x7ff;
insn |= top5;
insn |= bottom11;
bfd_put_32 (output_bfd, insn, contents + offset);
}
/* Choose which PLT scheme to use, and set .plt flags appropriately.
Returns -1 on error, 0 for old PLT, 1 for new PLT. */
@ -7611,6 +8053,9 @@ ppc_elf_relocate_section (bfd *output_bfd,
case R_PPC_UADDR16:
goto dodyn;
case R_PPC_VLE_REL8:
case R_PPC_VLE_REL15:
case R_PPC_VLE_REL24:
case R_PPC_REL24:
case R_PPC_REL14:
case R_PPC_REL14_BRTAKEN:
@ -7984,9 +8429,53 @@ ppc_elf_relocate_section (bfd *output_bfd,
}
break;
case R_PPC_VLE_LO16A:
relocation = (relocation + addend) & 0xffff;
ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
relocation, split16a_type);
continue;
case R_PPC_VLE_LO16D:
relocation = (relocation + addend) & 0xffff;
ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
relocation, split16d_type);
continue;
case R_PPC_VLE_HI16A:
relocation = ((relocation + addend) >> 16) & 0xffff;
ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
relocation, split16a_type);
continue;
case R_PPC_VLE_HI16D:
relocation = ((relocation + addend) >> 16) & 0xffff;
ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
relocation, split16d_type);
continue;
case R_PPC_VLE_HA16A:
{
bfd_vma value = relocation + addend;
value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
value, split16a_type);
}
continue;
case R_PPC_VLE_HA16D:
{
bfd_vma value = relocation + addend;
value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
value, split16d_type);
}
continue;
/* Relocate against either _SDA_BASE_, _SDA2_BASE_, or 0. */
case R_PPC_EMB_SDA21:
case R_PPC_VLE_SDA21:
case R_PPC_EMB_RELSDA:
case R_PPC_VLE_SDA21_LO:
{
const char *name;
int reg;
@ -8043,7 +8532,25 @@ ppc_elf_relocate_section (bfd *output_bfd,
addend -= SYM_VAL (sda);
}
if (r_type == R_PPC_EMB_SDA21)
if (reg == 0
&& (r_type == R_PPC_VLE_SDA21
|| r_type == R_PPC_VLE_SDA21_LO))
{
/* Use the split20 format. */
bfd_vma insn, bits12to15, bits21to31;
bfd_vma value = (relocation + rel->r_offset) & 0xffff;
/* Propagate sign bit, if necessary. */
insn = (value & 0x8000) ? 0x70107800 : 0x70000000;
bits12to15 = value & 0x700;
bits21to31 = value & 0x7ff;
insn |= bits12to15;
insn |= bits21to31;
bfd_put_32 (output_bfd, insn, contents + rel->r_offset);
continue;
}
else if (r_type == R_PPC_EMB_SDA21
|| r_type == R_PPC_VLE_SDA21
|| r_type == R_PPC_VLE_SDA21_LO)
{
bfd_vma insn; /* Fill in register field. */
@ -8054,6 +8561,107 @@ ppc_elf_relocate_section (bfd *output_bfd,
}
break;
case R_PPC_VLE_SDAREL_LO16A:
case R_PPC_VLE_SDAREL_LO16D:
case R_PPC_VLE_SDAREL_HI16A:
case R_PPC_VLE_SDAREL_HI16D:
case R_PPC_VLE_SDAREL_HA16A:
case R_PPC_VLE_SDAREL_HA16D:
{
bfd_vma value;
const char *name;
//int reg;
struct elf_link_hash_entry *sda = NULL;
if (sec == NULL || sec->output_section == NULL)
{
unresolved_reloc = TRUE;
break;
}
name = bfd_get_section_name (abfd, sec->output_section);
if (((CONST_STRNEQ (name, ".sdata")
&& (name[6] == 0 || name[6] == '.'))
|| (CONST_STRNEQ (name, ".sbss")
&& (name[5] == 0 || name[5] == '.'))))
{
//reg = 13;
sda = htab->sdata[0].sym;
}
else if (CONST_STRNEQ (name, ".sdata2")
|| CONST_STRNEQ (name, ".sbss2"))
{
//reg = 2;
sda = htab->sdata[1].sym;
}
else
{
(*_bfd_error_handler)
(_("%B: the target (%s) of a %s relocation is "
"in the wrong output section (%s)"),
input_bfd,
sym_name,
howto->name,
name);
bfd_set_error (bfd_error_bad_value);
ret = FALSE;
continue;
}
if (sda != NULL)
{
if (!is_static_defined (sda))
{
unresolved_reloc = TRUE;
break;
}
}
value = sda->root.u.def.section->output_section->vma
+ sda->root.u.def.section->output_offset;
if (r_type == R_PPC_VLE_SDAREL_LO16A)
{
value = (value + addend) & 0xffff;
ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
value, split16a_type);
}
else if (r_type == R_PPC_VLE_SDAREL_LO16D)
{
value = (value + addend) & 0xffff;
ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
value, split16d_type);
}
else if (r_type == R_PPC_VLE_SDAREL_HI16A)
{
value = ((value + addend) >> 16) & 0xffff;
ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
value, split16a_type);
}
else if (r_type == R_PPC_VLE_SDAREL_HI16D)
{
value = ((value + addend) >> 16) & 0xffff;
ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
value, split16d_type);
}
else if (r_type == R_PPC_VLE_SDAREL_HA16A)
{
value += addend;
value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
value, split16a_type);
}
else if (r_type == R_PPC_VLE_SDAREL_HA16D)
{
value += addend;
value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
value, split16d_type);
}
}
continue;
/* Relocate against the beginning of the section. */
case R_PPC_SECTOFF:
case R_PPC_SECTOFF_LO:
@ -9092,7 +9700,7 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
#define bfd_elf32_bfd_merge_private_bfd_data ppc_elf_merge_private_bfd_data
#define bfd_elf32_bfd_relax_section ppc_elf_relax_section
#define bfd_elf32_bfd_reloc_type_lookup ppc_elf_reloc_type_lookup
#define bfd_elf32_bfd_reloc_name_lookup ppc_elf_reloc_name_lookup
#define bfd_elf32_bfd_reloc_name_lookup ppc_elf_reloc_name_lookup
#define bfd_elf32_bfd_set_private_flags ppc_elf_set_private_flags
#define bfd_elf32_bfd_link_hash_table_create ppc_elf_link_hash_table_create
#define bfd_elf32_get_synthetic_symtab ppc_elf_get_synthetic_symtab
@ -9113,6 +9721,7 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
#define elf_backend_finish_dynamic_sections ppc_elf_finish_dynamic_sections
#define elf_backend_fake_sections ppc_elf_fake_sections
#define elf_backend_additional_program_headers ppc_elf_additional_program_headers
#define elf_backend_modify_segment_map ppc_elf_modify_segment_map
#define elf_backend_grok_prstatus ppc_elf_grok_prstatus
#define elf_backend_grok_psinfo ppc_elf_grok_psinfo
#define elf_backend_write_core_note ppc_elf_write_core_note
@ -9125,6 +9734,9 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
#define elf_backend_action_discarded ppc_elf_action_discarded
#define elf_backend_init_index_section _bfd_elf_init_1_index_section
#define elf_backend_post_process_headers _bfd_elf_set_osabi
#define elf_backend_lookup_section_flags_hook ppc_elf_lookup_section_flags
#define elf_backend_section_flags ppc_elf_section_flags
#define elf_backend_section_processing ppc_elf_section_processing
#include "elf32-target.h"

4
bfd/elf32-ppc.h
View file

@ -26,8 +26,12 @@ enum ppc_elf_plt_type
PLT_VXWORKS
};
bfd_boolean is_ppc_vle (asection *);
int ppc_elf_select_plt_layout (bfd *, struct bfd_link_info *,
enum ppc_elf_plt_type, int);
asection *ppc_elf_tls_setup (bfd *, struct bfd_link_info *, int);
bfd_boolean ppc_elf_tls_optimize (bfd *, struct bfd_link_info *);
void ppc_elf_set_sdata_syms (bfd *, struct bfd_link_info *);
extern bfd_boolean ppc_elf_modify_segment_map (bfd *,
struct bfd_link_info * ATTRIBUTE_UNUSED);
extern bfd_boolean ppc_elf_section_processing (bfd *, Elf_Internal_Shdr *);

110
bfd/elflink.c
View file

@ -12220,58 +12220,84 @@ static elf_flags_to_name_table elf_flags_to_names [] =
{ "SHF_EXCLUDE", SHF_EXCLUDE },
};
void
/* Returns TRUE if the section is to be included, otherwise FALSE. */
bfd_boolean
bfd_elf_lookup_section_flags (struct bfd_link_info *info,
struct flag_info *flaginfo)
struct flag_info *finfo,
asection *section)
{
bfd *output_bfd = info->output_bfd;
const struct elf_backend_data *bed = get_elf_backend_data (output_bfd);
struct flag_info_list *tf = flaginfo->flag_list;
int with_hex = 0;
int without_hex = 0;
const bfd_vma sh_flags = elf_section_flags(section);
for (tf = flaginfo->flag_list; tf != NULL; tf = tf->next)
if (finfo->flags_initialized == FALSE)
{
int i;
if (bed->elf_backend_lookup_section_flags_hook)
{
flagword hexval =
(*bed->elf_backend_lookup_section_flags_hook) ((char *) tf->name);
const struct elf_backend_data *bed =
get_elf_backend_data (info->output_bfd);
struct flag_info_list *tf = finfo->flag_list;
int with_hex = 0;
int without_hex = 0;
if (hexval != 0)
for (tf = finfo->flag_list; tf != NULL; tf = tf->next)
{
unsigned i;
if (bed->elf_backend_lookup_section_flags_hook)
{
if (tf->with == with_flags)
with_hex |= hexval;
else if (tf->with == without_flags)
without_hex |= hexval;
tf->valid = TRUE;
continue;
flagword hexval =
(*bed->elf_backend_lookup_section_flags_hook) ((char*)tf->name);
if (hexval != 0)
{
if (tf->with == with_flags)
with_hex |= hexval;
else if (tf->with == without_flags)
without_hex |= hexval;
tf->valid = TRUE;
continue;
}
}
for (i = 0;
i < sizeof(elf_flags_to_names) / sizeof(elf_flags_to_name_table);
++i)
{
if (!strcmp (tf->name, elf_flags_to_names[i].flag_name))
{
if (tf->with == with_flags)
with_hex |= elf_flags_to_names[i].flag_value;
else if (tf->with == without_flags)
without_hex |= elf_flags_to_names[i].flag_value;
tf->valid = TRUE;
break;
}
}
if (tf->valid == FALSE)
{
info->callbacks->einfo
(_("Unrecognized INPUT_SECTION_FLAG %s\n"), tf->name);
return FALSE;
}
}
for (i = 0; i < 12; i++)
{
if (!strcmp (tf->name, elf_flags_to_names[i].flag_name))
{
if (tf->with == with_flags)
with_hex |= elf_flags_to_names[i].flag_value;
else if (tf->with == without_flags)
without_hex |= elf_flags_to_names[i].flag_value;
tf->valid = TRUE;
continue;
}
}
if (tf->valid == FALSE)
{
info->callbacks->einfo
(_("Unrecognized INPUT_SECTION_FLAG %s\n"), tf->name);
return;
}
finfo->flags_initialized = TRUE;
finfo->only_with_flags |= with_hex;
finfo->not_with_flags |= without_hex;
}
flaginfo->flags_initialized = TRUE;
flaginfo->only_with_flags |= with_hex;
flaginfo->not_with_flags |= without_hex;
return;
if (finfo->only_with_flags != 0
&& finfo->not_with_flags != 0
&& ((finfo->not_with_flags & sh_flags) != 0
|| (finfo->only_with_flags & sh_flags)
!= finfo->only_with_flags))
return FALSE;
if (finfo->only_with_flags != 0
&& (finfo->only_with_flags & sh_flags)
!= finfo->only_with_flags)
return FALSE;
if (finfo->not_with_flags != 0
&& (finfo->not_with_flags & sh_flags) != 0)
return FALSE;
return TRUE;
}
struct alloc_got_off_arg {

2
bfd/libbfd-in.h
View file

@ -459,7 +459,7 @@ extern bfd_boolean _bfd_generic_set_section_contents
((bfd_boolean (*) (bfd *, struct bfd_link_info *)) \
bfd_false)
#define _bfd_nolink_bfd_lookup_section_flags \
((void (*) (struct bfd_link_info *, struct flag_info *)) \
((bfd_boolean (*) (struct bfd_link_info *, struct flag_info *, asection *)) \
bfd_0)
#define _bfd_nolink_bfd_merge_sections \
((bfd_boolean (*) (bfd *, struct bfd_link_info *)) \

23
bfd/libbfd.h
View file

@ -464,7 +464,7 @@ extern bfd_boolean _bfd_generic_set_section_contents
((bfd_boolean (*) (bfd *, struct bfd_link_info *)) \
bfd_false)
#define _bfd_nolink_bfd_lookup_section_flags \
((void (*) (struct bfd_link_info *, struct flag_info *)) \
((bfd_boolean (*) (struct bfd_link_info *, struct flag_info *, asection *)) \
bfd_0)
#define _bfd_nolink_bfd_merge_sections \
((bfd_boolean (*) (bfd *, struct bfd_link_info *)) \
@ -1343,6 +1343,23 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_PPC_EMB_RELST_HA",
"BFD_RELOC_PPC_EMB_BIT_FLD",
"BFD_RELOC_PPC_EMB_RELSDA",
"BFD_RELOC_PPC_VLE_REL8",
"BFD_RELOC_PPC_VLE_REL15",
"BFD_RELOC_PPC_VLE_REL24",
"BFD_RELOC_PPC_VLE_LO16A",
"BFD_RELOC_PPC_VLE_LO16D",
"BFD_RELOC_PPC_VLE_HI16A",
"BFD_RELOC_PPC_VLE_HI16D",
"BFD_RELOC_PPC_VLE_HA16A",
"BFD_RELOC_PPC_VLE_HA16D",
"BFD_RELOC_PPC_VLE_SDA21",
"BFD_RELOC_PPC_VLE_SDA21_LO",
"BFD_RELOC_PPC_VLE_SDAREL_LO16A",
"BFD_RELOC_PPC_VLE_SDAREL_LO16D",
"BFD_RELOC_PPC_VLE_SDAREL_HI16A",
"BFD_RELOC_PPC_VLE_SDAREL_HI16D",
"BFD_RELOC_PPC_VLE_SDAREL_HA16A",
"BFD_RELOC_PPC_VLE_SDAREL_HA16D",
"BFD_RELOC_PPC64_HIGHER",
"BFD_RELOC_PPC64_HIGHER_S",
"BFD_RELOC_PPC64_HIGHEST",
@ -2586,8 +2603,8 @@ bfd_boolean bfd_generic_relax_section
bfd_boolean bfd_generic_gc_sections
(bfd *, struct bfd_link_info *);
void bfd_generic_lookup_section_flags
(struct bfd_link_info *, struct flag_info *);
bfd_boolean bfd_generic_lookup_section_flags
(struct bfd_link_info *, struct flag_info *, asection *);
bfd_boolean bfd_generic_merge_sections
(bfd *, struct bfd_link_info *);

47
bfd/reloc.c
View file

@ -2805,6 +2805,40 @@ ENUMX
BFD_RELOC_PPC_EMB_BIT_FLD
ENUMX
BFD_RELOC_PPC_EMB_RELSDA
ENUMX
BFD_RELOC_PPC_VLE_REL8
ENUMX
BFD_RELOC_PPC_VLE_REL15
ENUMX
BFD_RELOC_PPC_VLE_REL24
ENUMX
BFD_RELOC_PPC_VLE_LO16A
ENUMX
BFD_RELOC_PPC_VLE_LO16D
ENUMX
BFD_RELOC_PPC_VLE_HI16A
ENUMX
BFD_RELOC_PPC_VLE_HI16D
ENUMX
BFD_RELOC_PPC_VLE_HA16A
ENUMX
BFD_RELOC_PPC_VLE_HA16D
ENUMX
BFD_RELOC_PPC_VLE_SDA21
ENUMX
BFD_RELOC_PPC_VLE_SDA21_LO
ENUMX
BFD_RELOC_PPC_VLE_SDAREL_LO16A
ENUMX
BFD_RELOC_PPC_VLE_SDAREL_LO16D
ENUMX
BFD_RELOC_PPC_VLE_SDAREL_HI16A
ENUMX
BFD_RELOC_PPC_VLE_SDAREL_HI16D
ENUMX
BFD_RELOC_PPC_VLE_SDAREL_HA16A
ENUMX
BFD_RELOC_PPC_VLE_SDAREL_HA16D
ENUMX
BFD_RELOC_PPC64_HIGHER
ENUMX
@ -6349,23 +6383,26 @@ INTERNAL_FUNCTION
bfd_generic_lookup_section_flags
SYNOPSIS
void bfd_generic_lookup_section_flags
(struct bfd_link_info *, struct flag_info *);
bfd_boolean bfd_generic_lookup_section_flags
(struct bfd_link_info *, struct flag_info *, asection *);
DESCRIPTION
Provides default handling for section flags lookup
-- i.e., does nothing.
Returns FALSE if the section should be omitted, otherwise TRUE.
*/
void
bfd_boolean
bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
struct flag_info *flaginfo)
struct flag_info *flaginfo,
asection *section ATTRIBUTE_UNUSED)
{
if (flaginfo != NULL)
{
(*_bfd_error_handler) (_("INPUT_SECTION_FLAGS are not supported.\n"));
return;
return FALSE;
}
return TRUE;
}
/*

6
bfd/section.c
View file

@ -517,9 +517,6 @@ CODE_FRAGMENT
. {* The BFD which owns the section. *}
. bfd *owner;
.
. {* INPUT_SECTION_FLAGS if specified in the linker script. *}
. struct flag_info *section_flag_info;
.
. {* A symbol which points at this section only. *}
. struct bfd_symbol *symbol;
. struct bfd_symbol **symbol_ptr_ptr;
@ -695,9 +692,6 @@ CODE_FRAGMENT
. {* target_index, used_by_bfd, constructor_chain, owner, *} \
. 0, NULL, NULL, NULL, \
. \
. {* flag_info, *} \
. NULL, \
. \
. {* symbol, symbol_ptr_ptr, *} \
. (struct bfd_symbol *) SYM, &SEC.symbol, \
. \

5
bfd/targets.c
View file

@ -497,8 +497,9 @@ BFD_JUMP_TABLE macros.
. bfd_boolean (*_bfd_gc_sections) (bfd *, struct bfd_link_info *);
.
. {* Sets the bitmask of allowed and disallowed section flags. *}
. void (*_bfd_lookup_section_flags) (struct bfd_link_info *,
. struct flag_info *);
. bfd_boolean (*_bfd_lookup_section_flags) (struct bfd_link_info *,
. struct flag_info *,
. asection *);
.
. {* Attempt to merge SEC_MERGE sections. *}
. bfd_boolean (*_bfd_merge_sections) (bfd *, struct bfd_link_info *);

2
binutils/NEWS
View file

@ -1,5 +1,7 @@
-*- text -*-
* Add support for the VLE extension to the PowerPC architecture.
* Add support for x64 Windows target of the delayed-load-library.
* Add support for the Renesas RL78 architecture.

2
binutils/dwarf.c
View file

@ -658,7 +658,7 @@ process_abbrev_section (unsigned char *start, unsigned char *end)
static const char *
get_TAG_name (unsigned long tag)
{
const char *name = get_DW_TAG_name (tag);
const char *name = get_DW_TAG_name ((unsigned int)tag);
if (name == NULL)
{

44
gas/ChangeLog
View file

@ -1,3 +1,47 @@
2012-05-14 James Lemke <jwlemke@codesourcery.com>
* config/tc-ppc.c (insn_validate): New func of existing code to call..
(ppc_setup_opcodes): ..from 2 places here.
Revise for second (VLE) opcode table.
Add #ifdef'd code to print opcode tables.
2012-05-14 James Lemke <jwlemke@codesourcery.com>
* config/tc-ppc.c (ppc_setup_opcodes): Allow out-of-order
for the VLE conditional branches.
2012-05-14 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Rhonda Wittels <rhonda@codesourcery.com>
* config/tc-ppc.c (PPC_VLE_SPLIT16A): New macro.
(PPC_VLE_SPLIT16D): New macro.
(PPC_VLE_LO16A): New macro.
(PPC_VLE_LO16D): New macro.
(PPC_VLE_HI16A): New macro.
(PPC_VLE_HI16D): New macro.
(PPC_VLE_HA16A): New macro.
(PPC_VLE_HA16D): New macro.
(PPC_APUINFO_VLE): New definition.
(md_chars_to_number): New function.
(md_parse_option): Check for combinations of little
endian and -mvle.
(md_show_usage): Document -mvle.
(ppc_arch): Recognize VLE.
(ppc_mach): Recognize bfd_mach_ppc_vle.
(ppc_setup_opcodes): Print the opcode table if
* config/tc-ppc.h (ppc_frag_check): Declare.
* doc/c-ppc.texi: Document -mvle.
* NEWS: Mention PowerPC VLE port.
2012-05-14 Catherine Moore <clm@codesourcery.com>
* config/tc-ppc.h (ppc_dw2_line_min_insn_length): Declare.
(DWARF2_LINE_MIN_INSN_LENGTH): Redefine.
* config/tc-ppc.c (ppc_dw2_line_min_insn_length): New.
* dwarf2dbg.c (scale_addr_delta): Handle values of 1
for DWARF2_LINE_MIN_INSN_LENGTH.
2012-05-12 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (tc_gen_reloc): Remove x32 addend overflow

2
gas/NEWS
View file

@ -1,5 +1,7 @@
-*- text -*-
* Add support for the VLE extension to the PowerPC architecture.
* Add support for the Freescale XGATE architecture.
* Add support for .bundle_align_mode, .bundle_lock, and .bundle_unlock

557
gas/config/tc-ppc.c
View file

@ -64,14 +64,40 @@ static int set_target_endian = 0;
/* #lo(value) denotes the least significant 16 bits of the indicated. */
#define PPC_LO(v) ((v) & 0xffff)
/* Split the indicated value with the msbs in bits 11-15
and the lsbs in bits 21-31. */
#define PPC_VLE_SPLIT16A(v) ((v & 0xf800) << 11) | (v & 0x7ff)
/* Split the indicated value with the msbs in bits 6-10
and the lsbs in bits 21-31. */
#define PPC_VLE_SPLIT16D(v) ((v & 0xf800) << 5) | (v & 0x7ff)
/* #lo(value) denotes the lsb 16 bits in split16a format. */
#define PPC_VLE_LO16A(v) PPC_VLE_SPLIT16A(PPC_LO(v))
/* #lo(value) denotes the lsb 16 bits in split16d format. */
#define PPC_VLE_LO16D(v) PPC_VLE_SPLIT16D(PPC_LO(v))
/* #hi(value) denotes bits 16 through 31 of the indicated value. */
#define PPC_HI(v) (((v) >> 16) & 0xffff)
/* #lo(value) denotes the msb 16 bits in split16a format. */
#define PPC_VLE_HI16A(v) PPC_VLE_SPLIT16A(PPC_HI(v))
/* #lo(value) denotes the msb 16 bits in split16d format. */
#define PPC_VLE_HI16D(v) PPC_VLE_SPLIT16D(PPC_HI(v))
/* #ha(value) denotes the high adjusted value: bits 16 through 31 of
the indicated value, compensating for #lo() being treated as a
signed number. */
#define PPC_HA(v) PPC_HI ((v) + 0x8000)
/* #ha(value) denotes the high adjusted value in split16a format. */
#define PPC_VLE_HA16A(v) PPC_VLE_SPLIT16A(PPC_HA(v))
/* #ha(value) denotes the high adjusted value in split16d format. */
#define PPC_VLE_HA16D(v) PPC_VLE_SPLIT16D(PPC_HA(v))
/* #higher(value) denotes bits 32 through 47 of the indicated value. */
#define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff)
@ -1038,6 +1064,7 @@ symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */
#define PPC_APUINFO_SPE 0x100
#define PPC_APUINFO_EFS 0x101
#define PPC_APUINFO_BRLOCK 0x102
#define PPC_APUINFO_VLE 0x104
/*
* We keep a list of APUinfo
@ -1059,6 +1086,35 @@ const struct option md_longopts[] = {
};
const size_t md_longopts_size = sizeof (md_longopts);
/* Convert the target integer stored in N bytes in BUF to a host
integer, returning that value. */
static valueT
md_chars_to_number (char *buf, int n)
{
valueT result = 0;
unsigned char *p = (unsigned char *) buf;
if (target_big_endian)
{
while (n--)
{
result <<= 8;
result |= (*p++ & 0xff);
}
}
else
{
while (n--)
{
result <<= 8;
result |= (p[n] & 0xff);
}
}
return result;
}
int
md_parse_option (int c, char *arg)
{
@ -1079,6 +1135,8 @@ md_parse_option (int c, char *arg)
{
target_big_endian = 0;
set_target_endian = 1;
if (ppc_cpu & PPC_OPCODE_VLE)
as_bad (_("The use of -mvle requires big endian."));
}
else
return 0;
@ -1126,8 +1184,13 @@ md_parse_option (int c, char *arg)
break;
case 'm':
if ((new_cpu = ppc_parse_cpu (ppc_cpu, arg)) != 0)
ppc_cpu = new_cpu;
new_cpu = ppc_parse_cpu (ppc_cpu, arg);
if (new_cpu != 0)
{
ppc_cpu = new_cpu;
if (set_target_endian && target_big_endian == 0)
as_bad (_("The use of -mvle requires big endian."));
}
else if (strcmp (arg, "regnames") == 0)
reg_names_p = TRUE;
@ -1160,6 +1223,8 @@ md_parse_option (int c, char *arg)
{
target_big_endian = 0;
set_target_endian = 1;
if (ppc_cpu & PPC_OPCODE_VLE)
as_bad (_("The use of -mvle requires big endian."));
}
else if (strcmp (arg, "big") == 0 || strcmp (arg, "big-endian") == 0)
@ -1268,6 +1333,7 @@ PowerPC options:\n\
-me5500, generate code for Freescale e5500 core complex\n\
-me6500, generate code for Freescale e6500 core complex\n\
-mspe generate code for Motorola SPE instructions\n\
-mvle generate code for Freescale VLE instructions\n\
-mtitan generate code for AppliedMicro Titan core complex\n\
-mregnames Allow symbolic names for registers\n\
-mno-regnames Do not allow symbolic names for registers\n"));
@ -1328,9 +1394,11 @@ ppc_arch (void)
if ((ppc_cpu & PPC_OPCODE_PPC) != 0)
return bfd_arch_powerpc;
else if ((ppc_cpu & PPC_OPCODE_POWER) != 0)
if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
return bfd_arch_powerpc;
if ((ppc_cpu & PPC_OPCODE_POWER) != 0)
return bfd_arch_rs6000;
else if ((ppc_cpu & (PPC_OPCODE_COMMON | PPC_OPCODE_ANY)) != 0)
if ((ppc_cpu & (PPC_OPCODE_COMMON | PPC_OPCODE_ANY)) != 0)
{
if (strcmp (default_cpu, "rs6000") == 0)
return bfd_arch_rs6000;
@ -1351,6 +1419,8 @@ ppc_mach (void)
return bfd_mach_rs6k;
else if (ppc_cpu & PPC_OPCODE_TITAN)
return bfd_mach_ppc_titan;
else if (ppc_cpu & PPC_OPCODE_VLE)
return bfd_mach_ppc_vle;
else
return bfd_mach_ppc;
}
@ -1384,6 +1454,54 @@ ppc_target_format (void)
#endif
}
/* Validate one entry in powerpc_opcodes[] or vle_opcodes[].
Return TRUE if there's a problem, otherwise FALSE. */
static bfd_boolean
insn_validate (const struct powerpc_opcode *op)
{
const unsigned char *o;
unsigned long omask = op->mask;
/* The mask had better not trim off opcode bits. */
if ((op->opcode & omask) != op->opcode)
{
as_bad (_("mask trims opcode bits for %s"), op->name);
return TRUE;
}
/* The operands must not overlap the opcode or each other. */
for (o = op->operands; *o; ++o)
{
if (*o >= num_powerpc_operands)
{
as_bad (_("operand index error for %s"), op->name);
return TRUE;
}
else
{
const struct powerpc_operand *operand = &powerpc_operands[*o];
if (operand->shift != PPC_OPSHIFT_INV)
{
unsigned long mask;
if (operand->shift >= 0)
mask = operand->bitm << operand->shift;
else
mask = operand->bitm >> -operand->shift;
if (omask & mask)
{
as_bad (_("operand %d overlap in %s"),
(int) (o - op->operands), op->name);
return TRUE;
}
omask |= mask;
}
}
}
return FALSE;
}
/* Insert opcodes and macros into hash tables. Called at startup and
for .cpu pseudo. */
@ -1440,89 +1558,29 @@ ppc_setup_opcodes (void)
{
if (ENABLE_CHECKING)
{
const unsigned char *o;
unsigned long omask = op->mask;
if (op != powerpc_opcodes)
{
int old_opcode = PPC_OP (op[-1].opcode);
int new_opcode = PPC_OP (op[0].opcode);
#ifdef PRINT_OPCODE_TABLE
printf ("%-14s\t#%04d\tmajor op: 0x%x\top: 0x%x\tmask: 0x%x\tflags: 0x%llx\n",
op->name, op - powerpc_opcodes, (unsigned int) new_opcode,
(unsigned int) op->opcode, (unsigned int) op->mask,
(unsigned long long) op->flags);
#endif
/* The major opcodes had better be sorted. Code in the
disassembler assumes the insns are sorted according to
major opcode. */
if (PPC_OP (op[0].opcode) < PPC_OP (op[-1].opcode))
if (new_opcode < old_opcode)
{
as_bad (_("major opcode is not sorted for %s"),
op->name);
bad_insn = TRUE;
}
/* Warn if the table isn't more strictly ordered.
Unfortunately it doesn't seem possible to order the
table on much more than the major opcode, which makes
it difficult to implement a binary search in the
disassembler. The problem is that we have multiple
ways to disassemble instructions, and we usually want
to choose a more specific form (with more bits set in
the opcode) than a more general form. eg. all of the
following are equivalent:
bne label # opcode = 0x40820000, mask = 0xff830003
bf 2,label # opcode = 0x40800000, mask = 0xff800003
bc 4,2,label # opcode = 0x40000000, mask = 0xfc000003
There are also cases where the table needs to be out
of order to disassemble the correct instruction for
processor variants. */
else if (0)
{
unsigned long t1 = op[0].opcode;
unsigned long t2 = op[-1].opcode;
if (((t1 ^ t2) & 0xfc0007ff) == 0
&& (t1 & 0xfc0006df) == 0x7c000286)
{
/* spr field is split. */
t1 = ((t1 & ~0x1ff800)
| ((t1 & 0xf800) << 5) | ((t1 & 0x1f0000) >> 5));
t2 = ((t2 & ~0x1ff800)
| ((t2 & 0xf800) << 5) | ((t2 & 0x1f0000) >> 5));
}
if (t1 < t2)
as_warn (_("%s (%08lx %08lx) after %s (%08lx %08lx)"),
op[0].name, op[0].opcode, op[0].mask,
op[-1].name, op[-1].opcode, op[-1].mask);
}
}
/* The mask had better not trim off opcode bits. */
if ((op->opcode & omask) != op->opcode)
{
as_bad (_("mask trims opcode bits for %s"),
op->name);
bad_insn = TRUE;
}
/* The operands must not overlap the opcode or each other. */
for (o = op->operands; *o; ++o)
if (*o >= num_powerpc_operands)
{
as_bad (_("operand index error for %s"),
op->name);
bad_insn = TRUE;
}
else
{
const struct powerpc_operand *operand = &powerpc_operands[*o];
if (operand->shift >= 0)
{
unsigned long mask = operand->bitm << operand->shift;
if (omask & mask)
{
as_bad (_("operand %d overlap in %s"),
(int) (o - op->operands), op->name);
bad_insn = TRUE;
}
omask |= mask;
}
}
bad_insn |= insn_validate (op);
}
if ((ppc_cpu & op->flags) != 0
@ -1544,6 +1602,59 @@ ppc_setup_opcodes (void)
for (op = powerpc_opcodes; op < op_end; op++)
hash_insert (ppc_hash, op->name, (void *) op);
op_end = vle_opcodes + vle_num_opcodes;
for (op = vle_opcodes; op < op_end; op++)
{
if (ENABLE_CHECKING)
{
if (op != vle_opcodes)
{
unsigned old_seg, new_seg;
old_seg = VLE_OP (op[-1].opcode, op[-1].mask);
old_seg = VLE_OP_TO_SEG (old_seg);
new_seg = VLE_OP (op[0].opcode, op[0].mask);
new_seg = VLE_OP_TO_SEG (new_seg);
#ifdef PRINT_OPCODE_TABLE
printf ("%-14s\t#%04d\tmajor op: 0x%x\top: 0x%x\tmask: 0x%x\tflags: 0x%llx\n",
op->name, op - powerpc_opcodes, (unsigned int) new_opcode,
(unsigned int) op->opcode, (unsigned int) op->mask,
(unsigned long long) op->flags);
#endif
/* The major opcodes had better be sorted. Code in the
disassembler assumes the insns are sorted according to
major opcode. */
if (new_seg < old_seg)
{
as_bad (_("major opcode is not sorted for %s"),
op->name);
bad_insn = TRUE;
}
}
bad_insn |= insn_validate (op);
}
if ((ppc_cpu & op->flags) != 0
&& !(ppc_cpu & op->deprecated))
{
const char *retval;
retval = hash_insert (ppc_hash, op->name, (void *) op);
if (retval != NULL)
{
as_bad (_("duplicate instruction %s"),
op->name);
bad_insn = TRUE;
}
}
}
if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
for (op = vle_opcodes; op < op_end; op++)
hash_insert (ppc_hash, op->name, (void *) op);
/* Insert the macros into a hash table. */
ppc_macro_hash = hash_new ();
@ -1743,8 +1854,10 @@ ppc_insert_operand (unsigned long insn,
if (errmsg != (const char *) NULL)
as_bad_where (file, line, "%s", errmsg);
}
else
else if (operand->shift >= 0)
insn |= ((long) val & operand->bitm) << operand->shift;
else
insn |= ((long) val & operand->bitm) >> -operand->shift;
return insn;
}
@ -1826,6 +1939,9 @@ ppc_elf_suffix (char **str_p, expressionS *exp_p)
MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC),
MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL),
MAP32 ("sdarel", BFD_RELOC_GPREL16),
MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A),
MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A),
MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A),
MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32),
MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16),
MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO),
@ -1835,6 +1951,7 @@ ppc_elf_suffix (char **str_p, expressionS *exp_p)
MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL),
MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16),
MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21),
MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO),
MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF),
MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16),
MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO),
@ -2371,6 +2488,22 @@ struct ppc_fixup
#define MAX_INSN_FIXUPS (5)
/* Form I16L. */
#define E_OR2I_INSN 0x7000C000
#define E_AND2I_DOT_INSN 0x7000C800
#define E_OR2IS_INSN 0x7000D000
#define E_LIS_INSN 0x7000E000
#define E_AND2IS_DOT_INSN 0x7000E800
/* Form I16A. */
#define E_ADD2I_DOT_INSN 0x70008800
#define E_ADD2IS_INSN 0x70009000
#define E_CMP16I_INSN 0x70009800
#define E_MULL2I_INSN 0x7000A000
#define E_CMPL16I_INSN 0x7000A800
#define E_CMPH16I_INSN 0x7000B000
#define E_CMPHL16I_INSN 0x7000B800
/* This routine is called for each instruction to be assembled. */
void
@ -2388,6 +2521,7 @@ md_assemble (char *str)
char *f;
int addr_mod;
int i;
unsigned int insn_length;
#ifdef OBJ_ELF
bfd_reloc_code_real_type reloc;
#endif
@ -2637,12 +2771,15 @@ md_assemble (char *str)
else
#endif /* TE_PE */
{
if ((reg_names_p && (operand->flags & PPC_OPERAND_CR) != 0)
if ((reg_names_p
&& (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
|| ((operand->flags & PPC_OPERAND_CR_REG) != 0)))
|| !register_name (&ex))
{
char save_lex = lex_type['%'];
if ((operand->flags & PPC_OPERAND_CR) != 0)
if (((operand->flags & PPC_OPERAND_CR_REG) != 0)
|| (operand->flags & PPC_OPERAND_CR_BIT) != 0)
{
cr_operand = TRUE;
lex_type['%'] |= LEX_BEGIN_NAME;
@ -2810,6 +2947,73 @@ md_assemble (char *str)
break;
}
/* If VLE-mode convert LO/HI/HA relocations. */
if (opcode->flags & PPC_OPCODE_VLE)
{
int tmp_insn = insn & opcode->mask;
int use_d_reloc = (tmp_insn == E_OR2I_INSN
|| tmp_insn == E_AND2I_DOT_INSN
|| tmp_insn == E_OR2IS_INSN
|| tmp_insn == E_LIS_INSN
|| tmp_insn == E_AND2IS_DOT_INSN);
int use_a_reloc = (tmp_insn == E_ADD2I_DOT_INSN
|| tmp_insn == E_ADD2IS_INSN
|| tmp_insn == E_CMP16I_INSN
|| tmp_insn == E_MULL2I_INSN
|| tmp_insn == E_CMPL16I_INSN
|| tmp_insn == E_CMPH16I_INSN
|| tmp_insn == E_CMPHL16I_INSN);
switch (reloc)
{
default:
break;
case BFD_RELOC_PPC_EMB_SDA21:
reloc = BFD_RELOC_PPC_VLE_SDA21;
break;
case BFD_RELOC_LO16:
if (use_d_reloc)
reloc = BFD_RELOC_PPC_VLE_LO16D;
else if (use_a_reloc)
reloc = BFD_RELOC_PPC_VLE_LO16A;
break;
case BFD_RELOC_HI16:
if (use_d_reloc)
reloc = BFD_RELOC_PPC_VLE_HI16D;
else if (use_a_reloc)
reloc = BFD_RELOC_PPC_VLE_HI16A;
break;
case BFD_RELOC_HI16_S:
if (use_d_reloc)
reloc = BFD_RELOC_PPC_VLE_HA16D;
else if (use_a_reloc)
reloc = BFD_RELOC_PPC_VLE_HA16A;
break;
case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
if (use_d_reloc)
reloc = BFD_RELOC_PPC_VLE_SDAREL_LO16D;
break;
case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
if (use_d_reloc)
reloc = BFD_RELOC_PPC_VLE_SDAREL_HI16D;
break;
case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
if (use_d_reloc)
reloc = BFD_RELOC_PPC_VLE_SDAREL_HA16D;
break;
}
}
/* For the absolute forms of branches, convert the PC
relative form back into the absolute. */
if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
@ -2974,8 +3178,8 @@ md_assemble (char *str)
as_bad (_("junk at end of line: `%s'"), str);
#ifdef OBJ_ELF
/* Do we need/want a APUinfo section? */
if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC)) != 0)
/* Do we need/want an APUinfo section? */
if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_VLE)) != 0)
{
/* These are all version "1". */
if (opcode->flags & PPC_OPCODE_SPE)
@ -2992,20 +3196,41 @@ md_assemble (char *str)
ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK, 1);
if (opcode->flags & PPC_OPCODE_RFMCI)
ppc_apuinfo_section_add (PPC_APUINFO_RFMCI, 1);
if (opcode->flags & PPC_OPCODE_VLE)
ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1);
}
#endif
/* Write out the instruction. */
f = frag_more (4);
addr_mod = frag_now_fix () & 3;
/* Differentiate between two and four byte insns. */
if (ppc_mach () == bfd_mach_ppc_vle)
{
if (PPC_OP_SE_VLE (insn))
insn_length = 2;
else
insn_length = 4;
addr_mod = frag_now_fix () & 1;
}
else
{
insn_length = 4;
addr_mod = frag_now_fix () & 3;
}
/* All instructions can start on a 2 byte boundary for VLE. */
f = frag_more (insn_length);
if (frag_now->has_code && frag_now->insn_addr != addr_mod)
as_bad (_("instruction address is not a multiple of 4"));
{
if (ppc_mach() == bfd_mach_ppc_vle)
as_bad (_("instruction address is not a multiple of 2"));
else
as_bad (_("instruction address is not a multiple of 4"));
}
frag_now->insn_addr = addr_mod;
frag_now->has_code = 1;
md_number_to_chars (f, insn, 4);
md_number_to_chars (f, insn, insn_length);
#ifdef OBJ_ELF
dwarf2_emit_insn (4);
dwarf2_emit_insn (insn_length);
#endif
/* Create any fixups. At this point we do not use a
@ -3049,6 +3274,12 @@ md_assemble (char *str)
case BFD_RELOC_LO16:
case BFD_RELOC_HI16:
case BFD_RELOC_HI16_S:
case BFD_RELOC_PPC_VLE_LO16A:
case BFD_RELOC_PPC_VLE_LO16D:
case BFD_RELOC_PPC_VLE_HI16A:
case BFD_RELOC_PPC_VLE_HI16D:
case BFD_RELOC_PPC_VLE_HA16A:
case BFD_RELOC_PPC_VLE_HA16D:
#ifdef OBJ_ELF
case BFD_RELOC_PPC64_HIGHER:
case BFD_RELOC_PPC64_HIGHER_S:
@ -3068,7 +3299,7 @@ md_assemble (char *str)
operand = &powerpc_operands[fixups[i].opindex];
fix_new_exp (frag_now,
f - frag_now->fr_literal,
4,
insn_length,
&fixups[i].exp,
(operand->flags & PPC_OPERAND_RELATIVE) != 0,
((bfd_reloc_code_real_type)
@ -5953,6 +6184,24 @@ ppc_fix_adjustable (fixS *fix)
}
#endif
void
ppc_frag_check (struct frag *fragP)
{
if (!fragP->has_code)
return;
if (ppc_mach() == bfd_mach_ppc_vle)
{
if (((fragP->fr_address + fragP->insn_addr) & 1) != 0)
as_bad (_("instruction address is not a multiple of 2"));
}
else
{
if (((fragP->fr_address + fragP->insn_addr) & 3) != 0)
as_bad (_("instruction address is not a multiple of 4"));
}
}
/* Implement HANDLE_ALIGN. This writes the NOP pattern into an
rs_align_code frag. */
@ -5962,7 +6211,14 @@ ppc_handle_align (struct frag *fragP)
valueT count = (fragP->fr_next->fr_address
- (fragP->fr_address + fragP->fr_fix));
if (count != 0 && (count & 3) == 0)
if (ppc_mach() == bfd_mach_ppc_vle && count != 0 && (count & 1) == 0)
{
char *dest = fragP->fr_literal + fragP->fr_fix;
fragP->fr_var = 2;
md_number_to_chars (dest, 0x4400, 2);
}
else if (count != 0 && (count & 3) == 0)
{
char *dest = fragP->fr_literal + fragP->fr_fix;
@ -6117,16 +6373,36 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
value, and stuff the instruction back again. */
where = fixP->fx_frag->fr_literal + fixP->fx_where;
if (target_big_endian)
insn = bfd_getb32 ((unsigned char *) where);
{
if (fixP->fx_size == 4)
insn = bfd_getb32 ((unsigned char *) where);
else
insn = bfd_getb16 ((unsigned char *) where);
}
else
insn = bfd_getl32 ((unsigned char *) where);
{
if (fixP->fx_size == 4)
insn = bfd_getl32 ((unsigned char *) where);
else
insn = bfd_getl16 ((unsigned char *) where);
}
insn = ppc_insert_operand (insn, operand, (offsetT) value,
fixP->tc_fix_data.ppc_cpu,
fixP->fx_file, fixP->fx_line);
if (target_big_endian)
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
{
if (fixP->fx_size == 4)
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
else
bfd_putb16 ((bfd_vma) insn, (unsigned char *) where);
}
else
bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
{
if (fixP->fx_size == 4)
bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
else
bfd_putl16 ((bfd_vma) insn, (unsigned char *) where);
}
if (fixP->fx_done)
/* Nothing else to do here. */
@ -6152,6 +6428,18 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
fixP->fx_where += 2;
#endif
}
else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
&& operand->bitm == 0x1fe
&& operand->shift == -1)
fixP->fx_r_type = BFD_RELOC_PPC_VLE_REL8;
else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
&& operand->bitm == 0xfffe
&& operand->shift == 0)
fixP->fx_r_type = BFD_RELOC_PPC_VLE_REL15;
else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
&& operand->bitm == 0x1fffffe
&& operand->shift == 0)
fixP->fx_r_type = BFD_RELOC_PPC_VLE_REL24;
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0
&& operand->bitm == 0x3fffffc
&& operand->shift == 0)
@ -6336,6 +6624,91 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
PPC_HA (value), 2);
break;
case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
case BFD_RELOC_PPC_VLE_LO16A:
{
int tval = PPC_VLE_LO16A (value);
valueT oldval = md_chars_to_number (
fixP->fx_frag->fr_literal + fixP->fx_where, 4);
md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
(oldval | tval), 4);
}
break;
case BFD_RELOC_PPC_VLE_SDAREL_LO16D:
case BFD_RELOC_PPC_VLE_LO16D:
{
int tval = PPC_VLE_LO16D (value);
valueT oldval = md_chars_to_number (
fixP->fx_frag->fr_literal + fixP->fx_where, 4);
md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
(oldval | tval), 4);
}
break;
case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
case BFD_RELOC_PPC_VLE_HI16A:
{
int tval = PPC_VLE_HI16A (value);
valueT oldval = md_chars_to_number (
fixP->fx_frag->fr_literal + fixP->fx_where, 4);
md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
(oldval | tval), 4);
}
break;
case BFD_RELOC_PPC_VLE_SDAREL_HI16D:
case BFD_RELOC_PPC_VLE_HI16D:
{
int tval = PPC_VLE_HI16D (value);
valueT oldval = md_chars_to_number (
fixP->fx_frag->fr_literal + fixP->fx_where, 4);
md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
(oldval | tval), 4);
}
break;
case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
case BFD_RELOC_PPC_VLE_HA16A:
{
int tval = PPC_VLE_HA16A (value);
valueT oldval = md_chars_to_number (
fixP->fx_frag->fr_literal + fixP->fx_where, 4);
md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
(oldval | tval), 4);
}
break;
case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
case BFD_RELOC_PPC_VLE_HA16D:
{
int tval = PPC_VLE_HA16D (value);
valueT oldval = md_chars_to_number (
fixP->fx_frag->fr_literal + fixP->fx_where, 4);
md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
(oldval | tval), 4);
}
break;
case BFD_RELOC_PPC_VLE_SDA21_LO:
{
int tval = PPC_LO (value);
valueT oldval = md_chars_to_number (
fixP->fx_frag->fr_literal + fixP->fx_where, 4);
md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
(oldval | tval), 4);
}
break;
case BFD_RELOC_PPC_VLE_SDA21:
{
valueT oldval = md_chars_to_number (
fixP->fx_frag->fr_literal + fixP->fx_where, 4);
md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
(oldval | value), 4);
}
break;
#ifdef OBJ_XCOFF
case BFD_RELOC_NONE:
break;

7
gas/config/tc-ppc.h
View file

@ -84,14 +84,11 @@ extern char *ppc_target_format (void);
ppc_handle_align (FRAGP);
extern void ppc_handle_align (struct frag *);
extern void ppc_frag_check (struct frag *);
#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
#define md_frag_check(FRAGP) \
if ((FRAGP)->has_code \
&& (((FRAGP)->fr_address + (FRAGP)->insn_addr) & 3) != 0) \
as_bad_where ((FRAGP)->fr_file, (FRAGP)->fr_line, \
_("instruction address is not a multiple of 4"));
#define md_frag_check(FRAGP) ppc_frag_check (FRAGP)
/* Arrange to store the value of ppc_cpu at the site of a fixup
for later use in md_apply_fix. */

22
gas/testsuite/ChangeLog
View file

@ -1,3 +1,25 @@
2012-05-14 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Rhonda Wittels <rhonda@codesourcery.com>
* gas/ppc/ppc.exp: Run new tests.
* gas/ppc/vle-reloc.d: New test.
* gas/ppc/vle-reloc.s: New test.
* gas/ppc/vle-simple-1.d: New test.
* gas/ppc/vle-simple-1.s: New test.
* gas/ppc/vle-simple-2.d: New test.
* gas/ppc/vle-simple-2.s: New test.
* gas/ppc/vle-simple-3.d: New test.
* gas/ppc/vle-simple-3.s: New test.
* gas/ppc/vle-simple-4.d: New test.
* gas/ppc/vle-simple-4.s: New test.
* gas/ppc/vle-simple-5.d: New test.
* gas/ppc/vle-simple-5.s: New test.
* gas/ppc/vle-simple-6.d: New test.
* gas/ppc/vle-simple-6.s: New test.
* gas/ppc/vle.d: New test.
* gas/ppc/vle.s: New test.
2012-05-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/cris/rd-pic-1.d: Expect addend as signed.

8
gas/testsuite/gas/ppc/ppc.exp
View file

@ -55,5 +55,13 @@ if { [istarget powerpc*-*-*] } then {
run_dump_test "vsx"
run_dump_test "476"
run_dump_test "titan"
run_dump_test "vle"
run_dump_test "vle-reloc"
run_dump_test "vle-simple-1"
run_dump_test "vle-simple-2"
run_dump_test "vle-simple-3"
run_dump_test "vle-simple-4"
run_dump_test "vle-simple-5"
run_dump_test "vle-simple-6"
}
}

172
gas/testsuite/gas/ppc/vle-reloc.d Normal file
View file

@ -0,0 +1,172 @@
#as: -mvle
#objdump: -dr -Mvle
#name: VLE relocations
.*: +file format elf.*-powerpc.*
Disassembly of section \.text:
00000000 <.text>:
0: e8 00 se_b 0x0
0: R_PPC_VLE_REL8 sub1
2: e9 00 se_bl 0x2
2: R_PPC_VLE_REL8 sub1
4: e1 00 se_ble 0x4
4: R_PPC_VLE_REL8 sub2
6: e6 00 se_beq 0x6
6: R_PPC_VLE_REL8 sub2
8: 78 00 00 00 e_b 0x8
8: R_PPC_VLE_REL24 sub3
c: 78 00 00 01 e_bl 0xc
c: R_PPC_VLE_REL24 sub4
10: 7a 05 00 00 e_ble cr1,0x10
10: R_PPC_VLE_REL15 sub5
14: 7a 1a 00 01 e_beql cr2,0x14
14: R_PPC_VLE_REL15 sub5
18: 70 20 c0 00 e_or2i r1,0
18: R_PPC_VLE_LO16D low
1c: 70 40 c0 00 e_or2i r2,0
1c: R_PPC_VLE_HI16D high
20: 70 60 c0 00 e_or2i r3,0
20: R_PPC_VLE_HA16D high_adjust
24: 70 80 c0 00 e_or2i r4,0
24: R_PPC_VLE_SDAREL_LO16D low_sdarel
28: 70 a0 c0 00 e_or2i r5,0
28: R_PPC_VLE_SDAREL_HI16D high_sdarel
2c: 70 40 c0 00 e_or2i r2,0
2c: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
30: 70 20 c8 00 e_and2i. r1,0
30: R_PPC_VLE_LO16D low
34: 70 40 c8 00 e_and2i. r2,0
34: R_PPC_VLE_HI16D high
38: 70 60 c8 00 e_and2i. r3,0
38: R_PPC_VLE_HA16D high_adjust
3c: 70 80 c8 00 e_and2i. r4,0
3c: R_PPC_VLE_SDAREL_LO16D low_sdarel
40: 70 a0 c8 00 e_and2i. r5,0
40: R_PPC_VLE_SDAREL_HI16D high_sdarel
44: 70 40 c8 00 e_and2i. r2,0
44: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
48: 70 40 c8 00 e_and2i. r2,0
48: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
4c: 70 20 d0 00 e_or2is r1,0
4c: R_PPC_VLE_LO16D low
50: 70 40 d0 00 e_or2is r2,0
50: R_PPC_VLE_HI16D high
54: 70 60 d0 00 e_or2is r3,0
54: R_PPC_VLE_HA16D high_adjust
58: 70 80 d0 00 e_or2is r4,0
58: R_PPC_VLE_SDAREL_LO16D low_sdarel
5c: 70 a0 d0 00 e_or2is r5,0
5c: R_PPC_VLE_SDAREL_HI16D high_sdarel
60: 70 40 d0 00 e_or2is r2,0
60: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
64: 70 20 e0 00 e_lis r1,0
64: R_PPC_VLE_LO16D low
68: 70 40 e0 00 e_lis r2,0
68: R_PPC_VLE_HI16D high
6c: 70 60 e0 00 e_lis r3,0
6c: R_PPC_VLE_HA16D high_adjust
70: 70 80 e0 00 e_lis r4,0
70: R_PPC_VLE_SDAREL_LO16D low_sdarel
74: 70 a0 e0 00 e_lis r5,0
74: R_PPC_VLE_SDAREL_HI16D high_sdarel
78: 70 40 e0 00 e_lis r2,0
78: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
7c: 70 20 e8 00 e_and2is. r1,0
7c: R_PPC_VLE_LO16D low
80: 70 40 e8 00 e_and2is. r2,0
80: R_PPC_VLE_HI16D high
84: 70 60 e8 00 e_and2is. r3,0
84: R_PPC_VLE_HA16D high_adjust
88: 70 80 e8 00 e_and2is. r4,0
88: R_PPC_VLE_SDAREL_LO16D low_sdarel
8c: 70 a0 e8 00 e_and2is. r5,0
8c: R_PPC_VLE_SDAREL_HI16D high_sdarel
90: 70 40 e8 00 e_and2is. r2,0
90: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
94: 70 01 98 00 e_cmp16i r1,0
94: R_PPC_VLE_LO16A low
98: 70 02 98 00 e_cmp16i r2,0
98: R_PPC_VLE_HI16A high
9c: 70 03 98 00 e_cmp16i r3,0
9c: R_PPC_VLE_HA16A high_adjust
a0: 70 04 98 00 e_cmp16i r4,0
a0: R_PPC_VLE_SDAREL_LO16A low_sdarel
a4: 70 05 98 00 e_cmp16i r5,0
a4: R_PPC_VLE_SDAREL_HI16A high_sdarel
a8: 70 02 98 00 e_cmp16i r2,0
a8: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
ac: 70 01 a8 00 e_cmpl16i r1,0
ac: R_PPC_VLE_LO16A low
b0: 70 02 a8 00 e_cmpl16i r2,0
b0: R_PPC_VLE_HI16A high
b4: 70 03 a8 00 e_cmpl16i r3,0
b4: R_PPC_VLE_HA16A high_adjust
b8: 70 04 a8 00 e_cmpl16i r4,0
b8: R_PPC_VLE_SDAREL_LO16A low_sdarel
bc: 70 05 a8 00 e_cmpl16i r5,0
bc: R_PPC_VLE_SDAREL_HI16A high_sdarel
c0: 70 02 a8 00 e_cmpl16i r2,0
c0: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
c4: 70 01 b0 00 e_cmph16i r1,0
c4: R_PPC_VLE_LO16A low
c8: 70 02 b0 00 e_cmph16i r2,0
c8: R_PPC_VLE_HI16A high
cc: 70 03 b0 00 e_cmph16i r3,0
cc: R_PPC_VLE_HA16A high_adjust
d0: 70 04 b0 00 e_cmph16i r4,0
d0: R_PPC_VLE_SDAREL_LO16A low_sdarel
d4: 70 05 b0 00 e_cmph16i r5,0
d4: R_PPC_VLE_SDAREL_HI16A high_sdarel
d8: 70 02 b0 00 e_cmph16i r2,0
d8: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
dc: 70 01 b8 00 e_cmphl16i r1,0
dc: R_PPC_VLE_LO16A low
e0: 70 02 b8 00 e_cmphl16i r2,0
e0: R_PPC_VLE_HI16A high
e4: 70 03 b8 00 e_cmphl16i r3,0
e4: R_PPC_VLE_HA16A high_adjust
e8: 70 04 b8 00 e_cmphl16i r4,0
e8: R_PPC_VLE_SDAREL_LO16A low_sdarel
ec: 70 05 b8 00 e_cmphl16i r5,0
ec: R_PPC_VLE_SDAREL_HI16A high_sdarel
f0: 70 02 b8 00 e_cmphl16i r2,0
f0: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
f4: 70 01 88 00 e_add2i. r1,0
f4: R_PPC_VLE_LO16A low
f8: 70 02 88 00 e_add2i. r2,0
f8: R_PPC_VLE_HI16A high
fc: 70 03 88 00 e_add2i. r3,0
fc: R_PPC_VLE_HA16A high_adjust
100: 70 04 88 00 e_add2i. r4,0
100: R_PPC_VLE_SDAREL_LO16A low_sdarel
104: 70 05 88 00 e_add2i. r5,0
104: R_PPC_VLE_SDAREL_HI16A high_sdarel
108: 70 02 88 00 e_add2i. r2,0
108: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
10c: 70 01 90 00 e_add2is r1,0
10c: R_PPC_VLE_LO16A low
110: 70 02 90 00 e_add2is r2,0
110: R_PPC_VLE_HI16A high
114: 70 03 90 00 e_add2is r3,0
114: R_PPC_VLE_HA16A high_adjust
118: 70 04 90 00 e_add2is r4,0
118: R_PPC_VLE_SDAREL_LO16A low_sdarel
11c: 70 05 90 00 e_add2is r5,0
11c: R_PPC_VLE_SDAREL_HI16A high_sdarel
120: 70 02 90 00 e_add2is r2,0
120: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
124: 70 01 a0 00 e_mull2i r1,0
124: R_PPC_VLE_LO16A low
128: 70 02 a0 00 e_mull2i r2,0
128: R_PPC_VLE_HI16A high
12c: 70 03 a0 00 e_mull2i r3,0
12c: R_PPC_VLE_HA16A high_adjust
130: 70 04 a0 00 e_mull2i r4,0
130: R_PPC_VLE_SDAREL_LO16A low_sdarel
134: 70 05 a0 00 e_mull2i r5,0
134: R_PPC_VLE_SDAREL_HI16A high_sdarel
138: 70 02 a0 00 e_mull2i r2,0
138: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel

95
gas/testsuite/gas/ppc/vle-reloc.s Normal file
View file

@ -0,0 +1,95 @@
.section .text
se_b sub1
se_bl sub1
se_bc 0,1,sub2
se_bc 1,2,sub2
e_b sub3
e_bl sub4
e_bc 0,5,sub5
e_bcl 1,10,sub5
e_or2i 1, low@l
e_or2i 2, high@h
e_or2i 3, high_adjust@ha
e_or2i 4, low_sdarel@sdarel@l
e_or2i 5, high_sdarel@sdarel@h
e_or2i 2, high_adjust_sdarel@sdarel@ha
e_and2i. 1, low@l
e_and2i. 2, high@h
e_and2i. 3, high_adjust@ha
e_and2i. 4, low_sdarel@sdarel@l
e_and2i. 5, high_sdarel@sdarel@h
e_and2i. 2, high_adjust_sdarel@sdarel@ha
e_and2i. 2, high_adjust_sdarel@sdarel@ha
e_or2is 1, low@l
e_or2is 2, high@h
e_or2is 3, high_adjust@ha
e_or2is 4, low_sdarel@sdarel@l
e_or2is 5, high_sdarel@sdarel@h
e_or2is 2, high_adjust_sdarel@sdarel@ha
e_lis 1, low@l
e_lis 2, high@h
e_lis 3, high_adjust@ha
e_lis 4, low_sdarel@sdarel@l
e_lis 5, high_sdarel@sdarel@h
e_lis 2, high_adjust_sdarel@sdarel@ha
e_and2is. 1, low@l
e_and2is. 2, high@h
e_and2is. 3, high_adjust@ha
e_and2is. 4, low_sdarel@sdarel@l
e_and2is. 5, high_sdarel@sdarel@h
e_and2is. 2, high_adjust_sdarel@sdarel@ha
e_cmp16i 1, low@l
e_cmp16i 2, high@h
e_cmp16i 3, high_adjust@ha
e_cmp16i 4, low_sdarel@sdarel@l
e_cmp16i 5, high_sdarel@sdarel@h
e_cmp16i 2, high_adjust_sdarel@sdarel@ha
e_cmpl16i 1, low@l
e_cmpl16i 2, high@h
e_cmpl16i 3, high_adjust@ha
e_cmpl16i 4, low_sdarel@sdarel@l
e_cmpl16i 5, high_sdarel@sdarel@h
e_cmpl16i 2, high_adjust_sdarel@sdarel@ha
e_cmph16i 1, low@l
e_cmph16i 2, high@h
e_cmph16i 3, high_adjust@ha
e_cmph16i 4, low_sdarel@sdarel@l
e_cmph16i 5, high_sdarel@sdarel@h
e_cmph16i 2, high_adjust_sdarel@sdarel@ha
e_cmphl16i 1, low@l
e_cmphl16i 2, high@h
e_cmphl16i 3, high_adjust@ha
e_cmphl16i 4, low_sdarel@sdarel@l
e_cmphl16i 5, high_sdarel@sdarel@h
e_cmphl16i 2, high_adjust_sdarel@sdarel@ha
e_add2i. 1, low@l
e_add2i. 2, high@h
e_add2i. 3, high_adjust@ha
e_add2i. 4, low_sdarel@sdarel@l
e_add2i. 5, high_sdarel@sdarel@h
e_add2i. 2, high_adjust_sdarel@sdarel@ha
e_add2is 1, low@l
e_add2is 2, high@h
e_add2is 3, high_adjust@ha
e_add2is 4, low_sdarel@sdarel@l
e_add2is 5, high_sdarel@sdarel@h
e_add2is 2, high_adjust_sdarel@sdarel@ha
e_mull2i 1, low@l
e_mull2i 2, high@h
e_mull2i 3, high_adjust@ha
e_mull2i 4, low_sdarel@sdarel@l
e_mull2i 5, high_sdarel@sdarel@h
e_mull2i 2, high_adjust_sdarel@sdarel@ha

39
gas/testsuite/gas/ppc/vle-simple-1.d Normal file
View file

@ -0,0 +1,39 @@
#as: -mvle
#objdump: -dr -Mvle
#name: VLE Simplified mnemonics 1
.*: +file format elf.*-powerpc.*
Disassembly of section \.text:
00000000 <target0>:
0: e6 03 se_beq 6 <target3>
00000002 <target1>:
2: e1 03 se_ble 8 <target4>
00000004 <target2>:
4: e0 00 se_bge 4 <target2>
00000006 <target3>:
6: e5 fe se_bgt 2 <target1>
00000008 <target4>:
8: e1 ff se_ble 6 <target3>
a: e4 03 se_blt 10 <target6>
0000000c <target5>:
c: e2 fb se_bne 2 <target1>
e: e1 01 se_ble 10 <target6>
00000010 <target6>:
10: e0 fc se_bge 8 <target4>
12: e3 fd se_bns c <target5>
00000014 <target8>:
14: e3 f8 se_bns 4 <target2>
16: e7 ff se_bso 14 <target8>
00000018 <target9>:
18: e6 fc se_beq 10 <target6>
1a: e7 ff se_bso 18 <target9>

34
gas/testsuite/gas/ppc/vle-simple-1.s Normal file
View file

@ -0,0 +1,34 @@
.section .text
target0:
se_beq target3
target1:
se_bf cr1, target4
target2:
se_bge target2
target3:
se_bgt target1
target4:
se_ble target3
se_blt target6
target5:
se_bne target1
se_bng target6
target6:
se_bnl target4
se_bns target5
target8:
se_bnu target2
se_bso target8
target9:
se_bt cr2, target6
se_bun target9

83
gas/testsuite/gas/ppc/vle-simple-2.d Normal file
View file

@ -0,0 +1,83 @@
#as: -mvle
#objdump: -dr -Mvle
#name: VLE Simplified mnemonics 2
.*: +file format elf.*-powerpc.*
Disassembly of section .text:
00000000 <target0>:
0: 7a 20 00 0c e_bdnz c <target1>
4: 7a 20 00 09 e_bdnzl c <target1>
8: 7a 30 00 10 e_bdz 18 <target2>
0000000c <target1>:
c: 7a 30 ff f5 e_bdzl 0 <target0>
10: 7a 12 ff f0 e_beq 0 <target0>
14: 7a 16 00 8c e_beq cr1,a0 <target8>
00000018 <target2>:
18: 7a 12 ff f5 e_beql c <target1>
1c: 7a 12 00 4d e_beql 68 <target6>
20: 7a 01 00 04 e_ble 24 <target3>
00000024 <target3>:
24: 7a 03 ff dd e_bnsl 0 <target0>
28: 7a 04 ff e4 e_bge cr1,c <target1>
2c: 7a 00 00 24 e_bge 50 <target5>
00000030 <target4>:
30: 7a 08 ff f5 e_bgel cr2,24 <target3>
34: 7a 00 ff fd e_bgel 30 <target4>
38: 7a 11 ff c8 e_bgt 0 <target0>
3c: 7a 11 ff c4 e_bgt 0 <target0>
40: 7a 19 ff d9 e_bgtl cr2,18 <target2>
44: 7a 11 ff d5 e_bgtl 18 <target2>
48: 7a 0d 00 08 e_ble cr3,50 <target5>
4c: 7a 01 00 04 e_ble 50 <target5>
00000050 <target5>:
50: 7a 01 ff e1 e_blel 30 <target4>
54: 7a 01 ff dd e_blel 30 <target4>
58: 7a 14 ff cc e_blt cr1,24 <target3>
5c: 7a 10 ff c8 e_blt 24 <target3>
60: 7a 10 ff a1 e_bltl 0 <target0>
64: 7a 14 ff 9d e_bltl cr1,0 <target0>
00000068 <target6>:
68: 7a 02 00 18 e_bne 80 <target7>
6c: 7a 06 ff 94 e_bne cr1,0 <target0>
70: 7a 02 ff e1 e_bnel 50 <target5>
74: 7a 02 ff dd e_bnel 50 <target5>
78: 7a 01 00 48 e_ble c0 <target9>
7c: 7a 05 ff b4 e_ble cr1,30 <target4>
00000080 <target7>:
80: 7a 09 ff e9 e_blel cr2,68 <target6>
84: 7a 01 00 1d e_blel a0 <target8>
88: 7a 04 ff c8 e_bge cr1,50 <target5>
8c: 7a 00 ff c4 e_bge 50 <target5>
90: 7a 0c ff 95 e_bgel cr3,24 <target3>
94: 7a 00 ff 91 e_bgel 24 <target3>
98: 7a 03 ff 80 e_bns 18 <target2>
9c: 7a 03 ff 7c e_bns 18 <target2>
000000a0 <target8>:
a0: 7a 0b ff 61 e_bnsl cr2,0 <target0>
a4: 7a 03 ff c5 e_bnsl 68 <target6>
a8: 7a 07 ff 64 e_bns cr1,c <target1>
ac: 7a 03 ff 60 e_bns c <target1>
b0: 7a 03 ff d1 e_bnsl 80 <target7>
b4: 7a 03 ff 71 e_bnsl 24 <target3>
b8: 7a 17 ff 78 e_bso cr1,30 <target4>
bc: 7a 13 ff 74 e_bso 30 <target4>
000000c0 <target9>:
c0: 7a 13 ff e1 e_bsol a0 <target8>
c4: 7a 13 ff dd e_bsol a0 <target8>
c8: 7a 11 ff b8 e_bgt 80 <target7>
cc: 7a 10 ff 85 e_bltl 50 <target5>
d0: 7a 17 ff 60 e_bso cr1,30 <target4>
d4: 7a 13 ff 5c e_bso 30 <target4>
d8: 7a 1b ff 29 e_bsol cr2,0 <target0>
dc: 7a 13 ff e5 e_bsol c0 <target9>

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gas/testsuite/gas/ppc/vle-simple-2.s Normal file
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.section .text
target0:
e_bdnz target1
e_bdnzl target1
e_bdz target2
target1:
e_bdzl target0
e_beq target0
e_beq cr1, target8
target2:
e_beql cr0, target1
e_beql target6
e_bf cr1, target3
target3:
e_bfl cr3, target0
e_bge cr1, target1
e_bge target5
target4:
e_bgel cr2, target3
e_bgel target4
e_bgt cr0, target0
e_bgt target0
e_bgtl cr2, target2
e_bgtl target2
e_ble cr3, target5
e_ble target5
target5:
e_blel cr0, target4
e_blel target4
e_blt cr1, target3
e_blt target3
e_bltl target0
e_bltl cr1, target0
target6:
e_bne target7
e_bne cr1, target0
e_bnel cr0, target5
e_bnel target5
e_bng target9
e_bng cr1, target4
target7:
e_bngl cr2, target6
e_bngl target8
e_bnl cr1, target5
e_bnl target5
e_bnll cr3, target3
e_bnll target3
e_bns target2
e_bns cr0, target2
target8:
e_bnsl cr2, target0
e_bnsl target6
e_bnu cr1, target1
e_bnu target1
e_bnul target7
e_bnul cr0, target3
e_bso cr1, target4
e_bso target4
target9:
e_bsol cr0, target8
e_bsol target8
e_bt cr1, target7
e_btl cr0, target5
e_bun cr1, target4
e_bun target4
e_bunl cr2, target0
e_bunl target9

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#as: -mvle
#objdump: -dr -Mvle
#name: VLE Simplified mnemonics 3
.*: +file format elf.*-powerpc.*
Disassembly of section .text:
00000000 <trap>:
0: 7f e0 00 08 trap
4: 7e 01 10 08 twlt r1,r2
8: 7e 83 20 08 twle r3,r4
c: 7c 80 08 08 tweq r0,r1
10: 7d 82 18 08 twge r2,r3
14: 7d 02 20 08 twgt r2,r4
18: 7d 82 28 08 twge r2,r5
1c: 7f 02 30 08 twne r2,r6
20: 7e 82 38 08 twle r2,r7
24: 7c 42 40 08 twllt r2,r8
28: 7c c2 48 08 twlle r2,r9
2c: 7c a2 50 08 twlge r2,r10
30: 7c 22 58 08 twlgt r2,r11
34: 7c a2 60 08 twlge r2,r12
38: 7c c2 68 08 twlle r2,r13

18
gas/testsuite/gas/ppc/vle-simple-3.s Normal file
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.section .text
trap:
trap
twlt 1, 2
twle 3, 4
tweq 0, 1
twge 2, 3
twgt 2, 4
twnl 2, 5
twne 2, 6
twng 2, 7
twllt 2, 8
twlle 2, 9
twlge 2, 10
twlgt 2, 11
twlnl 2, 12
twlng 2, 13

23
gas/testsuite/gas/ppc/vle-simple-4.d Normal file
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#as: -mvle
#objdump: -dr -Mvle
#name: VLE Simplified mnemonics 4
.*: +file format elf.*-powerpc.*
Disassembly of section .text:
00000000 <subtract>:
0: 7c 23 10 50 subf r1,r3,r2
4: 7c a3 20 51 subf. r5,r3,r4
8: 7c 21 14 50 subfo r1,r1,r2
c: 7c 01 14 51 subfo. r0,r1,r2
10: 7c 65 20 10 subfc r3,r5,r4
14: 7c 65 20 11 subfc. r3,r5,r4
18: 7c 23 14 10 subfco r1,r3,r2
1c: 7c a7 34 11 subfco. r5,r7,r6
20: 18 85 84 d0 e_addi r4,r5,-48
24: 18 66 94 fe e_addic r3,r6,-2
28: 18 e8 9c f0 e_addic. r7,r8,-16
2c: 1c 22 ff f1 e_add16i r1,r2,-15
30: 73 e5 8f ff e_add2i. r5,-1
34: 73 ea 97 00 e_add2is r10,-256

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gas/testsuite/gas/ppc/vle-simple-4.s Executable file
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.section .text
subtract:
sub 1, 2, 3
sub. 5, 4, 3
subo 1, 2, 1
subo. 0, 2, 1
subc 3, 4, 5
subc. 3, 4, 5
subco 1, 2, 3
subco. 5, 6, 7
e_subi 4, 5, 0x30
e_subic 3, 6, 0x2
e_subic. 7, 8, 0x10
e_sub16i 1, 2, 0xf
e_sub2i. 5, 0x1
e_sub2is 10, 0x100

20
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#as: -mvle
#objdump: -dr -Mvle
#name: VLE Simplified mnemonics 5
.*: +file format elf.*-powerpc.*
Disassembly of section .text:
00000000 <.text>:
0: 74 42 00 01 e_rlwinm r2,r2,0,0,0
4: 74 62 7d bf e_rlwinm r2,r3,15,22,31
8: 74 a4 f8 48 e_rlwimi r4,r5,31,1,4
c: 74 e6 c9 4c e_rlwimi r6,r7,25,5,6
10: 74 41 50 3f e_rlwinm r1,r2,10,0,31
14: 74 83 c0 3f e_rlwinm r3,r4,24,0,31
18: 7c 62 f8 70 e_slwi r2,r3,31
1c: 7c 25 f4 70 e_srwi r5,r1,30
20: 74 64 07 7f e_rlwinm r4,r3,0,29,31
24: 74 41 00 07 e_rlwinm r1,r2,0,0,3
28: 74 e6 d8 49 e_rlwinm r6,r7,27,1,4

13
gas/testsuite/gas/ppc/vle-simple-5.s Normal file
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.section .text
e_extlwi 2, 2, 1, 0
e_extrwi 2, 3, 10, 5
e_inslwi 4, 5, 4, 1
e_insrwi 6, 7, 2, 5
e_rotlwi 1, 2, 10
e_rotrwi 3, 4, 8
e_slwi 2, 3, 31
e_srwi 5, 1, 30
e_clrlwi 4, 3, 29
e_clrrwi 1, 2, 28
e_clrlslwi 6, 7, 28, 27

60
gas/testsuite/gas/ppc/vle-simple-6.d Normal file
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#as: -mvle
#objdump: -dr -Mvle
#name: VLE Simplified mnemonics 6
.*: +file format elf.*-powerpc.*
Disassembly of section .text:
00000000 <.text>:
0: 7c b1 9b a6 mtmas1 r5
4: 7c 3a 0b a6 mtcsrr0 r1
8: 7c 5b 0b a6 mtcsrr1 r2
c: 7c b0 62 a6 mfivor0 r5
10: 7c b1 62 a6 mfivor1 r5
14: 7c b2 62 a6 mfivor2 r5
18: 7c b3 62 a6 mfivor3 r5
1c: 7c b4 62 a6 mfivor4 r5
20: 7c b5 62 a6 mfivor5 r5
24: 7c b6 62 a6 mfivor6 r5
28: 7c b7 62 a6 mfivor7 r5
2c: 7c b8 62 a6 mfivor8 r5
30: 7c b9 62 a6 mfivor9 r5
34: 7c ba 62 a6 mfivor10 r5
38: 7c bb 62 a6 mfivor11 r5
3c: 7c bc 62 a6 mfivor12 r5
40: 7c bd 62 a6 mfivor13 r5
44: 7c be 62 a6 mfivor14 r5
48: 7c bf 62 a6 mfivor15 r5
4c: 7d 50 43 a6 mtsprg 0,r10
50: 7d 51 43 a6 mtsprg 1,r10
54: 7d 52 43 a6 mtsprg 2,r10
58: 7d 53 43 a6 mtsprg 3,r10
5c: 7d 54 43 a6 mtsprg 4,r10
60: 7d 55 43 a6 mtsprg 5,r10
64: 7d 56 43 a6 mtsprg 6,r10
68: 7d 57 43 a6 mtsprg 7,r10
6c: 7d 50 43 a6 mtsprg 0,r10
70: 7d 51 43 a6 mtsprg 1,r10
74: 7d 52 43 a6 mtsprg 2,r10
78: 7d 53 43 a6 mtsprg 3,r10
7c: 7d 54 43 a6 mtsprg 4,r10
80: 7d 55 43 a6 mtsprg 5,r10
84: 7d 56 43 a6 mtsprg 6,r10
88: 7d 57 43 a6 mtsprg 7,r10
8c: 7d 30 42 a6 mfsprg r9,0
90: 7d 31 42 a6 mfsprg r9,1
94: 7d 32 42 a6 mfsprg r9,2
98: 7d 33 42 a6 mfsprg r9,3
9c: 7d 24 42 a6 mfsprg r9,4
a0: 7d 25 42 a6 mfsprg r9,5
a4: 7d 26 42 a6 mfsprg r9,6
a8: 7d 27 42 a6 mfsprg r9,7
ac: 7d 30 42 a6 mfsprg r9,0
b0: 7d 31 42 a6 mfsprg r9,1
b4: 7d 32 42 a6 mfsprg r9,2
b8: 7d 33 42 a6 mfsprg r9,3
bc: 7d 24 42 a6 mfsprg r9,4
c0: 7d 25 42 a6 mfsprg r9,5
c4: 7d 26 42 a6 mfsprg r9,6
c8: 7d 27 42 a6 mfsprg r9,7

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.section .text
mtmas1 5
mtcsrr0 1
mtcsrr1 2
mfivor0 5
mfivor1 5
mfivor2 5
mfivor3 5
mfivor4 5
mfivor5 5
mfivor6 5
mfivor7 5
mfivor8 5
mfivor9 5
mfivor10 5
mfivor11 5
mfivor12 5
mfivor13 5
mfivor14 5
mfivor15 5
mtsprg 0, 10
mtsprg 1, 10
mtsprg 2, 10
mtsprg 3, 10
mtsprg 4, 10
mtsprg 5, 10
mtsprg 6, 10
mtsprg 7, 10
mtsprg0 10
mtsprg1 10
mtsprg2 10
mtsprg3 10
mtsprg4 10
mtsprg5 10
mtsprg6 10
mtsprg7 10
mfsprg 9, 0
mfsprg 9, 1
mfsprg 9, 2
mfsprg 9, 3
mfsprg 9, 4
mfsprg 9, 5
mfsprg 9, 6
mfsprg 9, 7
mfsprg0 9
mfsprg1 9
mfsprg2 9
mfsprg3 9
mfsprg4 9
mfsprg5 9
mfsprg6 9
mfsprg7 9

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gas/testsuite/gas/ppc/vle.d Executable file
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#as: -mvle
#objdump: -dr -Mvle
#name: Validate VLE instructions
.*: +file format elf.*-powerpc.*
Disassembly of section \.text:
0+00 <.*>:
0: 1c 83 00 1b e_add16i r4,r3,27
4: 70 c0 8c 56 e_add2i\. r0,13398
8: 71 01 93 21 e_add2is r1,17185
c: 18 46 88 37 e_addi\. r2,r6,55
10: 18 65 81 37 e_addi r3,r5,14080
14: 18 84 9a 37 e_addic\. r4,r4,3604480
18: 18 e8 93 37 e_addic r7,r8,922746880
1c: 71 3f ce ed e_and2i\. r9,65261
20: 71 40 e8 05 e_and2is\. r10,5
24: 19 ab c8 39 e_andi\. r11,r13,57
28: 19 ec c2 37 e_andi r12,r15,3604480
2c: 78 00 00 ec e_b 118 <middle_label>
30: 78 00 00 01 e_bl 30 <start_label\+0x30>
30: R_PPC_VLE_REL24 extern_subr
34: 7a 03 ff cc e_bns 0 <start_label>
38: 7a 1f 00 01 e_bsol cr3,38 <start_label\+0x38>
38: R_PPC_VLE_REL15 extern_subr
3c: 70 c2 9b 33 e_cmp16i r2,13107
40: 18 46 a9 37 e_cmpi cr2,r6,14080
44: 7c 87 58 1c e_cmph cr1,r7,r11
48: 73 ec b5 ef e_cmph16i r12,-529
4c: 7c 06 40 5c e_cmphl cr0,r6,r8
50: 70 4d ba 34 e_cmphl16i r13,4660
54: 73 e1 ae e0 e_cmpl16i r1,65248
58: 18 a3 ab 37 e_cmpli cr1,r3,922746880
5c: 7f a3 02 02 e_crand 4\*cr7\+gt,so,lt
60: 7c 02 e9 02 e_crandc lt,eq,4\*cr7\+gt
64: 7d f0 8a 42 e_creqv 4\*cr3\+so,4\*cr4\+lt,4\*cr4\+gt
68: 7d e0 19 c2 e_crnand 4\*cr3\+so,lt,so
6c: 7d e0 18 42 e_crnor 4\*cr3\+so,lt,so
70: 7d 8d 73 82 e_cror 4\*cr3\+lt,4\*cr3\+gt,4\*cr3\+eq
74: 7e 72 8b 42 e_crorc 4\*cr4\+so,4\*cr4\+eq,4\*cr4\+gt
78: 7c 00 01 82 e_crclr lt
7c: 30 e3 cc 0d e_lbz r7,-13299\(r3\)
80: 18 e5 00 cc e_lbzu r7,-52\(r5\)
84: 39 0a 01 ff e_lha r8,511\(r10\)
88: 19 01 03 ff e_lhau r8,-1\(r1\)
8c: 58 e0 18 38 e_lhz r7,6200\(0\)
90: 18 e0 01 3e e_lhzu r7,62\(0\)
94: 70 06 1b 33 e_li r0,209715
98: 70 26 e3 33 e_lis r1,13107
9c: 18 a3 08 18 e_lmw r5,24\(r3\)
a0: 50 a3 27 28 e_lwz r5,10024\(r3\)
a4: 18 c2 02 72 e_lwzu r6,114\(r2\)
a8: 7c 98 00 20 e_mcrf cr1,cr6
ac: 19 2a a0 37 e_mulli r9,r10,55
b0: 70 01 a6 68 e_mull2i r1,1640
b4: 70 a4 c3 45 e_or2i r5,9029
b8: 70 b4 d3 45 e_or2is r5,41797
bc: 19 27 d8 37 e_ori\. r7,r9,55
c0: 19 07 d1 37 e_ori r7,r8,14080
c4: 7e d2 02 30 e_rlw r18,r22,r0
c8: 7c 48 02 31 e_rlw\. r8,r2,r0
cc: 7c 74 aa 70 e_rlwi r20,r3,21
d0: 7c 62 aa 71 e_rlwi\. r2,r3,21
d4: 76 64 6a 1e e_rlwimi r4,r19,13,8,15
d8: 74 24 68 63 e_rlwinm r4,r1,13,1,17
dc: 7e 6c 30 70 e_slwi r12,r19,6
e0: 7d 4c a0 71 e_slwi\. r12,r10,20
e4: 7c 20 84 70 e_srwi r0,r1,16
e8: 7c 20 5c 71 e_srwi\. r0,r1,11
ec: 34 61 55 f0 e_stb r3,22000\(r1\)
f0: 1a 76 04 fc e_stbu r19,-4\(r22\)
f4: 5c 15 02 9a e_sth r0,666\(r21\)
f8: 18 37 05 ff e_sthu r1,-1\(r23\)
fc: 18 03 09 04 e_stmw r0,4\(r3\)
100: 54 60 3f 21 e_stw r3,16161\(0\)
104: 1a c4 06 ee e_stwu r22,-18\(r4\)
108: 18 15 b2 37 e_subfic r0,r21,3604480
10c: 1a c0 bb 37 e_subfic\. r22,r0,922746880
110: 18 75 e1 37 e_xori r21,r3,14080
114: 1a 80 e8 37 e_xori\. r0,r20,55
0+0000118 <middle_label>:
118: 04 7f se_add r31,r7
11a: 21 ec se_addi r28,31
11c: 46 10 se_and r0,r1
11e: 47 01 se_and\. r1,r0
120: 45 32 se_andc r2,r3
122: 2f 14 se_andi r4,17
124: e8 fa se_b 118 <middle_label>
126: e9 00 se_bl 126 <middle_label\+0xe>
126: R_PPC_VLE_REL8 extern_subr
128: e7 14 se_bso 150 <not_end_label>
12a: 61 2b se_bclri r27,18
12c: 00 06 se_bctr
12e: 00 07 se_bctrl
130: 63 17 se_bgeni r7,17
132: 00 04 se_blr
134: 00 05 se_blrl
136: 2c 06 se_bmaski r6,0
138: 64 10 se_bseti r0,1
13a: 66 74 se_btsti r4,7
13c: 0c 10 se_cmp r0,r1
13e: 0e cf se_cmph r31,r28
140: 0f 91 se_cmphl r1,r25
142: 2b 63 se_cmpi r3,22
144: 0d 76 se_cmpl r6,r7
146: 22 bc se_cmpli r28,12
148: 00 d1 se_extsb r1
14a: 00 f2 se_extsh r2
14c: 00 ce se_extzb r30
14e: 00 e8 se_extzh r24
0+0000150 <not_end_label>:
150: 00 00 se_illegal
152: 00 01 se_isync
154: 88 18 se_lbz r1,8\(r24\)
156: a9 84 se_lhz r24,18\(r4\)
158: 4c f4 se_li r4,79
15a: cf 60 se_lwz r6,60\(r0\)
15c: 03 07 se_mfar r7,r8
15e: 00 a3 se_mfctr r3
160: 00 84 se_mflr r4
162: 01 0f se_mr r31,r0
164: 02 2f se_mtar r23,r2
166: 00 b6 se_mtctr r6
168: 00 9f se_mtlr r31
16a: 05 43 se_mullw r3,r4
16c: 00 38 se_neg r24
16e: 00 29 se_not r25
170: 44 10 se_or r0,r1
172: 00 09 se_rfci
174: 00 0a se_rfdi
176: 00 08 se_rfi
178: 00 02 se_sc
17a: 42 65 se_slw r5,r6
17c: 6c 77 se_slwi r7,7
17e: 41 e6 se_sraw r6,r30
180: 6a 89 se_srawi r25,8
182: 40 0e se_srw r30,r0
184: 69 9d se_srwi r29,25
186: 9a 02 se_stb r0,10\(r2\)
188: b6 1e se_sth r1,12\(r30\)
18a: d0 7d se_stw r7,0\(r29\)
18c: 06 21 se_sub r1,r2
18e: 07 ad se_subf r29,r26
190: 25 77 se_subi r7,24
0+0000192 <end_label>:
192: 27 29 se_subi\. r25,19
194: e9 c2 se_bl 118 <middle_label>
196: 79 ff ff 82 e_b 118 <middle_label>
19a: 79 ff fe 67 e_bl 0 <start_label>

184
gas/testsuite/gas/ppc/vle.s Executable file
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# Freescale PowerPC VLE instruction tests
#as: -mvle
.section .text
.extern extern_subr
.equ UI8,0x37
.equ SCI0,UI8<<0
.equ SCI1,UI8<<8
.equ SCI2,UI8<<16
.equ SCI3,UI8<<24
.equ r0,0
.equ r1,1
.equ r2,2
.equ r3,3
.equ r4,4
.equ r5,5
.equ r6,6
.equ r7,7
.equ r8,8
.equ r9,9
.equ r10,10
.equ r11,11
.equ r12,12
.equ r13,13
.equ r14,14
.equ r15,15
.equ r16,16
.equ r17,17
.equ r18,18
.equ r19,19
.equ r20,20
.equ r21,21
.equ r22,22
.equ r23,23
.equ r24,24
.equ r25,25
.equ r26,26
.equ r27,27
.equ r28,28
.equ r29,29
.equ r30,30
.equ r31,31
.equ r32,32
.equ rsp,r1
start_label:
e_add16i r4,r3,27
e_add2i. r0,0x3456
e_add2is r1,0x4321
e_addi. r2,r6,SCI0
e_addi r3,r5,SCI1
e_addic. r4,r4,SCI2
e_addic r7,r8,SCI3
e_and2i. r9,0xfeed
e_and2is. r10,5
e_andi. r11,r13,0x39
e_andi r12,r15,SCI2
e_b middle_label
e_bl extern_subr
e_bc 0,3,start_label
e_bcl 1,15,extern_subr
e_cmp16i r2,0x3333
e_cmpi 2,r6,SCI1
e_cmph 1,r7,r11
e_cmph16i r12,0xfdef
e_cmphl 0,r6,r8
e_cmphl16i r13,0x1234
e_cmpl16i r1, 0xfee0
e_cmpli 1,r3,SCI3
e_crand 0x1d,3,0
e_crandc 0,2,0x1d
e_creqv 15,16,17
e_crnand 0xf,0,3
e_crnor 0xf,0,3
e_cror 12,13,14
e_crorc 19,18,17
e_crxor 0,0,0
e_lbz r7,0xffffcc0d(r3)
e_lbzu r7,-52(r5)
e_lha r8,0x1ff(r10)
e_lhau r8,-1(r1)
e_lhz r7,6200(r0)
e_lhzu r7,62(r0)
e_li r0,0x33333
e_lis r1,0x3333
e_lmw r5,24(r3)
e_lwz r5,10024(r3)
e_lwzu r6,0x72(r2)
e_mcrf 1,6
e_mulli r9,r10,SCI0
e_mull2i r1,0x668
e_or2i r5,0x2345
e_or2is r5,0xa345
e_ori. r7,r9,SCI0
e_ori r7,r8,SCI1
e_rlw r18, r22,r0
e_rlw. r8, r2,r0
e_rlwi r20,r3,21
e_rlwi. r2,r3,21
e_rlwimi r4,r19,13,8,15
e_rlwinm r4,r1,13,1,17
e_slwi r12,r19,6
e_slwi. r12,r10,20
e_srwi r0,r1,16
e_srwi. r0,r1,11
e_stb r3,22000(r1)
e_stbu r19,-4(r22)
e_sth r0,666(r21)
e_sthu r1,-1(r23)
e_stmw r0,4(r3)
e_stw r3,16161(r0)
e_stwu r22,0xffffffee(r4)
e_subfic r0,r21,SCI2
e_subfic. r22,r0,SCI3
e_xori r21,r3,SCI1
e_xori. r0,r20,SCI0
middle_label:
se_add r31,r7
se_addi r28,0x1f
se_and r0,r1
se_and. r1,r0
se_andc r2, r3
se_andi r4,0x11
se_b middle_label
se_bl extern_subr
se_bc 1,3,not_end_label
se_bclri r27,0x12
se_bctr
se_bctrl
se_bgeni r7,17
se_blr
se_blrl
se_bmaski r6,0
se_bseti r0,1
se_btsti r4,7
se_cmp r0,r1
se_cmph r31,r28
se_cmphl r1,r25
se_cmpi r3,22
se_cmpl r6,r7
se_cmpli r28,0xc
se_extsb r1
se_extsh r2
se_extzb r30
se_extzh r24
not_end_label:
se_illegal
se_isync
se_lbz r1,8(r24)
se_lhz r24,18(r4)
se_li r4,0x4f
se_lwz r6,60(r0)
se_mfar r7,r8
se_mfctr r3
se_mflr r4
se_mr r31,r0
se_mtar r23,r2
se_mtctr r6
se_mtlr r31
se_mullw r3,r4
se_neg r24
se_not r25
se_or r0,r1
se_rfci
se_rfdi
se_rfi
se_sc
se_slw r5,r6
se_slwi r7,7
se_sraw r6,r30
se_srawi r25,8
se_srw r30,r0
se_srwi r29,25
se_stb r0,10(r2)
se_sth r1,12(r30)
se_stw r7,0(r29)
se_sub r1,r2
se_subf r29,r26
se_subi r7,24
end_label:
se_subi. r25,19
se_bl middle_label
e_b middle_label
e_bl start_label

30
include/elf/ChangeLog
View file

@ -1,3 +1,33 @@
2012-05-14 James Lemke <jwlemke@codesourcery.com>
* ppc.h (SEC_PPC_VLE): Remove.
2012-05-14 Catherine Moore <clm@codesourcery.com>
James Lemke <jwlemke@codesourcery.com>
* ppc.h (R_PPC_VLE_REL8): New reloction.
(R_PPC_VLE_REL15): Likewise.
(R_PPC_VLE_REL24): Likewise.
(R_PPC_VLE_LO16A): Likewise.
(R_PPC_VLE_LO16D): Likewise.
(R_PPC_VLE_HI16A): Likewise.
(R_PPC_VLE_HI16D): Likewise.
(R_PPC_VLE_HA16A): Likewise.
(R_PPC_VLE_HA16D): Likewise.
(R_PPC_VLE_SDA21): Likewise.
(R_PPC_VLE_SDA21_LO): Likewise.
(R_PPC_VLE_SDAREL_LO16A): Likewise.
(R_PPC_VLE_SDAREL_LO16D): Likewise.
(R_PPC_VLE_SDAREL_HI16A): Likewise.
(R_PPC_VLE_SDAREL_HI16D): Likewise.
(R_PPC_VLE_SDAREL_HA16A): Likewise.
(R_PPC_VLE_SDAREL_HA16D): Likewise.
(SEC_PPC_VLE): Remove.
(PF_PPC_VLE): New program header flag.
(SHF_PPC_VLE): New section header flag.
(vle_opcodes, vle_num_opcodes): New.
(VLE_OP): New macro.
(VLE_OP_TO_SEG): New macro.
2012-05-11 Georg-Johann Lay <avr@gjlay.de
PR target/13503

27
include/elf/ppc.h
View file

@ -131,6 +131,25 @@ START_RELOC_NUMBERS (elf_ppc_reloc_type)
RELOC_NUMBER (R_PPC_EMB_BIT_FLD, 115)
RELOC_NUMBER (R_PPC_EMB_RELSDA, 116)
/* PowerPC VLE relocations. */
RELOC_NUMBER (R_PPC_VLE_REL8, 216)
RELOC_NUMBER (R_PPC_VLE_REL15, 217)
RELOC_NUMBER (R_PPC_VLE_REL24, 218)
RELOC_NUMBER (R_PPC_VLE_LO16A, 219)
RELOC_NUMBER (R_PPC_VLE_LO16D, 220)
RELOC_NUMBER (R_PPC_VLE_HI16A, 221)
RELOC_NUMBER (R_PPC_VLE_HI16D, 222)
RELOC_NUMBER (R_PPC_VLE_HA16A, 223)
RELOC_NUMBER (R_PPC_VLE_HA16D, 224)
RELOC_NUMBER (R_PPC_VLE_SDA21, 225)
RELOC_NUMBER (R_PPC_VLE_SDA21_LO, 226)
RELOC_NUMBER (R_PPC_VLE_SDAREL_LO16A, 227)
RELOC_NUMBER (R_PPC_VLE_SDAREL_LO16D, 228)
RELOC_NUMBER (R_PPC_VLE_SDAREL_HI16A, 229)
RELOC_NUMBER (R_PPC_VLE_SDAREL_HI16D, 230)
RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16A, 231)
RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16D, 232)
/* Support STT_GNU_IFUNC plt calls. */
RELOC_NUMBER (R_PPC_IRELATIVE, 248)
@ -166,9 +185,11 @@ END_RELOC_NUMBERS (R_PPC_max)
#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag. */
#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib flag. */
/* This bit is reserved by BFD for processor specific stuff. Name
it properly so that we can easily stay consistent elsewhere. */
#define SEC_PPC_VLE SEC_TIC54X_BLOCK
/* Processor specific program headers, p_flags field. */
#define PF_PPC_VLE 0x10000000 /* PowerPC VLE. */
/* Processor specific section headers, sh_flags field. */
#define SHF_PPC_VLE 0x10000000 /* PowerPC VLE text section. */
/* Processor specific section headers, sh_type field. */

15
include/opcode/ChangeLog
View file

@ -1,3 +1,18 @@
2012-05-14 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Rhonda Wittels <rhonda@codesourcery.com>
* ppc.h (PPC_OPCODE_VLE): New definition.
(PPC_OP_SA): New macro.
(PPC_OP_SE_VLE): New macro.
(PPC_OP): Use a variable shift amount.
(powerpc_operand): Update comments.
(PPC_OPSHIFT_INV): New macro.
(PPC_OPERAND_CR): Replace with...
(PPC_OPERAND_CR_BIT): ...this and
(PPC_OPERAND_CR_REG): ...this.
2012-05-03 Sean Keys <skeys@ipdatasys.com>
* xgate.h: Header file for XGATE assembler.

43
include/opcode/ppc.h
View file

@ -65,6 +65,8 @@ struct powerpc_opcode
instructions. */
extern const struct powerpc_opcode powerpc_opcodes[];
extern const int powerpc_num_opcodes;
extern const struct powerpc_opcode vle_opcodes[];
extern const int vle_num_opcodes;
/* Values defined for the flags field of a struct powerpc_opcode. */
@ -183,8 +185,20 @@ extern const int powerpc_num_opcodes;
/* Opcode is supported by Thread management APU */
#define PPC_OPCODE_TMR 0x800000000ull
/* Opcode which is supported by the VLE extension. */
#define PPC_OPCODE_VLE 0x1000000000ull
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
/* A macro to determine if the instruction is a 2-byte VLE insn. */
#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
/* A macro to extract the major opcode from a VLE instruction. */
#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
/* A macro to convert a VLE opcode to a VLE opcode segment. */
#define VLE_OP_TO_SEG(i) ((i) >> 1)
/* The operands table is an array of struct powerpc_operand. */
@ -193,16 +207,22 @@ struct powerpc_operand
/* A bitmask of bits in the operand. */
unsigned int bitm;
/* How far the operand is left shifted in the instruction.
-1 to indicate that BITM and SHIFT cannot be used to determine
where the operand goes in the insn. */
/* The shift operation to be applied to the operand. No shift
is made if this is zero. For positive values, the operand
is shifted left by SHIFT. For negative values, the operand
is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
that BITM and SHIFT cannot be used to determine where the
operand goes in the insn. */
int shift;
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
i |= (op & o->bitm) << o->shift;
if (o->shift >= 0)
i |= (op & o->bitm) << o->shift;
else
i |= (op & o->bitm) >> -o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the operand value).
@ -220,7 +240,10 @@ struct powerpc_operand
extract this operand type from an instruction, check this field.
If it is NULL, compute
op = (i >> o->shift) & o->bitm;
if (o->shift >= 0)
op = (i >> o->shift) & o->bitm;
else
op = (i << -o->shift) & o->bitm;
if ((o->flags & PPC_OPERAND_SIGNED) != 0)
sign_extend (op);
(i is the instruction, o is a pointer to this structure, and op
@ -244,6 +267,11 @@ struct powerpc_operand
extern const struct powerpc_operand powerpc_operands[];
extern const unsigned int num_powerpc_operands;
/* Use with the shift field of a struct powerpc_operand to indicate
that BITM and SHIFT cannot be used to determine where the operand
goes in the insn. */
#define PPC_OPSHIFT_INV (-1 << 31)
/* Values defined for the flags field of a struct powerpc_operand. */
/* This operand takes signed values. */
@ -277,7 +305,7 @@ extern const unsigned int num_powerpc_operands;
cr4 4 cr5 5 cr6 6 cr7 7
These may be combined arithmetically, as in cr2*4+gt. These are
only supported on the PowerPC, not the POWER. */
#define PPC_OPERAND_CR (0x10)
#define PPC_OPERAND_CR_BIT (0x10)
/* This operand names a register. The disassembler uses this to print
register names with a leading 'r'. */
@ -342,6 +370,9 @@ extern const unsigned int num_powerpc_operands;
/* This operand names a vector-scalar unit register. The disassembler
prints these with a leading 'vs'. */
#define PPC_OPERAND_VSR (0x100000)
/* This is a CR FIELD that does not use symbolic names. */
#define PPC_OPERAND_CR_REG (0x200000)
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an

34
ld/ChangeLog
View file

@ -1,3 +1,37 @@
2012-05-14 James Lemke <jwlemke@codesourcery.com>
* ldlang.c (walk_wild_consider_section): Don't copy section_flag_list.
Pass it to callback.
(walk_wild_section_general): Pass section_flag_list to callback.
(lang_add_section): Add sflag_list parm.
Move out logic to keep / omit a section & call bfd_lookup_section_flags.
(output_section_callback_fast): Add sflag_list parm.
Add new parm to lang_add_section calls.
(output_section_callback): Likewise.
(check_section_callback): Add sflag_list parm.
(lang_place_orphans): Add new parm to lang_add_section calls.
(gc_section_callback): Add sflag_list parm.
(find_relro_section_callback): Likewise.
* ldlang.h (callback_t): Add flag_info parm.
(lang_add_section): Add sflag_list parm.
* emultempl/armelf.em (elf32_arm_add_stub_section):
Add lang_add_section parm.
* emultempl/beos.em (gld*_place_orphan): Likewise.
* emultempl/elf32.em (gld*_place_orphan): Likewise.
* emultempl/hppaelf.em (hppaelf_add_stub_section): Likewise.
* emultempl/m68hc1xelf.em (m68hc11elf_add_stub_section): Likewise.
* emultempl/mipself.em (mips_add_stub_section): Likewise.
* emultempl/mmo.em (mmo_place_orphan): Likewise.
* emultempl/pe.em (gld_*_place_orphan): Likewise.
* emultempl/pep.em (gld_*_place_orphan): Likewise.
* emultempl/ppc64elf.em (ppc_add_stub_section): Likewise.
* emultempl/spuelf.em (spu_place_special_section): Likewise.
* emultempl/vms.em (vms_place_orphan): Likewise.
2012-05-14 Catherine Moore <clm@codesourcery.com>
* NEWS: Mention PowerPC VLE port.
2012-05-11 Daniel Richard G. <skunk@iskunk.org>
PR binutils/14028

2
ld/NEWS
View file

@ -1,5 +1,7 @@
-*- text -*-
* Add support for the VLE extension to the PowerPC architecture.
* Add support for the Freescale XGATE architecture.
* Add option -f FILE on AIX (for response file).

2
ld/emultempl/armelf.em
View file

@ -208,7 +208,7 @@ elf32_arm_add_stub_section (const char *stub_sec_name,
info.input_section = input_section;
lang_list_init (&info.add);
lang_add_section (&info.add, stub_sec, os);
lang_add_section (&info.add, stub_sec, NULL, os);
if (info.add.head == NULL)
goto err_ret;

2
ld/emultempl/beos.em
View file

@ -718,7 +718,7 @@ gld${EMULATION_NAME}_place_orphan (asection *s,
The sections still have to be sorted, but that has to wait until
all such sections have been processed by us. The sorting is done by
sort_sections. */
lang_add_section (&l->wild_statement.children, s, os);
lang_add_section (&l->wild_statement.children, s, NULL, os);
return os;
}

6
ld/emultempl/elf32.em
View file

@ -1861,7 +1861,7 @@ gld${EMULATION_NAME}_place_orphan (asection *s,
If the section already exists but does not have any flags
set, then it has been created by the linker, probably as a
result of a --section-start command line switch. */
lang_add_section (&os->children, s, os);
lang_add_section (&os->children, s, NULL, os);
return os;
}
@ -1875,7 +1875,7 @@ gld${EMULATION_NAME}_place_orphan (asection *s,
unused one and use that. */
if (match_by_name)
{
lang_add_section (&match_by_name->children, s, match_by_name);
lang_add_section (&match_by_name->children, s, NULL, match_by_name);
return match_by_name;
}
@ -1901,7 +1901,7 @@ gld${EMULATION_NAME}_place_orphan (asection *s,
&& hold[orphan_text].os != NULL)
{
os = hold[orphan_text].os;
lang_add_section (&os->children, s, os);
lang_add_section (&os->children, s, NULL, os);
return os;
}

2
ld/emultempl/hppaelf.em
View file

@ -195,7 +195,7 @@ hppaelf_add_stub_section (const char *stub_sec_name, asection *input_section)
info.input_section = input_section;
lang_list_init (&info.add);
lang_add_section (&info.add, stub_sec, os);
lang_add_section (&info.add, stub_sec, NULL, os);
if (info.add.head == NULL)
goto err_ret;

2
ld/emultempl/m68hc1xelf.em
View file

@ -271,7 +271,7 @@ m68hc11elf_add_stub_section (const char *stub_sec_name,
at the correct place. */
info.input_section = tramp_section;
lang_list_init (&info.add);
lang_add_section (&info.add, stub_sec, os);
lang_add_section (&info.add, stub_sec, NULL, os);
if (info.add.head == NULL)
goto err_ret;

2
ld/emultempl/mipself.em
View file

@ -180,7 +180,7 @@ mips_add_stub_section (const char *stub_sec_name, asection *input_section,
/* Initialize a statement list that contains only the new statement. */
lang_list_init (&info.add);
lang_add_section (&info.add, stub_sec, os);
lang_add_section (&info.add, stub_sec, NULL, os);
if (info.add.head == NULL)
goto err_ret;

2
ld/emultempl/mmo.em
View file

@ -75,7 +75,7 @@ mmo_place_orphan (asection *s,
(regardless of whether the linker script lists it as input). */
if (os != NULL)
{
lang_add_section (&os->children, s, os);
lang_add_section (&os->children, s, NULL, os);
return os;
}

4
ld/emultempl/pe.em
View file

@ -1915,7 +1915,7 @@ gld_${EMULATION_NAME}_place_orphan (asection *s,
If the section already exists but does not have any flags set,
then it has been created by the linker, probably as a result of
a --section-start command line switch. */
lang_add_section (&add_child, s, os);
lang_add_section (&add_child, s, NULL, os);
break;
}
@ -1929,7 +1929,7 @@ gld_${EMULATION_NAME}_place_orphan (asection *s,
unused one and use that. */
if (os == NULL && match_by_name)
{
lang_add_section (&match_by_name->children, s, match_by_name);
lang_add_section (&match_by_name->children, s, NULL, match_by_name);
return match_by_name;
}

4
ld/emultempl/pep.em
View file

@ -1651,7 +1651,7 @@ gld_${EMULATION_NAME}_place_orphan (asection *s,
If the section already exists but does not have any flags set,
then it has been created by the linker, probably as a result of
a --section-start command line switch. */
lang_add_section (&add_child, s, os);
lang_add_section (&add_child, s, NULL, os);
break;
}
@ -1665,7 +1665,7 @@ gld_${EMULATION_NAME}_place_orphan (asection *s,
unused one and use that. */
if (os == NULL && match_by_name)
{
lang_add_section (&match_by_name->children, s, match_by_name);
lang_add_section (&match_by_name->children, s, NULL, match_by_name);
return match_by_name;
}

2
ld/emultempl/ppc64elf.em
View file

@ -395,7 +395,7 @@ ppc_add_stub_section (const char *stub_sec_name, asection *input_section)
info.input_section = input_section;
lang_list_init (&info.add);
lang_add_section (&info.add, stub_sec, os);
lang_add_section (&info.add, stub_sec, NULL, os);
if (info.add.head == NULL)
goto err_ret;

4
ld/emultempl/spuelf.em
View file

@ -151,7 +151,7 @@ spu_place_special_section (asection *s, asection *o, const char *output_name)
lang_statement_list_type add;
lang_list_init (&add);
lang_add_section (&add, s, os);
lang_add_section (&add, s, NULL, os);
*add.tail = os->children.head;
os->children.head = add.head;
}
@ -168,7 +168,7 @@ spu_place_special_section (asection *s, asection *o, const char *output_name)
lang_add_assignment (exp_assign (".", e_size));
pop_stat_ptr ();
}
lang_add_section (&os->children, s, os);
lang_add_section (&os->children, s, NULL, os);
}
s->output_section->size += s->size;

2
ld/emultempl/vms.em
View file

@ -117,7 +117,7 @@ vms_place_orphan (asection *s,
if (hold_data.os != NULL)
{
lang_add_section (&hold_data.os->children, s, hold_data.os);
lang_add_section (&hold_data.os->children, s, NULL, hold_data.os);
return hold_data.os;
}
else

50
ld/ldlang.c
View file

@ -236,9 +236,6 @@ walk_wild_consider_section (lang_wild_statement_type *ptr,
{
struct name_list *list_tmp;
/* Propagate the section_flag_info from the wild statement to the section. */
s->section_flag_info = ptr->section_flag_list;
/* Don't process sections from files which were excluded. */
for (list_tmp = sec->spec.exclude_name_list;
list_tmp;
@ -265,7 +262,7 @@ walk_wild_consider_section (lang_wild_statement_type *ptr,
return;
}
(*callback) (ptr, sec, s, file, data);
(*callback) (ptr, sec, s, ptr->section_flag_list, file, data);
}
/* Lowest common denominator routine that can handle everything correctly,
@ -284,7 +281,7 @@ walk_wild_section_general (lang_wild_statement_type *ptr,
{
sec = ptr->section_list;
if (sec == NULL)
(*callback) (ptr, sec, s, file, data);
(*callback) (ptr, sec, s, ptr->section_flag_list, file, data);
while (sec != NULL)
{
@ -506,6 +503,7 @@ static void
output_section_callback_fast (lang_wild_statement_type *ptr,
struct wildcard_list *sec,
asection *section,
struct flag_info *sflag_list ATTRIBUTE_UNUSED,
lang_input_statement_type *file,
void *output)
{
@ -538,7 +536,7 @@ output_section_callback_tree_to_list (lang_wild_statement_type *ptr,
if (tree->left)
output_section_callback_tree_to_list (ptr, tree->left, output);
lang_add_section (&ptr->children, tree->section,
lang_add_section (&ptr->children, tree->section, NULL,
(lang_output_section_statement_type *) output);
if (tree->right)
@ -1809,7 +1807,7 @@ lang_insert_orphan (asection *s,
if (add_child == NULL)
add_child = &os->children;
lang_add_section (add_child, s, os);
lang_add_section (add_child, s, NULL, os);
if (after && (s->flags & (SEC_LOAD | SEC_ALLOC)) != 0)
{
@ -2227,16 +2225,15 @@ section_already_linked (bfd *abfd, asection *sec, void *data)
foo.o(.text, .data). */
/* Add SECTION to the output section OUTPUT. Do this by creating a
lang_input_section statement which is placed at PTR. FILE is the
input file which holds SECTION. */
lang_input_section statement which is placed at PTR. */
void
lang_add_section (lang_statement_list_type *ptr,
asection *section,
struct flag_info *sflag_info,
lang_output_section_statement_type *output)
{
flagword flags = section->flags;
struct flag_info *sflag_info = section->section_flag_info;
bfd_boolean discard;
lang_input_section_type *new_section;
@ -2268,24 +2265,11 @@ lang_add_section (lang_statement_list_type *ptr,
if (sflag_info)
{
if (sflag_info->flags_initialized == FALSE)
bfd_lookup_section_flags (&link_info, sflag_info);
bfd_boolean keep;
if (sflag_info->only_with_flags != 0
&& sflag_info->not_with_flags != 0
&& ((sflag_info->not_with_flags & flags) != 0
|| (sflag_info->only_with_flags & flags)
!= sflag_info->only_with_flags))
return;
if (sflag_info->only_with_flags != 0
&& (sflag_info->only_with_flags & flags)
!= sflag_info->only_with_flags)
return;
if (sflag_info->not_with_flags != 0
&& (sflag_info->not_with_flags & flags) != 0)
return;
keep = bfd_lookup_section_flags (&link_info, sflag_info, section);
if (!keep)
return;
}
if (section->output_section != NULL)
@ -2498,6 +2482,7 @@ static void
output_section_callback (lang_wild_statement_type *ptr,
struct wildcard_list *sec,
asection *section,
struct flag_info *sflag_info,
lang_input_statement_type *file,
void *output)
{
@ -2518,14 +2503,14 @@ output_section_callback (lang_wild_statement_type *ptr,
of the current list. */
if (before == NULL)
lang_add_section (&ptr->children, section, os);
lang_add_section (&ptr->children, section, sflag_info, os);
else
{
lang_statement_list_type list;
lang_statement_union_type **pp;
lang_list_init (&list);
lang_add_section (&list, section, os);
lang_add_section (&list, section, sflag_info, os);
/* If we are discarding the section, LIST.HEAD will
be NULL. */
@ -2551,6 +2536,7 @@ static void
check_section_callback (lang_wild_statement_type *ptr ATTRIBUTE_UNUSED,
struct wildcard_list *sec ATTRIBUTE_UNUSED,
asection *section,
struct flag_info *sflag_info ATTRIBUTE_UNUSED,
lang_input_statement_type *file ATTRIBUTE_UNUSED,
void *output)
{
@ -6010,7 +5996,7 @@ lang_place_orphans (void)
= lang_output_section_statement_lookup (".bss", 0,
TRUE);
lang_add_section (&default_common_section->children, s,
default_common_section);
NULL, default_common_section);
}
}
else
@ -6032,7 +6018,7 @@ lang_place_orphans (void)
&& (link_info.relocatable
|| (s->flags & (SEC_LOAD | SEC_ALLOC)) == 0))
os->addr_tree = exp_intop (0);
lang_add_section (&os->children, s, os);
lang_add_section (&os->children, s, NULL, os);
}
}
}
@ -6253,6 +6239,7 @@ static void
gc_section_callback (lang_wild_statement_type *ptr,
struct wildcard_list *sec ATTRIBUTE_UNUSED,
asection *section,
struct flag_info *sflag_info ATTRIBUTE_UNUSED,
lang_input_statement_type *file ATTRIBUTE_UNUSED,
void *data ATTRIBUTE_UNUSED)
{
@ -6324,6 +6311,7 @@ static void
find_relro_section_callback (lang_wild_statement_type *ptr ATTRIBUTE_UNUSED,
struct wildcard_list *sec ATTRIBUTE_UNUSED,
asection *section,
struct flag_info *sflag_info ATTRIBUTE_UNUSED,
lang_input_statement_type *file ATTRIBUTE_UNUSED,
void *data)
{

5
ld/ldlang.h
View file

@ -314,7 +314,8 @@ typedef struct
typedef struct lang_wild_statement_struct lang_wild_statement_type;
typedef void (*callback_t) (lang_wild_statement_type *, struct wildcard_list *,
asection *, lang_input_statement_type *, void *);
asection *, struct flag_info *,
lang_input_statement_type *, void *);
typedef void (*walk_wild_section_handler_t) (lang_wild_statement_type *,
lang_input_statement_type *,
@ -616,7 +617,7 @@ extern void lang_leave_group
(void);
extern void lang_add_section
(lang_statement_list_type *, asection *,
lang_output_section_statement_type *);
struct flag_info *, lang_output_section_statement_type *);
extern void lang_new_phdr
(const char *, etree_type *, bfd_boolean, bfd_boolean, etree_type *,
etree_type *);

35
ld/testsuite/ChangeLog
View file

@ -1,3 +1,38 @@
2012-05-14 James Lemke <jwlemke@codesourcery.com>
* ld-powerpc/powerpc.exp: Create ppceabitests.
* ld-powerpc/vle-multiseg.s: New.
* ld-powerpc/vle-multiseg-1.d: New.
* ld-powerpc/vle-multiseg-1.ld: New.
* ld-powerpc/vle-multiseg-2.d: New.
* ld-powerpc/vle-multiseg-2.ld: New.
* ld-powerpc/vle-multiseg-3.d: New.
* ld-powerpc/vle-multiseg-3.ld: New.
* ld-powerpc/vle-multiseg-4.d: New.
* ld-powerpc/vle-multiseg-4.ld: New.
* ld-powerpc/vle-multiseg-5.d: New.
* ld-powerpc/vle-multiseg-5.ld: New.
* ld-powerpc/vle-multiseg-6.d: New.
* ld-powerpc/vle-multiseg-6.ld: New.
* ld-powerpc/vle-multiseg-6a.s: New.
* ld-powerpc/vle-multiseg-6b.s: New.
* ld-powerpc/vle-multiseg-6c.s: New.
* ld-powerpc/vle-multiseg-6d.s: New.
* ld-powerpc/powerpc.exp: Run new tests.
2012-05-14 Catherine Moore <clm@codesourcery.com>
* ld-powerpc/apuinfo.rd: Update for VLE.
* ld-powerpc/vle-reloc-1.d: New.
* ld-powerpc/vle-reloc-1.s: New.
* ld-powerpc/vle-reloc-2.d: New.
* ld-powerpc/vle-reloc-2.s: New.
* ld-powerpc/vle-reloc-3.d: New.
* ld-powerpc/vle-reloc-3.s: New.
* ld-powerpc/vle-reloc-def-1.s: New.
* ld-powerpc/vle-reloc-def-2.s: New.
* ld-powerpc/vle-reloc-def-3.s: New.
2012-05-13 Richard Sandiford <rdsandiford@googlemail.com>
* ld-mips-elf/mips-elf.exp (mips16_call_global_test): Use the

5
ld/testsuite/ld-powerpc/apuinfo.rd
View file

@ -6,6 +6,7 @@
#target: powerpc-eabi*
Hex dump of section '.PPC.EMB.apuinfo':
0x00000000 00000008 0000001c 00000002 41505569 ............APUi
0x00000000 00000008 00000020 00000002 41505569 ....... ....APUi
0x00000010 6e666f00 00420001 00430001 00410001 nfo..B...C...A..
0x00000020 01020001 01010001 00400001 01000001 .........@......
0x00000020 01020001 01010001 00400001 01040001 .........@......
0x00000030 01000001 ....$

33
ld/testsuite/ld-powerpc/powerpc.exp
View file

@ -215,6 +215,33 @@ set ppc64elftests {
{{objdump -s tocopt5.d}} "tocopt5"}
}
set ppceabitests {
{"VLE multiple segments 1" "-T vle-multiseg-1.ld"
"-mregnames -mvle" {vle-multiseg.s}
{{readelf "-l" vle-multiseg-1.d}} "vle-multiseg-1"}
{"VLE multiple segments 2" "-T vle-multiseg-2.ld"
"-mregnames -mvle" {vle-multiseg.s}
{{readelf "-l" vle-multiseg-2.d}} "vle-multiseg-2"}
{"VLE multiple segments 3" "-T vle-multiseg-3.ld"
"-mregnames -mvle" {vle-multiseg.s}
{{readelf "-l" vle-multiseg-3.d}} "vle-multiseg-3"}
{"VLE multiple segments 4" "-T vle-multiseg-4.ld"
"-mregnames -mvle" {vle-multiseg.s}
{{readelf "-l" vle-multiseg-4.d}} "vle-multiseg-4"}
{"VLE multiple segments 5" "-T vle-multiseg-5.ld"
"-mregnames -mvle" {vle-multiseg.s}
{{readelf "-l" vle-multiseg-5.d}} "vle-multiseg-5"}
{"VLE relocations 1" ""
"-mvle" {vle-reloc-1.s vle-reloc-def-1.s}
{{objdump "-Mvle -d" vle-reloc-1.d}} "vle-reloc-1"}
{"VLE relocations 2" ""
"-mvle" {vle-reloc-2.s vle-reloc-def-2.s}
{{objdump "-Mvle -d" vle-reloc-2.d}} "vle-reloc-2"}
{"VLE relocations 3" ""
"-mvle" {vle-reloc-3.s vle-reloc-def-3.s}
{{objdump "-Mvle -d" vle-reloc-3.d}} "vle-reloc-3"}
}
run_ld_link_tests $ppcelftests
@ -223,6 +250,10 @@ if [ supports_ppc64 ] then {
run_dump_test "relbrlt"
}
if { [istarget "powerpc*-eabi*"] } {
run_ld_link_tests $ppceabitests
}
run_dump_test "plt1"
run_dump_test "attr-gnu-4-00"
@ -251,3 +282,5 @@ run_dump_test "attr-gnu-8-31"
run_dump_test "attr-gnu-12-11"
run_dump_test "attr-gnu-12-21"
run_dump_test "vle-multiseg-6"

14
ld/testsuite/ld-powerpc/vle-multiseg-1.d Normal file
View file

@ -0,0 +1,14 @@
Elf file type is EXEC.*
Entry point 0x0
There are 2 program headers, starting at offset [0-9]+
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
Section to Segment mapping:
Segment Sections...
00 .data
01 .text_vle .text_iv .iv_handlers

17
ld/testsuite/ld-powerpc/vle-multiseg-1.ld Normal file
View file

@ -0,0 +1,17 @@
SECTIONS
{
.data 0x00000400 :
{ *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) }
.text_vle 0x00001000 :
{
. = ALIGN(16);
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle)
}
.text_iv . : { . = ALIGN(16); *(.text_iv) }
.iv_handlers 0x0001F000 : { *(.iv_handlers) }
}

16
ld/testsuite/ld-powerpc/vle-multiseg-2.d Normal file
View file

@ -0,0 +1,16 @@
Elf file type is EXEC.*
Entry point 0x0
There are 3 program headers, starting at offset [0-9]+
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
Section to Segment mapping:
Segment Sections...
00 .text_vle
01 .data
02 .text_iv .iv_handlers

17
ld/testsuite/ld-powerpc/vle-multiseg-2.ld Normal file
View file

@ -0,0 +1,17 @@
SECTIONS
{
.text_vle 0x00001000 :
{
. = ALIGN(16);
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle)
}
.data 0x00001400 :
{ *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) }
.text_iv . : { . = ALIGN(16); *(.text_iv) }
.iv_handlers 0x0001F000 : { *(.iv_handlers) }
}

16
ld/testsuite/ld-powerpc/vle-multiseg-3.d Normal file
View file

@ -0,0 +1,16 @@
Elf file type is EXEC.*
Entry point 0x0
There are 3 program headers, starting at offset [0-9]+
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
Section to Segment mapping:
Segment Sections...
00 .text_vle .text_iv
01 .data
02 .iv_handlers

17
ld/testsuite/ld-powerpc/vle-multiseg-3.ld Normal file
View file

@ -0,0 +1,17 @@
SECTIONS
{
.text_vle 0x00001000 :
{
. = ALIGN(16);
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle)
}
.text_iv . : { . = ALIGN(16); *(.text_iv) }
.data 0x00001400 :
{ *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) }
.iv_handlers 0x0001F000 : { *(.iv_handlers) }
}

14
ld/testsuite/ld-powerpc/vle-multiseg-4.d Normal file
View file

@ -0,0 +1,14 @@
Elf file type is EXEC.*
Entry point 0x0
There are 2 program headers, starting at offset [0-9]+
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
Section to Segment mapping:
Segment Sections...
00 .text_vle .text_iv .iv_handlers
01 .data

17
ld/testsuite/ld-powerpc/vle-multiseg-4.ld Normal file
View file

@ -0,0 +1,17 @@
SECTIONS
{
.text_vle 0x00001000 :
{
. = ALIGN(16);
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle)
}
.text_iv . : { . = ALIGN(16); *(.text_iv) }
.iv_handlers 0x0001F000 : { *(.iv_handlers) }
.data 0x00020400 :
{ *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) }
}

16
ld/testsuite/ld-powerpc/vle-multiseg-5.d Normal file
View file

@ -0,0 +1,16 @@
Elf file type is EXEC.*
Entry point 0x0
There are 3 program headers, starting at offset [0-9]+
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
Section to Segment mapping:
Segment Sections...
00 .text_vle .text_iv
01 .data
02 .iv_handlers

44
ld/testsuite/ld-powerpc/vle-multiseg-5.ld Normal file
View file

@ -0,0 +1,44 @@
MEMORY
{
code_rom (rxw) : org = 0x00001000, len = 0x1EF000
irpt_rom (rx) : org = 0x001F0000, len = 0x2000
int__ram (rxw) : org = 0x40000000, len = 256K
}
REGION_ALIAS("INTR", irpt_rom)
REGION_ALIAS("CODE", code_rom)
REGION_ALIAS("RODATA", code_rom)
REGION_ALIAS("RAM", int__ram)
SECTIONS
{
.iv_handlers :
{
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.iv_handlers)
} > INTR
.text_vle :
{
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle)
} > CODE
.rodata :
{
*(.rodata)
} > RODATA
.data :
{
*(.data)
*(.data.*)
*(.ctors)
*(.dtors)
} > RAM AT>RODATA
}

25
ld/testsuite/ld-powerpc/vle-multiseg-6.d Normal file
View file

@ -0,0 +1,25 @@
#source: vle-multiseg-6a.s -mregnames -mvle
#source: vle-multiseg-6b.s
#source: vle-multiseg-6c.s
#source: vle-multiseg-6d.s -mregnames -mvle
#ld: -T vle-multiseg-6.ld
#target: powerpc-*-*
#readelf: -l
Elf file type is EXEC.*
Entry point 0x[0-9a-f]+
There are 4 program headers, starting at offset [0-9]+
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
Section to Segment mapping:
Segment Sections...
00 .data
01 .text_vle
02 .text_iv
03 .text

37
ld/testsuite/ld-powerpc/vle-multiseg-6.ld Normal file
View file

@ -0,0 +1,37 @@
MEMORY
{
vle_seg1 (rxw): org = 0x00000000, len = 0x10000
vle_seg2 (rxw): org = 0x00100000, len = 0x10000
nonvle_seg (rxw): org = 0x001F0000, len = 0x20000
}
SECTIONS
{
.data 0x00000100 :
{
*(.data)
*(.ctors)
*(.dtors)
*(.eh_frame)
*(.jcr)
}
.text_vle 0x00001000 :
{
. = ALIGN(16);
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text*)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init*)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini*)
} > vle_seg1
.text_iv 0x100000 :
{
. = ALIGN(16);
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_iv)
INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.iv_handlers)
} >vle_seg2
.text 0x101000 :
{
. = ALIGN(16);
INPUT_SECTION_FLAGS (!SHF_PPC_VLE) *(.text*)
}
}

47
ld/testsuite/ld-powerpc/vle-multiseg-6a.s Normal file
View file

@ -0,0 +1,47 @@
.text
e_stw r12, 0x4C(r1)
e_stw r11, 0x48(r1)
e_stw r10, 0x44(r1)
e_stw r9, 0x40(r1)
e_stw r8, 0x3C(r1)
e_stw r7, 0x38(r1)
e_stw r6, 0x34(r1)
e_stw r5, 0x30(r1)
e_stw r4, 0x2c(r1)
.globl IV_table
.section ".iv_handlers", "ax"
IV_table:
e_b dummy
.align 4
e_b dummy
.align 4
e_b dummy
.align 4
e_b dummy
.align 4
e_b dummy
.align 4
e_b dummy
.align 4
e_b dummy
.align 4
e_b dummy
.align 4
dummy:
se_nop
e_b dummy
.section ".text_iv", "ax"
e_lis r3, IV_table@h
mtivpr r3
e_li r3, IV_table@l+0x00
mtivor0 r3
e_li r3, IV_table@l+0x10
mtivor1 r3
e_li r3, IV_table@l+0x20
mtivor2 r3
.data
.long 0xdeadbeef

6
ld/testsuite/ld-powerpc/vle-multiseg-6b.s Normal file
View file

@ -0,0 +1,6 @@
.text
and. 3,4,5
and 3,4,5
andc 13,14,15
andc. 16,17,18

6
ld/testsuite/ld-powerpc/vle-multiseg-6c.s Normal file
View file

@ -0,0 +1,6 @@
.text
and. 3,4,5
and 3,4,5
andc 13,14,15
andc. 16,17,18

9
ld/testsuite/ld-powerpc/vle-multiseg-6d.s Normal file
View file

@ -0,0 +1,9 @@
.section ".text_iv", "ax"
e_lis r3, IV_table@h
mtivpr r3
e_li r3, IV_table@l+0x00
mtivor0 r3
e_li r3, IV_table@l+0x10
mtivor1 r3
e_li r3, IV_table@l+0x20
mtivor2 r3

50
ld/testsuite/ld-powerpc/vle-multiseg.s Normal file
View file

@ -0,0 +1,50 @@
# Make up several VLE text sections which the linker script will put into
# separate output sections. We will then check for separate load segments.
# .include "mpc5500_usrdefs.inc"
# .section ".text_vle"
e_stw r12, 0x4C(r1)
e_stw r11, 0x48(r1)
e_stw r10, 0x44(r1)
e_stw r9, 0x40(r1)
e_stw r8, 0x3C(r1)
e_stw r7, 0x38(r1)
e_stw r6, 0x34(r1)
e_stw r5, 0x30(r1)
e_stw r4, 0x2c(r1)
.globl IV_table
.section ".iv_handlers", "ax"
IV_table:
e_b dummy
.align 4
e_b dummy
.align 4
e_b dummy
.align 4
e_b dummy
.align 4
e_b dummy
.align 4
e_b dummy
.align 4
e_b dummy
.align 4
e_b dummy
.align 4
dummy:
se_nop
e_b dummy
.section ".text_iv", "ax"
e_lis r3, IV_table@h
mtivpr r3
e_li r3, IV_table@l+0x00
mtivor0 r3
e_li r3, IV_table@l+0x10
mtivor1 r3
e_li r3, IV_table@l+0x20
mtivor2 r3
.data
.long 0xdeadbeef

29
ld/testsuite/ld-powerpc/vle-reloc-1.d Normal file
View file

@ -0,0 +1,29 @@
.*: file format .*
Disassembly of section .text:
01800054 <sub1>:
1800054: 00 04 se_blr
01800056 <sub2>:
1800056: 00 04 se_blr
01800058 <vle_reloc>:
1800058: e8 fe se_b 1800054 <sub1>
180005a: e9 fd se_bl 1800054 <sub1>
180005c: e1 fd se_ble 1800056 <sub2>
180005e: e6 fc se_beq 1800056 <sub2>
1800060: 78 00 00 10 e_b 1800070 <sub3>
1800064: 78 00 00 0f e_bl 1800072 <sub4>
1800068: 7a 05 00 0c e_ble cr1,1800074 <sub5>
180006c: 7a 1a 00 09 e_beql cr2,1800074 <sub5>
01800070 <sub3>:
1800070: 00 04 se_blr
01800072 <sub4>:
1800072: 00 04 se_blr
01800074 <sub5>:
1800074: 00 04 se_blr

18
ld/testsuite/ld-powerpc/vle-reloc-1.s Normal file
View file

@ -0,0 +1,18 @@
.section .text
sub1:
se_blr
sub2:
se_blr
.section .text
vle_reloc:
se_b sub1
se_bl sub1
se_bc 0,1,sub2
se_bc 1,2,sub2
e_b sub3
e_bl sub4
e_bc 0,5,sub5
e_bcl 1,10,sub5

87
ld/testsuite/ld-powerpc/vle-reloc-2.d Normal file
View file

@ -0,0 +1,87 @@
.*: file format .*
Disassembly of section .text:
01800094 <sub1>:
1800094: 00 04 se_blr
01800096 <sub2>:
1800096: 00 04 se_blr
01800098 <vle_reloc_2>:
1800098: 70 20 c1 c2 e_or2i r1,450
180009c: 70 40 c1 81 e_or2i r2,385
18000a0: 70 60 c1 81 e_or2i r3,385
18000a4: 70 80 c1 ce e_or2i r4,462
18000a8: 70 a0 c1 80 e_or2i r5,384
18000ac: 70 40 c1 81 e_or2i r2,385
18000b0: 70 20 c9 c2 e_and2i. r1,450
18000b4: 70 40 c9 81 e_and2i. r2,385
18000b8: 70 60 c9 81 e_and2i. r3,385
18000bc: 70 80 c9 ce e_and2i. r4,462
18000c0: 70 a0 c9 80 e_and2i. r5,384
18000c4: 70 40 c9 81 e_and2i. r2,385
18000c8: 70 20 d1 c2 e_or2is r1,450
18000cc: 70 40 d1 81 e_or2is r2,385
18000d0: 70 60 d1 81 e_or2is r3,385
18000d4: 70 80 d1 ce e_or2is r4,462
18000d8: 70 a0 d1 80 e_or2is r5,384
18000dc: 70 40 d1 81 e_or2is r2,385
18000e0: 70 20 e1 c2 e_lis r1,450
18000e4: 70 40 e1 81 e_lis r2,385
18000e8: 70 60 e1 81 e_lis r3,385
18000ec: 70 80 e1 ce e_lis r4,462
18000f0: 70 a0 e1 80 e_lis r5,384
18000f4: 70 40 e1 81 e_lis r2,385
18000f8: 70 20 e9 c2 e_and2is. r1,450
18000fc: 70 40 e9 81 e_and2is. r2,385
1800100: 70 60 e9 81 e_and2is. r3,385
1800104: 70 80 e9 ce e_and2is. r4,462
1800108: 70 a0 e9 80 e_and2is. r5,384
180010c: 70 40 e9 81 e_and2is. r2,385
1800110: 70 01 99 c2 e_cmp16i r1,450
1800114: 70 02 99 81 e_cmp16i r2,385
1800118: 70 03 99 81 e_cmp16i r3,385
180011c: 70 04 99 ce e_cmp16i r4,462
1800120: 70 05 99 80 e_cmp16i r5,384
1800124: 70 02 99 81 e_cmp16i r2,385
1800128: 70 01 a9 c2 e_cmpl16i r1,450
180012c: 70 02 a9 81 e_cmpl16i r2,385
1800130: 70 03 a9 81 e_cmpl16i r3,385
1800134: 70 04 a9 ce e_cmpl16i r4,462
1800138: 70 05 a9 80 e_cmpl16i r5,384
180013c: 70 02 a9 81 e_cmpl16i r2,385
1800140: 70 01 b1 c2 e_cmph16i r1,450
1800144: 70 02 b1 81 e_cmph16i r2,385
1800148: 70 03 b1 81 e_cmph16i r3,385
180014c: 70 04 b1 ce e_cmph16i r4,462
1800150: 70 05 b1 80 e_cmph16i r5,384
1800154: 70 02 b1 81 e_cmph16i r2,385
1800158: 70 01 b9 c2 e_cmphl16i r1,450
180015c: 70 02 b9 81 e_cmphl16i r2,385
1800160: 70 03 b9 81 e_cmphl16i r3,385
1800164: 70 04 b9 ce e_cmphl16i r4,462
1800168: 70 05 b9 80 e_cmphl16i r5,384
180016c: 70 02 b9 81 e_cmphl16i r2,385
1800170: 70 01 89 c2 e_add2i. r1,450
1800174: 70 02 89 81 e_add2i. r2,385
1800178: 70 03 89 81 e_add2i. r3,385
180017c: 70 04 89 ce e_add2i. r4,462
1800180: 70 05 89 80 e_add2i. r5,384
1800184: 70 02 89 81 e_add2i. r2,385
1800188: 70 01 91 c2 e_add2is r1,450
180018c: 70 02 91 81 e_add2is r2,385
1800190: 70 03 91 81 e_add2is r3,385
1800194: 70 04 91 ce e_add2is r4,462
1800198: 70 05 91 80 e_add2is r5,384
180019c: 70 02 91 81 e_add2is r2,385
18001a0: 70 01 a1 c2 e_mull2i r1,450
18001a4: 70 02 a1 81 e_mull2i r2,385
18001a8: 70 03 a1 81 e_mull2i r3,385
18001ac: 70 04 a1 ce e_mull2i r4,462
18001b0: 70 05 a1 80 e_mull2i r5,384
18001b4: 70 02 a1 81 e_mull2i r2,385
018001b8 <sub3>:
18001b8: 00 04 se_blr
018001ba <sub4>:
18001ba: 00 04 se_blr
018001bc <sub5>:
18001bc: 00 04 se_blr

92
ld/testsuite/ld-powerpc/vle-reloc-2.s Normal file
View file

@ -0,0 +1,92 @@
.section .text
sub1:
se_blr
sub2:
se_blr
.section .text
vle_reloc_2:
e_or2i 1, low@l
e_or2i 2, high@h
e_or2i 3, high_adjust@ha
e_or2i 4, low_sdarel@sdarel@l
e_or2i 5, high_sdarel@sdarel@h
e_or2i 2, high_adjust_sdarel@sdarel@ha
e_and2i. 1, low@l
e_and2i. 2, high@h
e_and2i. 3, high_adjust@ha
e_and2i. 4, low_sdarel@sdarel@l
e_and2i. 5, high_sdarel@sdarel@h
e_and2i. 2, high_adjust_sdarel@sdarel@ha
e_or2is 1, low@l
e_or2is 2, high@h
e_or2is 3, high_adjust@ha
e_or2is 4, low_sdarel@sdarel@l
e_or2is 5, high_sdarel@sdarel@h
e_or2is 2, high_adjust_sdarel@sdarel@ha
e_lis 1, low@l
e_lis 2, high@h
e_lis 3, high_adjust@ha
e_lis 4, low_sdarel@sdarel@l
e_lis 5, high_sdarel@sdarel@h
e_lis 2, high_adjust_sdarel@sdarel@ha
e_and2is. 1, low@l
e_and2is. 2, high@h
e_and2is. 3, high_adjust@ha
e_and2is. 4, low_sdarel@sdarel@l
e_and2is. 5, high_sdarel@sdarel@h
e_and2is. 2, high_adjust_sdarel@sdarel@ha
e_cmp16i 1, low@l
e_cmp16i 2, high@h
e_cmp16i 3, high_adjust@ha
e_cmp16i 4, low_sdarel@sdarel@l
e_cmp16i 5, high_sdarel@sdarel@h
e_cmp16i 2, high_adjust_sdarel@sdarel@ha
e_cmpl16i 1, low@l
e_cmpl16i 2, high@h
e_cmpl16i 3, high_adjust@ha
e_cmpl16i 4, low_sdarel@sdarel@l
e_cmpl16i 5, high_sdarel@sdarel@h
e_cmpl16i 2, high_adjust_sdarel@sdarel@ha
e_cmph16i 1, low@l
e_cmph16i 2, high@h
e_cmph16i 3, high_adjust@ha
e_cmph16i 4, low_sdarel@sdarel@l
e_cmph16i 5, high_sdarel@sdarel@h
e_cmph16i 2, high_adjust_sdarel@sdarel@ha
e_cmphl16i 1, low@l
e_cmphl16i 2, high@h
e_cmphl16i 3, high_adjust@ha
e_cmphl16i 4, low_sdarel@sdarel@l
e_cmphl16i 5, high_sdarel@sdarel@h
e_cmphl16i 2, high_adjust_sdarel@sdarel@ha
e_add2i. 1, low@l
e_add2i. 2, high@h
e_add2i. 3, high_adjust@ha
e_add2i. 4, low_sdarel@sdarel@l
e_add2i. 5, high_sdarel@sdarel@h
e_add2i. 2, high_adjust_sdarel@sdarel@ha
e_add2is 1, low@l
e_add2is 2, high@h
e_add2is 3, high_adjust@ha
e_add2is 4, low_sdarel@sdarel@l
e_add2is 5, high_sdarel@sdarel@h
e_add2is 2, high_adjust_sdarel@sdarel@ha
e_mull2i 1, low@l
e_mull2i 2, high@h
e_mull2i 3, high_adjust@ha
e_mull2i 4, low_sdarel@sdarel@l
e_mull2i 5, high_sdarel@sdarel@h
e_mull2i 2, high_adjust_sdarel@sdarel@ha

8
ld/testsuite/ld-powerpc/vle-reloc-3.d Normal file
View file

@ -0,0 +1,8 @@
.*: file format .*
Disassembly of section .text:
01800094 <sda21_test>:
1800094: 1c ad 80 08 e_add16i r5,r13,-32760
1800098: 1c a2 80 04 e_add16i r5,r2,-32764
180009c: 70 00 00 ac e_li r0,172

10
ld/testsuite/ld-powerpc/vle-reloc-3.s Normal file
View file

@ -0,0 +1,10 @@
.section .text
.extern exdat1c
.extern exdat2b
.extern exdat1a
.globl sda21_test
sda21_test:
e_add16i 5, 4, exdat1c@sda21
e_add16i 5, 4, exdat2b@sda21
e_add16i 5, 4, exdat0b@sda21

13
ld/testsuite/ld-powerpc/vle-reloc-def-1.s Normal file
View file

@ -0,0 +1,13 @@
.section .text
.globl sub3
sub3:
se_blr
.globl sub4
sub4:
se_blr
.globl sub5
sub5:
se_blr

41
ld/testsuite/ld-powerpc/vle-reloc-def-2.s Normal file
View file

@ -0,0 +1,41 @@
.section .text
.globl sub3
sub3:
se_blr
.globl sub4
sub4:
se_blr
.globl sub5
sub5:
se_blr
.section .sdata
.globl low_sdarel
low_sdarel:
.long 2
.globl high_adjust_sdarel
high_adjust_sdarel:
.long 0xff
.section .sdata2
.globl high_sdarel
high_sdarel:
.long 0xf
.data
.globl low
low:
.long 5
.globl high
high:
.long 0x10
.globl high_adjust
high_adjust:
.long 0xffff

29
ld/testsuite/ld-powerpc/vle-reloc-def-3.s Normal file
View file

@ -0,0 +1,29 @@
.section .sdata
.globl exdat1a
.globl exdat1b
.globl exdat1c
exdat1a: .long 6
exdat1b: .long 7
exdat1c: .long 8
.section .sdata2
.globl exdat2a
.globl exdat2b
.globl exdat2c
exdat2a: .long 5
exdat2b: .long 4
exdat2c: .long 3
.section .PPC.EMB.sdata0
.globl exdat0a
.globl exdat0b
.globl exdat0c
exdat0a: .long 1
exdat0b: .long 2
exdat0c: .long 3
.section .sbss
.globl exbss1a
.globl exbss1b
exbss1a: .int
exbss1b: .int

64
opcodes/ChangeLog
View file

@ -1,3 +1,67 @@
2012-05-14 James Lemke <jwlemke@codesourcery.com>
* ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
(PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
(vle_opcd_indices): New array.
(lookup_vle): New function.
(disassemble_init_powerpc): Revise for second (VLE) opcode table.
(print_insn_powerpc): Likewise.
* ppc-opc.c: Likewise.
2012-05-14 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Rhonda Wittels <rhonda@codesourcery.com>
Nathan Froyd <froydnj@codesourcery.com>
* ppc-opc.c (insert_arx, extract_arx): New functions.
(insert_ary, extract_ary): New functions.
(insert_li20, extract_li20): New functions.
(insert_rx, extract_rx): New functions.
(insert_ry, extract_ry): New functions.
(insert_sci8, extract_sci8): New functions.
(insert_sci8n, extract_sci8n): New functions.
(insert_sd4h, extract_sd4h): New functions.
(insert_sd4w, extract_sd4w): New functions.
(insert_vlesi, extract_vlesi): New functions.
(insert_vlensi, extract_vlensi): New functions.
(insert_vleui, extract_vleui): New functions.
(insert_vleil, extract_vleil): New functions.
(BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
(BI16, BI32, BO32, B8): New.
(B15, B24, CRD32, CRS): New.
(CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
(DB, IMM20, RD, Rx, ARX, RY, RZ): New.
(ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
(SH6_MASK): Use PPC_OPSHIFT_INV.
(SI8, UI5, OIMM5, UI7, BO16): New.
(VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
(XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
(ALLOW8_SPRG): New.
(insert_sprg, extract_sprg): Check ALLOW8_SPRG.
(OPVUP, OPVUP_MASK OPVUP): New
(BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
(EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
(BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
(BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
(IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
(IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
(SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
(SE_IM5, SE_IM5_MASK): New.
(SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
(EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
(BO32DNZ, BO32DZ): New.
(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
(PPCVLE): New.
(powerpc_opcodes): Add new VLE instructions. Update existing
instruction to include PPCVLE if supported.
* ppc-dis.c (ppc_opts): Add vle entry.
(get_powerpc_dialect): New function.
(powerpc_init_dialect): VLE support.
(print_insn_big_powerpc): Call get_powerpc_dialect.
(print_insn_little_powerpc): Likewise.
(operand_value_powerpc): Handle negative shift counts.
(print_insn_powerpc): Handle 2-byte instruction lengths.
2012-05-11 Daniel Richard G. <skunk@iskunk.org>
PR binutils/14028

210
opcodes/ppc-dis.c
View file

@ -23,6 +23,9 @@
#include <stdio.h>
#include "sysdep.h"
#include "dis-asm.h"
#include "elf-bfd.h"
#include "elf32-ppc.h"
#include "elf/ppc.h"
#include "opintl.h"
#include "opcode/ppc.h"
@ -181,18 +184,38 @@ struct ppc_mopt ppc_opts[] = {
{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
0 },
{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
PPC_OPCODE_VLE },
{ "vsx", (PPC_OPCODE_PPC),
PPC_OPCODE_VSX },
};
/* Switch between Booke and VLE dialects for interlinked dumps. */
static ppc_cpu_t
get_powerpc_dialect (struct disassemble_info *info)
{
ppc_cpu_t dialect = 0;
dialect = POWERPC_DIALECT (info);
/* Disassemble according to the section headers flags for VLE-mode. */
if (dialect & PPC_OPCODE_VLE
&& is_ppc_vle (info->section))
return dialect;
else
return dialect & ~ PPC_OPCODE_VLE;
}
/* Handle -m and -M options that set cpu type, and .machine arg. */
ppc_cpu_t
ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg)
{
const ppc_cpu_t retain_mask = (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
| PPC_OPCODE_SPE | PPC_OPCODE_ANY
| PPC_OPCODE_VLE | PPC_OPCODE_PMR);
/* Sticky bits. */
ppc_cpu_t retain_flags = ppc_cpu & (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
| PPC_OPCODE_SPE | PPC_OPCODE_ANY);
ppc_cpu_t retain_flags = ppc_cpu & retain_mask;
unsigned int i;
for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
@ -201,8 +224,7 @@ ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg)
if (ppc_opts[i].sticky)
{
retain_flags |= ppc_opts[i].sticky;
if ((ppc_cpu & ~(ppc_cpu_t) (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
| PPC_OPCODE_SPE | PPC_OPCODE_ANY)) != 0)
if ((ppc_cpu & ~retain_mask) != 0)
break;
}
ppc_cpu = ppc_opts[i].cpu;
@ -256,16 +278,22 @@ powerpc_init_dialect (struct disassemble_info *info)
dialect |= PPC_OPCODE_64;
else
dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
/* Choose a reasonable default. */
dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
| PPC_OPCODE_ALTIVEC);
if (info->mach == bfd_mach_ppc_vle)
dialect |= PPC_OPCODE_PPC | PPC_OPCODE_VLE;
else
/* Choose a reasonable default. */
dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
| PPC_OPCODE_ALTIVEC);
}
info->private_data = priv;
POWERPC_DIALECT(info) = dialect;
}
static unsigned short powerpc_opcd_indices[65];
#define PPC_OPCD_SEGS 64
static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
#define VLE_OPCD_SEGS 32
static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
/* Calculate opcode table indices to speed up disassembly,
and init dialect. */
@ -285,13 +313,30 @@ disassemble_init_powerpc (struct disassemble_info *info)
}
last = powerpc_num_opcodes;
for (i = 64; i > 0; --i)
for (i = PPC_OPCD_SEGS; i > 0; --i)
{
if (powerpc_opcd_indices[i] == 0)
powerpc_opcd_indices[i] = last;
last = powerpc_opcd_indices[i];
}
i = vle_num_opcodes;
while (--i >= 0)
{
unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
unsigned seg = VLE_OP_TO_SEG (op);
vle_opcd_indices[seg] = i;
}
last = vle_num_opcodes;
for (i = VLE_OPCD_SEGS; i > 0; --i)
{
if (vle_opcd_indices[i] == 0)
vle_opcd_indices[i] = last;
last = vle_opcd_indices[i];
}
if (info->arch == bfd_arch_powerpc)
powerpc_init_dialect (info);
}
@ -301,7 +346,7 @@ disassemble_init_powerpc (struct disassemble_info *info)
int
print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
{
return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT(info));
return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
}
/* Print a little endian PowerPC instruction. */
@ -309,7 +354,7 @@ print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
int
print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
{
return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT(info));
return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
}
/* Print a POWER (RS/6000) instruction. */
@ -333,11 +378,14 @@ operand_value_powerpc (const struct powerpc_operand *operand,
value = (*operand->extract) (insn, dialect, &invalid);
else
{
value = (insn >> operand->shift) & operand->bitm;
if (operand->shift >= 0)
value = (insn >> operand->shift) & operand->bitm;
else
value = (insn << -operand->shift) & operand->bitm;
if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
{
/* BITM is always some number of zeros followed by some
number of ones, followed by some numer of zeros. */
number of ones, followed by some number of zeros. */
unsigned long top = operand->bitm;
/* top & -top gives the rightmost 1 bit, so this
fills in any trailing zeros. */
@ -372,7 +420,7 @@ skip_optional_operands (const unsigned char *opindex,
/* Find a match for INSN in the opcode table, given machine DIALECT.
A DIALECT of -1 is special, matching all machine opcode variations. */
static const struct powerpc_opcode *
lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
{
@ -416,6 +464,60 @@ lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
return NULL;
}
/* Find a match for INSN in the VLE opcode table. */
static const struct powerpc_opcode *
lookup_vle (unsigned long insn)
{
const struct powerpc_opcode *opcode;
const struct powerpc_opcode *opcode_end;
unsigned op, seg;
op = PPC_OP (insn);
if (op >= 0x20 && op <= 0x37)
{
/* This insn has a 4-bit opcode. */
op &= 0x3c;
}
seg = VLE_OP_TO_SEG (op);
/* Find the first match in the opcode table for this major opcode. */
opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
for (opcode = vle_opcodes + vle_opcd_indices[seg];
opcode < opcode_end;
++opcode)
{
unsigned long table_opcd = opcode->opcode;
unsigned long table_mask = opcode->mask;
bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
unsigned long insn2;
const unsigned char *opindex;
const struct powerpc_operand *operand;
int invalid;
insn2 = insn;
if (table_op_is_short)
insn2 >>= 16;
if ((insn2 & table_mask) != table_opcd)
continue;
/* Check validity of operands. */
invalid = 0;
for (opindex = opcode->operands; *opindex != 0; ++opindex)
{
operand = powerpc_operands + *opindex;
if (operand->extract)
(*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
}
if (invalid)
continue;
return opcode;
}
return NULL;
}
/* Print a PowerPC or POWER instruction. */
static int
@ -428,12 +530,28 @@ print_insn_powerpc (bfd_vma memaddr,
int status;
unsigned long insn;
const struct powerpc_opcode *opcode;
bfd_boolean insn_is_short;
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
/* The final instruction may be a 2-byte VLE insn. */
if ((dialect & PPC_OPCODE_VLE) != 0)
{
/* Clear buffer so unused bytes will not have garbage in them. */
buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
}
else
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
}
if (bigendian)
@ -441,7 +559,17 @@ print_insn_powerpc (bfd_vma memaddr,
else
insn = bfd_getl32 (buffer);
opcode = lookup_powerpc (insn, dialect);
/* Get the major opcode of the insn. */
opcode = NULL;
insn_is_short = FALSE;
if ((dialect & PPC_OPCODE_VLE) != 0)
{
opcode = lookup_vle (insn);
if (opcode != NULL)
insn_is_short = PPC_OP_SE_VLE(opcode->mask);
}
if (opcode == NULL)
opcode = lookup_powerpc (insn, dialect);
if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
@ -458,6 +586,10 @@ print_insn_powerpc (bfd_vma memaddr,
else
(*info->fprintf_func) (info->stream, "%s", opcode->name);
if (insn_is_short)
/* The operands will be fetched out of the 16-bit instruction. */
insn >>= 16;
/* Now extract and print the operands. */
need_comma = 0;
need_paren = 0;
@ -513,26 +645,26 @@ print_insn_powerpc (bfd_vma memaddr,
(*info->fprintf_func) (info->stream, "fcr%ld", value);
else if ((operand->flags & PPC_OPERAND_UDI) != 0)
(*info->fprintf_func) (info->stream, "%ld", value);
else if ((operand->flags & PPC_OPERAND_CR) != 0
&& (dialect & PPC_OPCODE_PPC) != 0)
else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
&& (((dialect & PPC_OPCODE_PPC) != 0)
|| ((dialect & PPC_OPCODE_VLE) != 0)))
(*info->fprintf_func) (info->stream, "cr%ld", value);
else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
&& (((dialect & PPC_OPCODE_PPC) != 0)
|| ((dialect & PPC_OPCODE_VLE) != 0)))
{
if (operand->bitm == 7)
(*info->fprintf_func) (info->stream, "cr%ld", value);
else
{
static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
int cr;
int cc;
static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
int cr;
int cc;
cr = value >> 2;
if (cr != 0)
(*info->fprintf_func) (info->stream, "4*cr%d+", cr);
cc = value & 3;
(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
}
cr = value >> 2;
if (cr != 0)
(*info->fprintf_func) (info->stream, "4*cr%d+", cr);
cc = value & 3;
(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
}
else
(*info->fprintf_func) (info->stream, "%ld", value);
(*info->fprintf_func) (info->stream, "%d", value);
if (need_paren)
{
@ -549,8 +681,16 @@ print_insn_powerpc (bfd_vma memaddr,
}
}
/* We have found and printed an instruction; return. */
return 4;
/* We have found and printed an instruction.
If it was a short VLE instruction we have more to do. */
if (insn_is_short)
{
memaddr += 2;
return 2;
}
else
/* Otherwise, return. */
return 4;
}
/* We could not find a match. */

2578
opcodes/ppc-opc.c
View file

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