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Add support for sparc %cfr ASR register.

Browse source 
opcodes/

	* sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
	* sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.

gas/

	* config/tc-sparc.c (v9a_asr_table): Add 'cfr'.

gas/testsuite/

	* gas/sparc/sparc.exp: Run cfr test.
	* gas/sparc/cfr.s: New testcase.
	* gas/sparc/cfr.d: Likewise.
This commit is contained in:
David S. Miller 2012-04-27 20:43:35 +00:00
parent 22d2b532b8
commit 2e52845baf
9 changed files with 38 additions and 1 deletions
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2
gas/ChangeLog
View file

@ -1,5 +1,7 @@
2012-04-27 David S. Miller <davem@davemloft.net>
* config/tc-sparc.c (v9a_asr_table): Add 'cfr'.
* config/tc-sparc.c (sparc_arch_table): Add HWCAP_PAUSE to sparc4,
v8pluse, v8plusv, v9e, and v9v.
(v9a_asr_table): Add 'pause'.

1
gas/config/tc-sparc.c
View file

@ -805,6 +805,7 @@ struct priv_reg_entry v9a_asr_table[] =
{"gsr", 19},
{"dcr", 18},
{"cps", 28},
{"cfr", 26},
{"clear_softint", 21},
{"", -1}, /* End marker. */
};

4
gas/testsuite/ChangeLog
View file

@ -1,5 +1,9 @@
2012-04-27 David S. Miller <davem@davemloft.net>
* gas/sparc/sparc.exp: Run cfr test.
* gas/sparc/cfr.s: New testcase.
* gas/sparc/cfr.d: Likewise.
* gas/sparc/sparc.exp: Run pause test.
* gas/sparc/pause.s: New testcase.
* gas/sparc/pause.d: Likewise.

15
gas/testsuite/gas/sparc/cfr.d Normal file
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@ -0,0 +1,15 @@
#as: -Av9v
#objdump: -dr
#name: sparc CFR
.*: +file format .*sparc.*
Disassembly of section .text:
0+ <.text>:
0: b5 82 40 16 wr %o1, %l6, %cfr
4: b5 80 62 34 wr %g1, 0x234, %cfr
8: 8b 46 80 00 rd %cfr, %g5
c: 97 46 80 00 rd %cfr, %o3
10: b5 46 80 00 rd %cfr, %i2
14: a9 46 80 00 rd %cfr, %l4

8
gas/testsuite/gas/sparc/cfr.s Normal file
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@ -0,0 +1,8 @@
# Test read/write %cfr instructions
.text
wr %o1, %l6, %cfr
wr %g1, 0x234, %cfr
rd %cfr, %g5
rd %cfr, %o3
rd %cfr, %i2
rd %cfr, %l4

1
gas/testsuite/gas/sparc/sparc.exp
View file

@ -65,6 +65,7 @@ if [istarget sparc*-*-*] {
run_dump_test "crypto"
run_dump_test "cbcond"
run_dump_test "pause"
run_dump_test "cfr"
run_list_test "pr4587" ""
}

3
opcodes/ChangeLog
View file

@ -1,5 +1,8 @@
2012-04-27 David S. Miller <davem@davemloft.net>
* sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
* sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
* sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
* sparc-dis.c (v9a_asr_reg_names): Add 'pause'.

2
opcodes/sparc-dis.c
View file

@ -108,7 +108,7 @@ static char *v9_hpriv_reg_names[] =
static char *v9a_asr_reg_names[] =
{
"pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
"softint", "tick_cmpr", "stick", "stick_cmpr", "resv26",
"softint", "tick_cmpr", "stick", "stick_cmpr", "cfr",
"pause", "cps"
};

3
opcodes/sparc-opc.c
View file

@ -876,6 +876,8 @@ const struct sparc_opcode sparc_opcodes[] = {
{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick */
{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", HWCAP_VIS2, 0, v9b }, /* wr r,r,%sys_tick_cmpr */
{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick_cmpr */
{ "wr", F3(2, 0x30, 0)|RD(26), F3(~2, ~0x30, ~0)|RD(~26)|ASI(~0), "1,2,_", 0, HWCAP_CBCOND, v9b }, /* wr r,r,%cfr */
{ "wr", F3(2, 0x30, 1)|RD(26), F3(~2, ~0x30, ~1)|RD(~26), "1,i,_", 0, HWCAP_CBCOND, v9b }, /* wr r,i,%cfr */
{ "wr", F3(2, 0x30, 0)|RD(27), F3(~2, ~0x30, ~0)|RD(~27)|ASI(~0), "1,2,_", 0, HWCAP_PAUSE, v9b }, /* wr r,r,%pause */
{ "wr", F3(2, 0x30, 1)|RD(27), F3(~2, ~0x30, ~1)|RD(~27), "1,i,_", 0, HWCAP_PAUSE, v9b }, /* wr r,i,%pause */
{ "wr", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|ASI(~0), "1,2,_", 0, HWCAP_VIS3, v9b }, /* wr r,r,%cps */
@ -903,6 +905,7 @@ const struct sparc_opcode sparc_opcodes[] = {
{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %tick_cmpr,r */
{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", HWCAP_VIS2, 0, v9b }, /* rd %sys_tick,r */
{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", HWCAP_VIS2, 0, v9b }, /* rd %sys_tick_cmpr,r */
{ "rd", F3(2, 0x28, 0)|RS1(26), F3(~2, ~0x28, ~0)|RS1(~26)|SIMM13(~0), "/,d", HWCAP_CBCOND, 0, v9b }, /* rd %cfr,r */
{ "rd", F3(2, 0x28, 0)|RS1(28), F3(~2, ~0x28, ~0)|RS1(~28)|SIMM13(~0), "/,d", 0, HWCAP_VIS3, v9b }, /* rd %cps,r */
{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, 0, v9 }, /* rdpr %priv,r */