old-cross-binutils/sim/mips
Andrew Cagney f23e93dab0 * mips.igen: Tag vr5000 instructions.
(ANDI): Was missing mipsIV model, fix assembler syntax.
        (do_c_cond_fmt): New function.
        (C.cond.fmt): Handle mips I-III which do not support CC field
        separatly.
        (bc1): Handle mips IV which do not have a delaed FCC separatly.
        (SDR): Mask paddr when BigEndianMem, not the converse as specified
        in IV3.2 spec.
        (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
        vr5000 which saves LO in a GPR separatly.
        * configure.in (enable-sim-igen): For vr5000, select vr5000
        specific instructions.
        * configure: Re-generate.
1997-11-14 08:27:38 +00:00
..
.Sanitize * gencode.c: Add tx49 configury and insns. 1997-10-29 19:42:49 +00:00
ChangeLog * mips.igen: Tag vr5000 instructions. 1997-11-14 08:27:38 +00:00
config.in Get configure to define RETSIGTYPE 1997-04-07 05:58:59 +00:00
configure * gencode.c: Add tx49 configury and insns. 1997-10-29 19:42:49 +00:00
configure.in * mips.igen: Tag vr5000 instructions. 1997-11-14 08:27:38 +00:00
gencode.c Replace global IPC with function argument cia or current instruction 1997-11-06 14:24:57 +00:00
interp.c Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1, 1997-11-11 07:50:13 +00:00
m16.igen Separate r5900 specifoc and mips16 instructions. 1997-10-27 07:55:24 +00:00
Makefile.in IGEN likes to cache the current instruction address (CIA). Change the 1997-11-06 09:16:16 +00:00
mips.dc MIPS/IGEN checkpoint - doesn't build. 1997-10-08 04:16:01 +00:00
mips.igen Make the signess of compares between GPR's explicit using a cast to 1997-11-11 12:31:24 +00:00
README.Cygnus
sim-main.h Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1, 1997-11-11 07:50:13 +00:00
tconfig.in * Makefile.in: Delete stuff moved to ../common/Make-common.in. 1996-11-20 10:00:42 +00:00
vr5400.igen Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1, 1997-11-11 07:50:13 +00:00

> README.Cygnus
-------------------------------------------------------------------------------

The following are the main reasons for constructing the simulator as a
generator:

1) Avoid large fixed decode source file, with lots of #ifs controlling
   the compilation. i.e. keep the source cleaner, smaller and easier
   to parse.

2) Allow optimum code to be created, without run-time checks on
   instruction types. Ensure that the simulator engine only includes
   code for the architecture being targetted. e.g. This avoids
   run-time checks on ISA conformance, aswell as increasing
   throughput.

3) Allow updates to the instruction sets to be added quickly. Having a
   table means that the information is together, and is easier to
   manipulate. Having the table generate the engine, rather than the
   run-time parse the table gives higher performance at simulation
   time.

4) Keep all the similar simulation code together. i.e. have a single
   place where, for example, the addition code is held. This ensures that
   updates to the simulation are not spread over a large flat source
   file maintained by the developer.

-------------------------------------------------------------------------------

To keep the simulator simple (and to avoid the slight chance of
mis-matched files) the manifests describing an engine, and the
simulator engine itself, are held in the same source file.

This means that the engine must be included twice, with the first pass
controlled by the SIM_MANIFESTS definition.

-------------------------------------------------------------------------------
> EOF README.Cygnus