darkkirb/old-cross-binutils
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37 commits

Author SHA1 Message Date
Andreas Schwab
aaea6334a0 * ppc-instructions: Fix missing assignment in last change. 2010-02-14 10:00:46 +00:00
Andreas Schwab
2ad0ff16f7 * ppc-instructions: Fix aliasing bugs when calling 
invalid_arithemetic_operation.
 2010-02-05 15:47:02 +00:00
Nathan Froyd
7631938e96 * ppc-instructions (sync): Add L field. 2009-01-12 20:04:36 +00:00
Joel Sherrill
e3b96e32ca 2008-12-15 Joel Sherrill <joel.sherrill@oarcorp.com> 
* ppc-instructions, ppc-spr-table: Add ability
	to read tbrl and tbru special registers.
 2008-12-15 19:48:06 +00:00
Andrew Cagney
6a58c676a9 2006-11-22 Tom Marn <tom.marn@telargo.com> 
Committed by Andrew Cagney.
	* ppc-instructions: Implement optional PowerPC stfiwx instruction.
 2006-11-29 15:20:55 +00:00
Andrew Cagney
54273454d0 2004-01-27 Andrew Cagney <cagney@redhat.com> 
* ppc-instructions: Update copyright.
	(convert_to_integer): Add trailing ";" to label.
 2004-01-27 13:21:09 +00:00
Andrew Cagney
345d88d96e 2003-06-22 Andrew Cagney <cagney@redhat.com> 
Written by matthew green <mrg@redhat.com>, with fixes from Aldy
	Hernandez <aldyh@redhat.com>, Jim Wilson <wilson@redhat.com>, and
	Nick Clifton <nickc@redhat.com>.

	* ppc-instructions: Include altivec.igen and e500.igen.
	(model_busy, model_data): Add vr_busy and vscr_busy.
	(model_trace_release): Trace vr_busy and vscr_busy.
	(model_new_cycle): Update vr_busy and vscr_busy.
	(model_make_busy): Update vr_busy and vscr_busy.
	* registers.c (register_description): Add Altivec and e500
	registers.
	* psim.c (psim_read_register, psim_read_register): Handle Altivec
	and e500 registers.
	* ppc-spr-table (SPEFSCR): Add VRSAVE and SPEFSCR registers.
	* configure.in (sim_filter): When *altivec* add "av".  When *spe*
	or *simd* add e500.
	(sim_float): When *altivec* define WITH_ALTIVEC.  When *spe* add
	WITH_E500.
	* configure: Re-generate.
	* e500.igen, altivec.igen: New files.
	* e500_expression.h, altivec_expression.h: New files.
	* idecode_expression.h: Update copyright.  Include
	"e500_expression.h" and "altivec_expression.h".
	* e500_registers.h, altivec_registers.h: New files.
	* registers.h: Update copyright.  Include "e500_registers.h" and
	"altivec_registers.h".
	(registers): Add Altivec and e500 specific registers.
	* Makefile.in (IDECODE_H): Add "idecode_e500.h" and
	"idecode_altivec.h".
	(REGISTERS_H): Add "e500_registers.h" and "altivec_registers.h".
	(tmp-igen): Add dependencies on altivec.igen and e500.igen .
 2003-06-22 16:48:12 +00:00
Andrew Cagney
21f86aab13 2003-06-21 Andrew Cagney <cagney@redhat.com> 
* ppc-instructions: Add missing +8 line.  Found by blofeldus at
	yahoo.com.
 2003-06-22 01:52:34 +00:00
Andrew Cagney
d81bb16ac0 2003-06-19 Andrew Cagney <cagney@redhat.com> 
* ld-insn.h: Update copyright.
	(cache_fields): Define.
	(insn_table_fields): Add insn_field_6 and insn_field_7.
	(load_insn_table): Pass in the "cache_rules".
	* ld-insn.c: Update copyright.
	(load_insn_table): Add parameter "cache_rules".  Handle "cache",
	"computed" and "scratch" fields.
	(main): Pass "cache_rules" to load_insn_table.
	* ld-cache.h: Update copyright.
	(append_cache_table): Declare.
	* ld-cache.c: Update copyright.
	(append_cache_table): New function.
	(load_cache_table): Call.
	* gen-model.c: Include "ld-cache.h".
	* gen-itable.c: Include "ld-cache.h".
	* igen.c: Move #include "ld-cache.h" to earlier.  Update
	copyright.
	(main): Permit a NULL "cache_rules".  Pass address of
	"cache_rules" to load_insn_table.
	* Makefile.in (tmp-ld-insn): Add "ld-cache.o".
	(tmp-igen): Do not include ppc-cache-rules.
	(gen-itable.o, gen-model.o): Add "ld-cache.h".
	* ppc-cache-rules: Delete file.
	* ppc-instructions: Add cache rules.
 2003-06-20 03:59:33 +00:00
Andrew Cagney
ec80ed8088 From 2001-12-09 Julien Ducourthial <jducourt@noos.fr>: 
* ppc-instructions (lswx): Do the register control with the
register count.  Initialize the right register in the loop.
(mtfsfi) : Correct prefix for the instruction.
 2002-03-23 21:18:31 +00:00
Geoffrey Keating
ae02957b46 * ppc-instructions (lfsux): Correct XO field of lfsux instruction. 2000-10-24 16:16:43 +00:00
Geoffrey Keating
9ff590a53b * ppc-instructions (Disabled_Exponent_Underflow): Increment 
the exponent when denormalizing.
 2000-03-25 18:45:41 +00:00
Stan Shebs
7a292a7adf import gdb-19990422 snapshot 1999-04-26 18:34:20 +00:00
Stan Shebs
c906108c21 Initial creation of sourceware repository 1999-04-16 01:35:26 +00:00
Stan Shebs
071ea11e85 Initial creation of sourceware repository 1999-04-16 01:34:07 +00:00
Michael Meissner
5c04f4f7fc January 23rd merge 1997-01-27 21:34:50 +00:00
Michael Meissner
30c87b55ec New simulator changes from Andrew 1996-07-23 15:42:42 +00:00
Michael Meissner
4ffd6ed0f3 Make {add to,subtract from} minus one; Make -t alu work better 1996-01-16 16:21:17 +00:00
Michael Meissner
290ad14a9d Add determining when we do not have enough writeback slots; Do not do model specific handling if not printing out the information 1995-11-28 18:47:07 +00:00
Michael Meissner
3d2f9d7c88 Make WITH_MODEL_ISSUE==0 not core dump 1995-11-25 05:56:28 +00:00
Michael Meissner
f2181eff5f Sort instruction names; Add igen -R option; count # of CRs that mtcrf moved 1995-11-25 01:35:14 +00:00
Michael Meissner
45525d8d6d Fix warnings to everything can be compiled with -Wall; Redo model specific changes once again to speed things up 1995-11-24 16:44:37 +00:00
Michael Meissner
46c065ab31 Count each type of conditional branch 1995-11-22 21:02:49 +00:00
Michael Meissner
4a0351ab45 Add floating point model specific support; Redo method model specific support is done; Add remaining floating add/subtract-multiply 1995-11-21 21:41:25 +00:00
Michael Meissner
0bcce7d390 speed up search for free function unit slightly. 1995-11-20 04:05:36 +00:00
Michael Meissner
15ec5b60e2 Add scheduling support for M{F,T}CR 1995-11-18 01:39:04 +00:00
Michael Meissner
54e986998a More scheduling stuff 1995-11-18 01:14:45 +00:00
Michael Meissner
4220dcd698 checkpoint ppc simulator 1995-11-17 19:17:58 +00:00
Michael Meissner
84bbbc3577 Delete old functional_unit support; Add --enable-sim-model-issue; Monitor branch prediction success 1995-11-16 21:42:27 +00:00
Michael Meissner
867b71685a fix bug in last checkin 1995-11-16 19:25:47 +00:00
Michael Meissner
845ff5a45f more functional unit changes 1995-11-16 19:02:52 +00:00
Michael Meissner
80948f392b More model specific changes 1995-11-15 22:53:59 +00:00
Michael Meissner
eb4ef19775 Add model-functions support 1995-11-13 01:27:21 +00:00
Michael Meissner
28816f45f5 Add support for setting model name and other things 1995-11-12 14:20:39 +00:00
Michael Meissner
73c4941b23 first stage in function unit support; add new switches & latest code from andrew 1995-11-08 18:57:06 +00:00
Michael Meissner
056e975cfe Add 2 config flags that were missing; make data cache instructions be nops 1995-11-03 19:37:28 +00:00
Michael Meissner
c143ef6296 Lots of changes 1995-11-01 19:32:38 +00:00