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2006-11-22 Tom Marn <tom.marn@telargo.com>

Browse source 
Committed by Andrew Cagney.
	* ppc-instructions: Implement optional PowerPC stfiwx instruction.
This commit is contained in:
Andrew Cagney 2006-11-29 15:20:55 +00:00
parent 64d756327a
commit 6a58c676a9
2 changed files with 17 additions and 7 deletions
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5
sim/ppc/ChangeLog
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@ -1,3 +1,8 @@
2006-11-22 Tom Marn <tom.marn@telargo.com>
Committed by Andrew Cagney.
* ppc-instructions: Implement optional PowerPC stfiwx instruction.
2006-07-12 Fred Fish <fnf@specifix.com>
* sim-endian.h (asm/byteorder.h): Don't include private kernel

19
sim/ppc/ppc-instructions
View file

@ -3644,6 +3644,18 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
STORE(EA, 8, *frS);
PPC_INSN_INT_FLOAT(0, 0, (RA_BITMASK & ~1) | RB_BITMASK, FRS_BITMASK);
0.31,6.FRS,11.RA,16.RB,21.983,31./:X:f::Store Floating-Point Integer Word Indexed
*603: PPC_UNIT_LSU, PPC_UNIT_LSU, 1, 2, 0
*603e:PPC_UNIT_LSU, PPC_UNIT_LSU, 1, 2, 0
*604: PPC_UNIT_LSU, PPC_UNIT_LSU, 1, 3, 0
unsigned_word b;
unsigned_word EA;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
STORE(EA, 4, *frS);
PPC_INSN_INT_FLOAT(0, 0, (RA_BITMASK & ~1) | RB_BITMASK, FRS_BITMASK);
0.55,6.FRS,11.RA,16.D:D:f::Store Floating-Point Double with Update
*601: PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*603: PPC_UNIT_LSU, PPC_UNIT_LSU, 1, 2, 0
@ -4682,13 +4694,6 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
FPSCR |= bit;
FPSCR_END(Rc);
#
# I.A.1.1 Floating-Point Store Instruction
#
0.31,6.FRS,11.RA,16.RB,21.983,31./:X:f,o::Store Floating-Point as Integer Word Indexed
program_interrupt(processor, cia, optional_instruction_program_interrupt);
#
# I.A.1.2 Floating-Point Arithmetic Instructions
#