explicitly. Clean up some regexps.
* gas/mips/ld-ilocks.d: Likewise. Add missing "$" prefixes to
the names of FP registers.
* gas/mips/ld-ilocks-addr32.d: Likewise.
* gas/mips/ld.s: Align sections to 4k, adjust padding.
* mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
macros before their corresponding MIPS III hardware instructions.
gas/
* config/tc-mips.c (macro)[M_LD_OB, M_SD_OB]: Handle 64-bit ABIs.
gas/testsuite/
* gas/mips/lineno.s: Convert to o32.
* gas/mips/lineno.d: Adjust patterns accordingly. Force the o32
ABI.
Make sure all illegal insns get assembled & decoded correctly.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The BYTEOP2M parser incorrectly calls BYTEOP2P to generate the opcode.
Once we've fixed that, it's easy to see that the disassembler also likes
to decode this insn incorrectly. So fix that and then add some tests.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The exact symbol addresses are not important to these tests. We only
care about the opcodes and the disassembly output. This makes adding
more insns to these tests easier.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
gas/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (_i386_insn): Add disp32_encoding.
(md_assemble): Don't call optimize_disp if disp32_encoding is
set.
(parse_insn): Support .d32 to force 32bit displacement.
(output_branch): Use BIG if disp32_encoding is set.
* doc/c-i386.texi: Document .d32 encoding suffix.
gas/testsuite/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/disp32.d: New.
* gas/i386/disp32.s: Likewise.
* gas/i386/x86-64-disp32.d: Likewise.
* gas/i386/x86-64-disp32.s: Likewise.
* gas/i386/i386.exp: Run disp32 and x86-64-disp32.
* s390-opc.c: Make the instruction masks for the load/store on
condition instructions to cover the condition code mask as well.
* s390-opc.txt: lgoc -> locg and stgoc -> stocg.
2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/zarch-z196.d: Adjust the load/store on condition
instructions.
* gas/s390/zarch-z196.s: Likewise.
* config/tc-tic6x.c (tic6x_try_encode): Correct encoding of fstg field
in SPKERNEL instructions.
opcodes/
* tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
in SPKERNEL instructions.
gas/testsuite/
* gas/tic6x/insns-c674x-sploop.d: Add two more sploop/spkernel tests.
* gas/tic6x/insns-c674x-sploop.s: Likewise.
* config/tc-mips.c (mips_fix_cn63xxp1): New variable.
(mips_ip): Add errata work around when mips_fix_cn63xxp1 set.
(OPTION_FIX_CN63XXP1, OPTION_NO_FIX_CN63XXP1): New enum options
enumerations.
(md_longopts): Add options for -mfix-cn63xxp1 and -mno-fix-cn63xxp1.
(md_parse_option): Handle OPTION_FIX_CN63XXP1 and
OPTION_NO_FIX_CN63XXP1.
(md_show_usage): Add documentation for -mfix-cn63xxp1.
* doc/c-mips.texi (-mfix-cn63xxp1, -mno-fix-cn63xxp1): Document
the new options.
2010-10-04 David Daney <ddaney@caviumnetworks.com>
* gas/mips/mips.exp (octeon-pref): Run the new test.
* gas/mips/octeon-pref.s: New test.
* gas/mips/octeon-pref.d: New expected results for the new test.
* gas/config/tc-arm.c (arm_ext_virt): New variable.
(arm_reg_type): Add REG_TYPE_RNB for banked registers.
(reg_entry): Allow registers to be larger than a byte.
(reg_alias): Fix type warning.
(parse_operands): Parse banked registers when appropriate.
(do_mrs): Add support for Virtualization Extensions.
(do_hvc): New function.
(do_t_mrs): Add support for Virtualization Extensions.
(do_t_msr): Likewise.
(do_t_hvc): New function.
(SPLRBANK): New define.
(reg_names): Add banked registers.
(insns): Add support for Virtualization Extensions.
(md_apply_fixup): Likewise.
(arm_cpus): -mcpu=cortex-a15 implies the Virtualization Extensions.
(arm_extensions): Add 'virt' extension.
(aeabi_set_public_attributes): Add support for Virtualization
Extensions.
* gas/doc/c-arm.texi: Document 'virt' extension.
* gas/testsuite/gas/arm/armv7-a+virt.d: New test.
* gas/testsuite/gas/arm/armv7-a+virt.s: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for Virtualization Extensions.
* gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d: New test.
* gas/testsuite/gas/arm/attr-march-armv7-a+virt.d: Likewise.
* include/opcode/arm.h (ARM_EXT_VIRT): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
(ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
Extensions.
* opcodes/arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
(thumb32_opcodes): Likewise.
(banked_regname): New function.
(print_insn_arm): Add Virtualization Extensions support.
(print_insn_thumb32): Likewise.
(do_div): New function.
(insns): Accept UDIV and SDIV in ARM state.
(arm_cpus): The cortex-a15 option has all current v7-A extensions.
(arm_extensions): Add 'idiv' extension.
(aeabi_set_public_attributes): Update Tag_DIV_use values for the
Integer Divide extension.
* gas/doc/c-arm.texi: Document the idiv extension.
* gas/testsuite/gas/arm/armv7-a+idiv.d: New test.
* gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension.
* gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test.
* include/opcode/arm.h (ARM_AEXT_ADIV): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
* opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
ARM state.
(arm_ext_m): Add support for OS extension.
(arm_ext_os): New variable.
(do_t_swi): In v6-M ensure we have the OS extension.
(arm_cpus): The cortex-m1 and cortex-m0 options have the OS
extension by default.
(arm_archs): Add armv6s-m.
(arm_extensions): Add 'os' extension.
(cpu_arch_ver): Add support for v6S-M.
* gas/doc/c-arm.texi: Document the OS Extension, and v6-m and v6s-m
architecture options.
* gas/testsuite/gas/arm/archv6s-m-bad.d: New test.
* gas/testsuite/gas/arm/archv6s-m-bad.l: Likewise.
* gas/testsuite/gas/arm/archv6s-m.d: Likewise.
* gas/testsuite/gas/arm/archv6s-m.s: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6-m+os.d: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6s-m.d: Likewise.
* include/opcode/arm.h (ARM_EXT_OS): New define.
(ARM_AEXT_V6SM): Likewise.
(ARM_ARCH_V6SM): Likewise.
Using "Register mismatch" everywhere can be a bit vague, so clarify
why exactly we're barfing on these unsupported insns.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some extended registers when given to the DBG/DBGCMPLX pseudo insns are
not encoded properly. So fix them, fix the display of them when being
disassembled, and add testcases.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT,
ASHIFT, or BXORSHIFT. So be specific when disassembling.
As fall out of this change, we need to update some assembler tests.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas/testsuite/gas/arm/attr-cpu-directive.d: Update test for change in canonical
CPU name.
* gas/testsuite/gas/arm/attr-mcpu.d: Likewise.
* ld/testsuite/ld-arm/attr-merge-6.attr: Update tests for change in canonical
CPU name.
* ld/testsuite/ld-arm/attr-merge-7.attr: Likewise.
* ld/testsuite/ld-arm/attr-merge-2.attr: Likewise.
* ld/testsuite/ld-arm/attr-merge-arch-2.attr: Likewise.
* config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead
of just RR.
2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
* gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand.
* gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv. Also
add disassembly for test added in copro.s
2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
* arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
* mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
gas/testsuite/
* gas/mips/mips32r2-sync.d: New test for MIPS32r2 "sync"
instruction variants.
* gas/mips/octeon@mips32r2-sync.d: Likewise, Octeon version.
* gas/mips/mips32r2-sync.s: Source for the new test.
* gas/mips/mips.exp: Run the new test.
