opcodes/
* mips-opc.c (mips_builtin_opcodes): Add "sync_acquire", "sync_mb", "sync_release", "sync_rmb" and "sync_wmb". gas/testsuite/ * gas/mips/mips32r2-sync.d: New test for MIPS32r2 "sync" instruction variants. * gas/mips/octeon@mips32r2-sync.d: Likewise, Octeon version. * gas/mips/mips32r2-sync.s: Source for the new test. * gas/mips/mips.exp: Run the new test.
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7 changed files with 104 additions and 0 deletions
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@ -1,3 +1,11 @@
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2010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
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* gas/mips/mips32r2-sync.d: New test for MIPS32r2 "sync"
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instruction variants.
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* gas/mips/octeon@mips32r2-sync.d: Likewise, Octeon version.
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* gas/mips/mips32r2-sync.s: Source for the new test.
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* gas/mips/mips.exp: Run the new test.
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2010-09-13 Kai Tietz <kai.tietz@onevision.com>
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* gas/pe/pe.exp: Add x64 SEH tests.
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@ -877,6 +877,8 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test "mips16-vis-1"
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run_dump_test "call-nonpic-1"
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run_dump_test "mips32-sync"
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run_dump_test_arches "mips32r2-sync" \
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[mips_arch_list_matching mips32r2]
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if $has_newabi { run_dump_test "cfi-n64-1" }
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29
gas/testsuite/gas/mips/mips32r2-sync.d
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29
gas/testsuite/gas/mips/mips32r2-sync.d
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@ -0,0 +1,29 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: MIPS32r2 sync instructions
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#as: -32
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#source: mips32r2-sync.s
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# Check MIPS32r2 sync instructions assembly and disassembly
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.*: +file format .*mips.*
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Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> 0000000f sync
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[0-9a-f]+ <[^>]*> 0000008f sync 0x2
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[0-9a-f]+ <[^>]*> 0000010f sync_wmb
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[0-9a-f]+ <[^>]*> 0000020f sync 0x8
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[0-9a-f]+ <[^>]*> 0000040f sync_mb
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[0-9a-f]+ <[^>]*> 0000044f sync_acquire
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[0-9a-f]+ <[^>]*> 0000048f sync_release
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[0-9a-f]+ <[^>]*> 000004cf sync_rmb
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[0-9a-f]+ <[^>]*> 0000060f sync 0x18
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[0-9a-f]+ <[^>]*> 0000000f sync
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[0-9a-f]+ <[^>]*> 0000008f sync 0x2
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[0-9a-f]+ <[^>]*> 0000010f sync_wmb
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[0-9a-f]+ <[^>]*> 0000020f sync 0x8
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[0-9a-f]+ <[^>]*> 0000040f sync_mb
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[0-9a-f]+ <[^>]*> 0000044f sync_acquire
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[0-9a-f]+ <[^>]*> 0000048f sync_release
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[0-9a-f]+ <[^>]*> 000004cf sync_rmb
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[0-9a-f]+ <[^>]*> 0000060f sync 0x18
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\.\.\.
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26
gas/testsuite/gas/mips/mips32r2-sync.s
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26
gas/testsuite/gas/mips/mips32r2-sync.s
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# Source file to test assembly of MIPS32r2 sync instructions.
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.text
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foo:
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sync
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sync 2
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sync_wmb
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sync 8
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sync_mb
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sync_acquire
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sync_release
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sync_rmb
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sync 0x18
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sync 0
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sync 2
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sync 4
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sync 8
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sync 0x10
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sync 0x11
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sync 0x12
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sync 0x13
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sync 0x18
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.align 2
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.space 8
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29
gas/testsuite/gas/mips/octeon@mips32r2-sync.d
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29
gas/testsuite/gas/mips/octeon@mips32r2-sync.d
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: MIPS32r2 sync instructions
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#as: -32
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#source: mips32r2-sync.s
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# Check MIPS32r2 sync instructions assembly and disassembly (Octeon).
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.*: +file format .*mips.*
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Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> 0000000f sync
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[0-9a-f]+ <[^>]*> 0000008f synciobdma
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[0-9a-f]+ <[^>]*> 0000010f syncw
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[0-9a-f]+ <[^>]*> 0000020f sync 0x8
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[0-9a-f]+ <[^>]*> 0000040f sync_mb
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[0-9a-f]+ <[^>]*> 0000044f sync_acquire
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[0-9a-f]+ <[^>]*> 0000048f sync_release
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[0-9a-f]+ <[^>]*> 000004cf sync_rmb
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[0-9a-f]+ <[^>]*> 0000060f sync 0x18
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[0-9a-f]+ <[^>]*> 0000000f sync
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[0-9a-f]+ <[^>]*> 0000008f synciobdma
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[0-9a-f]+ <[^>]*> 0000010f syncw
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[0-9a-f]+ <[^>]*> 0000020f sync 0x8
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[0-9a-f]+ <[^>]*> 0000040f sync_mb
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[0-9a-f]+ <[^>]*> 0000044f sync_acquire
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[0-9a-f]+ <[^>]*> 0000048f sync_release
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[0-9a-f]+ <[^>]*> 000004cf sync_rmb
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[0-9a-f]+ <[^>]*> 0000060f sync 0x18
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\.\.\.
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@ -1,3 +1,8 @@
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2010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
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* mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
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"sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
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2010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
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* src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
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@ -1335,6 +1335,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"syncs", "", 0x0000018f, 0xffffffff, INSN_SYNC, 0, IOCT },
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{"syncw", "", 0x0000010f, 0xffffffff, INSN_SYNC, 0, IOCT },
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{"syncws", "", 0x0000014f, 0xffffffff, INSN_SYNC, 0, IOCT },
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{"sync_acquire", "", 0x0000044f, 0xffffffff, INSN_SYNC, 0, I33 },
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{"sync_mb", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I33 },
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{"sync_release", "", 0x0000048f, 0xffffffff, INSN_SYNC, 0, I33 },
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{"sync_rmb", "", 0x000004cf, 0xffffffff, INSN_SYNC, 0, I33 },
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{"sync_wmb", "", 0x0000010f, 0xffffffff, INSN_SYNC, 0, I33 },
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{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 },
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{"sync", "1", 0x0000000f, 0xfffff83f, INSN_SYNC, 0, I32 },
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{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 },
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