entries are presorted so that entries with the same mnemonic are
adjacent to each other in the table. Sort the entries for each
instruction so that this is true.
Start mn10200 gdb port by adding copies of mn10300
target-specific files with all instances of mn10300 changed
to mn10200 to start with.
* mn10200-tdep.c: new
* config/mn10200/tm-mn10200.h: new, REGISTER_SIZE is 24 bits not 32,
SP_REGNUM and FP_REGNUM are different, also no lar or lir.
* config/mn10200/mn10200.mt: new
* configure.tgt: add mn10200 entry
Start mn10200 gdb port by adding copies of mn10300
target-specific files with all instances of mn10300 changed
to mn10200 to start with.
* mn10200-tdep.c: new
* config/mn10200/tm-mn10200.h: new, REGISTER_SIZE is 24 bits not 32,
SP_REGNUM and FP_REGNUM are different, also no lar or lir.
* config/mn10200/mn10200.mt: new
* mn10300-tdep.c: wrote/fixed implementations of
mn10300_frame_chain, mn10300_init_extra_frame_info,
mn10300_frame_saved_pc
* config/mn10300/tm-mn10300.h: redefine INIT_EXTRA_FRAME_INFO
and INIT_FRAME_PC macros
Backtracing starting to work correctly.
function up into several smaller ones and arranged for
the instruction printing function to be callable recursively
to print vector instructions that have both a load and a
math instruction packed into a single opcode.
* tic80-opc.c (tic80_opcodes): Expand comment for vld opcode
to explain why it comes after the other vector opcodes.
* m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
move insns to handle immediate operands.
From Andreas Schwab:
* m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil".
New macros for building vector instruction opcodes.
(tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and
FMT_LI, which were unused. The field is now a flags field.
Remove some opcodes that are possible, but illegal, such
as long immediate instructions with doubles for immediate
values. Add "vadd" and "vld" instructions.
(FMT_UNUSED, FMT_SI, FMT_LI, FMT_REG): Delete.
(TIC80_VECTOR): Define a flag bit for the flags. This one means
that the opcode can have two vector instructions in a single
32 bit word and we have to encode/decode both.
auxiliary_filters, and make it char **.
* lexsup.c (parse_args): Handle -f by setting up an array.
* emultempl/elf32.em (gld${EMULATION_NAME}_before_allocation): Use
new name of auxiliary_filters.
the order more logical. Move the shift alias instructions ("rotl",
"shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be
interspersed with the regular sr.x and sl.x instructions. Add
and test new instruction opcodes for "sl", "sli", "sr", "sri", "st",
"sub", "subu", "swcr", and "trap".
* mn10300-tdep.c: made a lot more generic, ripping out code
from copied target (no more mn10300_scan_prologue,
init_extra_frame_info, and mn10300_fix_call_dummy calls)
* config/mn10300/tm-mn10300.h: undefine INIT_EXTRA_FRAME_INFO
and INIT_FRAME_PC macros
