Commit graph

13 commits

Author SHA1 Message Date
Andrew Cagney
a276b6f057 Clean up tracing for Bcond & jmp insns.
Fix computation of disp16 and disp22.
Clean up tracing of sld* insns.
1997-09-19 06:39:21 +00:00
Andrew Cagney
bd4c35cc6d Fix cmov immed. 1997-09-19 02:20:02 +00:00
Andrew Cagney
60fe0e06a8 Fix cmov insn. 1997-09-19 00:50:19 +00:00
Andrew Cagney
a72f8fb439 Clean up more tracing.
FIX interrupt delivery - was zapping PSW before it had been saved.
FIX interrupt return, was one instruction out.
1997-09-17 08:14:23 +00:00
Andrew Cagney
6aead89a5f Fix tracing for: "ctret", "bsw", "hsw"
Fix bugs in: "bsh", "callt", "stsr".
1997-09-17 05:31:00 +00:00
Andrew Cagney
fb1fd47514 Smooth some of ALU tracing's rough edges.
Fix switch insn.
1997-09-16 14:00:15 +00:00
Andrew Cagney
c7db488f71 Restrict ldsr (load system register) to modifying just non-reserved PSW bits.
For v850eq, include PSW[US] in bits that can be modified.
1997-09-16 04:49:24 +00:00
Andrew Cagney
721478d51b Add v850e version of breakpoint instruction. 1997-09-16 02:15:55 +00:00
Andrew Cagney
4dda50b052 For instructions moved into v850.igen was computing (wrong) NIA when
this wasn't needed.
1997-09-15 23:09:26 +00:00
Andrew Cagney
bda6163995 Fix sanitization for v850 V v850e V v850eq 1997-09-15 14:42:51 +00:00
Andrew Cagney
658303f7d4 For v850eq start up with US bit set.
Let sim_analyze_program determine the architecture.
Fix various sanitizations.
1997-09-15 08:18:20 +00:00
Andrew Cagney
410230cf6d Check reserved bits before executing instructions.
Make v850[eq] the the default simulator.
Report illegal instructions.
Include v850e instructions in v850eq.
1997-09-12 05:56:38 +00:00
Andrew Cagney
5d37a07bc5 Add multi-sim support to v850/v850e/v850eq simulators. 1997-09-08 17:42:48 +00:00