Andrew Cagney
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a276b6f057
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Clean up tracing for Bcond & jmp insns.
Fix computation of disp16 and disp22.
Clean up tracing of sld* insns.
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1997-09-19 06:39:21 +00:00 |
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Andrew Cagney
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bd4c35cc6d
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Fix cmov immed.
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1997-09-19 02:20:02 +00:00 |
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Andrew Cagney
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60fe0e06a8
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Fix cmov insn.
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1997-09-19 00:50:19 +00:00 |
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Andrew Cagney
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a72f8fb439
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Clean up more tracing.
FIX interrupt delivery - was zapping PSW before it had been saved.
FIX interrupt return, was one instruction out.
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1997-09-17 08:14:23 +00:00 |
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Andrew Cagney
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6aead89a5f
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Fix tracing for: "ctret", "bsw", "hsw"
Fix bugs in: "bsh", "callt", "stsr".
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1997-09-17 05:31:00 +00:00 |
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Andrew Cagney
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fb1fd47514
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Smooth some of ALU tracing's rough edges.
Fix switch insn.
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1997-09-16 14:00:15 +00:00 |
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Andrew Cagney
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c7db488f71
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Restrict ldsr (load system register) to modifying just non-reserved PSW bits.
For v850eq, include PSW[US] in bits that can be modified.
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1997-09-16 04:49:24 +00:00 |
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Andrew Cagney
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721478d51b
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Add v850e version of breakpoint instruction.
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1997-09-16 02:15:55 +00:00 |
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Andrew Cagney
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4dda50b052
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For instructions moved into v850.igen was computing (wrong) NIA when
this wasn't needed.
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1997-09-15 23:09:26 +00:00 |
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Andrew Cagney
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bda6163995
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Fix sanitization for v850 V v850e V v850eq
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1997-09-15 14:42:51 +00:00 |
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Andrew Cagney
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658303f7d4
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For v850eq start up with US bit set.
Let sim_analyze_program determine the architecture.
Fix various sanitizations.
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1997-09-15 08:18:20 +00:00 |
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Andrew Cagney
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410230cf6d
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Check reserved bits before executing instructions.
Make v850[eq] the the default simulator.
Report illegal instructions.
Include v850e instructions in v850eq.
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1997-09-12 05:56:38 +00:00 |
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Andrew Cagney
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5d37a07bc5
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Add multi-sim support to v850/v850e/v850eq simulators.
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1997-09-08 17:42:48 +00:00 |
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