2005-02-02 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (dot_pred_rel): Update comment. Handle @-prefixed
designators along with quoted ones. Free copy of quoted designator
when done.
gas/testsuite/
2005-02-02 Jan Beulich <jbeulich@novell.com>
* gas/ia64/pred-rel.s: New.
* gas/ia64/ia64.exp: Run new test.
2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (parse_operands): Parse all specified operands,
immediately discarding (but counting) those exceeding the maximum
possible amount. Track whether output and input operand counts ever
matched, and use this to better indicate which of the operands/
operand types was wrong; specifically don't default to pointing to
the first operand.
gas/testsuite/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/operands.[ls]: New.
* gas/ia64/ia64.exp: Run new test.
2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (unwind): Remove proc_end (now an automatic
variable in dot_endp). Add body and insn. Make prologue,
prologue_mask, body, and insn bitfields.
(fixup_unw_records): Remove spurious new-lines from end of diagnostic
messages.
(in_procedure, in_prologue, in_body): New.
(dot_fframe, dot_vframe, dot_vframesp, dot_vframepsp, dot_save,
dot_restore, dot_restorereg, dot_restorereg_p, dot_handlerdata,
dot_unwentry, dot_altrp, dot_savemem, dot_saveg, dot_savef, dot_saveb,
dot_savegf, dot_spill, dot_spillreg, dot_spillmem, dot_spillreg_p,
dot_spillmem_p, dot_label_state, dot_copy_state, dot_unwabi,
dot_personality): Use the appropriate one of the above.
(dot_proc): Clear unwind.proc_start; set to current location only if
none of the entry points were valid. Check for non-zero-length entry
point names. Check that entry points aren't defined, yet. Clear
unwind.prologue, unwind.body, and unwind.insn.
(dot_body): Call in_procedure. Check that first directive in procedure
had no insns emitted before. Set unwind.body.
(dot_prologue): Call in_procedure. Check that not already in prologue.
Check that first directive in procedure had no insns emitted before.
Clear unwind.body.
(dot_endp): Call in_procedure. Declare proc_end. Check for non-zero-
length entry point names. Check that entry points became defined.
(md_assemble): Set unwind.insn once unwind.proc_start is defined.
gas/testsuite/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/proc.[ls]: New.
* gas/ia64/unwind-err.[ls]: New.
* gas/ia64/ia64.exp: Run new tests.
2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (emit_one_bundle): Snapshot manual bundling state
before actually using it. Don't generate an error in manual bundling
mode when looking at an insn requiring slot 2 but not yet at slot 2.
Don't generate an error in manual bundling mode when looking at an
insn required to be last in its group but the required slot hasn't
been reached, yet. Allow conversion from MII to MI;I for bundle
consisting of only 2 insns with the stop between them. Suppress
various meaningless errors resulting from detecting earlier ones.
gas/testsuite/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/bundling.[ds]: New.
* gas/ia64/label.[ls]: New.
* gas/ia64/last.[ls]: New.
* gas/ia64/slot2.[ls]: New.
* gas/ia64/ia64.exp: Run new tests.
2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (parse_operands): Also handle alloc without first
input being ar.pfs.
gas/testsuite/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/pseudo.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
opcodes/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* ia64-gen.c (NELEMS): Define.
(shrink): Generate alias with missing second predicate register when
opcode has two outputs and these are both predicates.
* ia64-opc-i.c (FULL17): Define.
(ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
here to generate output template.
(TBITCM, TNATCM): Undefine after use.
* ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
first input. Add ld16 aliases without ar.csd as second output. Add
st16 aliases without ar.csd as second input. Add cmpxchg aliases
without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
ar.ccv as third/fourth inputs. Consolidate through...
(CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
* ia64-asmtab.c: Regenerate.
2005-01-28 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (ia64_estimate_size_before_relax): Allocate space
for personality routine pointer only if there is one.
(ia64_convert_frag): Likewise.
(generate_unwind_image): Likewise.
ld/testsuite/
2005-01-28 Jan Beulich <jbeulich@novell.com>
* ld/ia64/tlsbin.[rt]d: Widen expected offset/size ranges.
* ld/ia64/tlspic.[rt]d: Likewise.
(md_apply_fix3): Make relative branches out of range an error
instead of a warning. Display correct line number for out of
range branches/calls/memory accesses.
2005-01-27 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (emit_one_bundle): Change "?imbf??" to "?ibmfxx".
gas/testsuite/
2005-01-27 Jan Beulich <jbeulich@novell.com>
* gas/ia64/nop_x.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
2005-01-25 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (emit_one_bundle): Add late resolution of move
to/from application registers dynamic insns.
(md_assemble): Defer resolution of move to/from application registers
dynamic insns when they can be issued on either the I- or M-units.
gas/testsuite/
2005-01-25 Jan Beulich <jbeulich@novell.com>
* gas/ia64/dv-waw-err.l: Don't expect ar112 move warning to refer to
M-unit.
* gas/ia64/mov-ar.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
* config/tc-ia64.c (md): Add member "loc_directive_seen".
(dot_loc): New function.
(md_pseudo_table): Add entry to map .loc to dot_loc().
(emit_one_bundle): Only call dwarf2_gen_line_info() if we have
seen a .loc directive or we're generating DWARF2 debug info for
assembly source.
* v850.h (R_V850_LO16_SPLIT_OFFSET): New reloc.
bfd/
* reloc.c (BFD_RELOC_V850_LO16_SPLIT_OFFSET): New bfd_reloc_code_type.
* elf32-v850.c (v850_elf_howto_table): Add entry for
R_V850_LO16_SPLIT_OFFSET.
(v850_elf_reloc_map): Map it to BFD_RELOC_V850_LO16_SPLIT_OFFSET.
(v850_elf_perform_lo16_relocation): New function, extracted from...
(v850_elf_perform_relocation): ...here. Use it to handle
R_V850_LO16_SPLIT_OFFSET.
(v850_elf_check_relocs, v850_elf_final_link_relocate): Handle
R_V850_LO16_SPLIT_OFFSET.
* libbfd.h, bfd-in2.h: Regenerate.
gas/
* config/tc-v850.c (handle_lo16): New function.
(v850_reloc_prefix): Use it to check lo().
(md_assemble, md_apply_fix3): Handle BFD_RELOC_V850_LO16_SPLIT_OFFSET.
gas/testsuite/
* gas/v850/split-lo16.{s,d}: New test.
* gas/v850/v850.exp: Run it.
ld/testsuite/
* ld-v850: New directory.
2004-12-15 Jan Beulich <jbeulich@novell.com>
* config/obj-elf.c (obj_elf_change_section): Only set type and
attributes on new sections. Emit warning when type of re-declared
section doesn't match.
gas/testsuite/
2004-12-15 Jan Beulich <jbeulich@novell.com>
* gas/elf/section5.[els]: New.
* configure.in: Use it for arm*-*-linux-gnueabi*.
* config/tc-arm.c: Allow emulation file to set FPU_DEFAULT.
* config/te-armlinuxeabi.h: New file.
* Makefile.in: Regenerated.
* aclocal.m4: Likewise.
* configure: Likewise.
* doc/Makefile.in: Regenerated.
2004-11-25 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (optimize_imm): Adjust immediates to only those
permissible for the selected instruction suffix.
(process_suffix): For DefaultSize instructions, suppressing the
guessing of a 'q' suffix if the instruction doesn't support it is
pointless, because only an 'l' suffix can be guessed in this place.
gas/testsuite/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-inval.[sl]: Remove sahf/lahf.
include/opcode/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
to/from test registers are illegal in 64-bit mode. Add missing
NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
(previously one had to explicitly encode a rex64 prefix). Re-enable
lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
They should be correct now.
* gas/mn10300/relax.s: Add further tests of the relaxing of branch instructions.
* gas/mn10300/relax.d: Add expected relocations.
2004-11-23 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to
indicate the MMX extensions added by both SSE and 3DNow!A.
(Cpu3dnowA): Declare.
(CpuUnknownFlags): Update.
* config/tc-i386.c (cpu_sub_arch_name): Declare.
(cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do
neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies
3DNow!. Athlon additionally implies 3DNow!A. Several new
entries (those starting with a dot are for sub-arch specification).
(set_cpu_arch): Handle sub-arch specifications.
(parse_insn): Distinguish between instructions not supported because
of insufficient CPU features and because of 64-bit mode.
* doc/c-i386.texi: Describe enhanced .arch directive.
include/opcode/
2004-11-23 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
available only with SSE2. Change the MMX additions introduced by SSE
and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
instructions by their now designated identifier (since combining i686
and 3DNow! does not really imply 3DNow!A).
include/ChangeLog
* xtensa-isa-internal.h (xtensa_interface_internal): Add class_id.
* xtensa-isa.h (xtensa_interface_class_id): New prototype.
bfd/ChangeLog
* xtensa-isa.c (xtensa_interface_class_id): New.
gas/ChangeLog
* config/tc-xtensa.c (finish_vinsn): Clear pending instruction if
there is a conflict.
(check_t1_t2_reads_and_writes): Check for both reads and writes to
interfaces that are related as determined by xtensa_interface_class_id.
* config/tc-xtensa.c (MAX_IMMED6): Change value to 65.
gas/testsuite/
* gas/xtensa/short_branch_offset.s: New.
* gas/xtensa/short_branch_offset.d: New.
* gas/xtensa/all.exp: Run new test.
* config/tc-crx.c: Rename argument types.
(processing_arg_number): Rename to 'cur_arg_num'.
(get_number_of_bits): Rename to 'set_operand_size'.
(get_operandtype): Rename to 'parse_operand', totally rewrite.
(set_cons_rparams): Rename to 'set_operand', totally rewrite.
(set_indexmode_parameters): Remove function, integrate its code into 'set_operand'.
(set_operand_size): Get rid of 'Operand Number' function parameter - use global variable 'cur_arg_num' instead.
Use a local 'argument' pointer to reference the current argument.
(parse_operand): Likewise.
(set_operand): Likewise.
(process_label_constant): Likewise.
DEFAULT_CRIS_ARCH. Handle crisv32-*-linux-gnu* like
cris-*-linux-gnu* and crisv32-*-* like cris-*-*.
* configure: Regenerate.
* config/tc-cris.c (enum cris_archs): New.
(cris_mach, cris_arch_from_string, s_cris_arch, get_sup_reg)
(cris_insn_ver_valid_for_arch): New functions.
(DEFAULT_CRIS_ARCH): New macro, default to cris_any_v0_v10.
(cris_arch): New variable.
(md_pseudo_table): New pseudo .arch.
(err_for_dangerous_mul_placement): Initialize according to
DEFAULT_CRIS_ARCH.
(STATE_COND_BRANCH): Renamed from STATE_CONDITIONAL_BRANCH.
All users changed.
(STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON)
(STATE_ABS_BRANCH_V32, STATE_LAPC, BRANCH_BF_V32, BRANCH_BB_V32)
(BRANCH_WF_V32, BRANCH_WB_V32): New.
(BRANCH_BF, BRANCH_BB, BRANCH_WF, BRANCH_WB): Don't undef after
use in md_cris_relax_table.
(md_cris_relax_table): Add entries for STATE_COND_BRANCH_V32,
STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
Update and improve head comment.
(OPTION_PIC): Define in terms of previous option, OPTION_US.
(OPTION_MULBUG_ABORT_ON, OPTION_MULBUG_ABORT_OFF): Similar.
(OPTION_ARCH): New.
(md_longopts): New option --march=...
(cris_any_v0_v10_long_jump_size, crisv32_long_jump_size): New
macros.
(md_long_jump_size): Initialize in terms of DEFAULT_CRIS_ARCH.
(HANDLE_RELAXABLE): New macro.
(md_estimate_size_before_relax): Use HANDLE_RELAXABLE for common
cases. Check for weak symbols and assume not relaxable. Handle
STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON,
STATE_ABS_BRANCH_V32, STATE_LAPC. Use new variable symbolP, not
fragP->fr_symbol.
(md_convert_frag): Handle STATE_COND_BRANCH_V32,
STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
(cris_create_short_jump): Adjust for CRISv32.
(md_create_long_jump): Ditto. Emit error for common_v10_v32.
(md_begin): Define symbols "..asm.arch.cris.v32",
"..asm.arch.cris.v10", "..asm.arch.cris.common_v10_v32" and
"..asm.arch.cris.any_v0_v10". Use cris_insn_ver_valid_for_arch
when entering opcode table entry points.
(md_assemble): Adjust branch handling for CRISv32. Handle LAPC
relaxation. In fix_new_exp call for main insn, pass 1 for pcrel
parameter for 8, 16 and 32-bit pc-relative insns and LAPC.
(cris_process_instruction): Initialize out_insnp->insn_type to
CRIS_INSN_NONE, not CRIS_INSN_NORMAL.
<case ']', '[', 'A', 'd', 'Q', 'N', 'n', 'Y', 'U', 'u', 'T'>: New
cases.
<case 'm'>: Check that modified_char == '.'.
<invalid operands>: Consume the rest of the line.
When operands don't match, skip over subsequent insns with
non-matching version specifier but same mnemonic.
<immediate constant, case SIZE_SPEC_REG>: Immediate operands for
special registers in CRISv32 are always 32 bit long.
<immediate constant, case SIZE_FIELD_SIGNED, SIZE_FIELD_UNSIGNED>:
New cases.
(get_gen_reg): Only recognize "PC" when followed by "+]" for v32
and compatible. Recognize "ACR" for v32, unless followed by "+".
(get_spec_reg): Consider cris_arch when looking up register.
(get_autoinc_prefix_or_indir_op): Don't recognize assignment for
v32 or compatible.
(get_3op_or_dip_prefix_op): Check for ']' after seeing '[rN+'.
(cris_get_expression): Restore input_line_pointer if failing "early".
(get_flags): Consider cris_arch and recognize flags accordingly.
(branch_disp): Adjust for CRISv32.
(gen_cond_branch_32): Similar. Emit error for common_v10_v32.
(cris_number_to_imm): Use as_bad_where, not as_bad. Remove
related FIXME. Don't insist on BFD_RELOC_32_PCREL fixup to be
resolved. Don't enter zeros in object file for
BFD_RELOC_32_PCREL.
<case BFD_RELOC_CRIS_LAPCQ_OFFSET, BFD_RELOC_CRIS_SIGNED_16>
<case BFD_RELOC_CRIS_SIGNED_8>: New case.
(md_parse_option): Break out "return 1".
<OPTION_ARCH> New case.
(tc_gen_reloc): <case BFD_RELOC_CRIS_LAPCQ_OFFSET>
<case BFD_RELOC_CRIS_SIGNED_16, BFD_RELOC_CRIS_SIGNED_8>
<case BFD_RELOC_CRIS_UNSIGNED_8, BFD_RELOC_CRIS_UNSIGNED_16>
<case BFD_RELOC_32_PCREL>: New cases.
Addends for non-zero fx_pcrel are too in fx_offset.
(md_show_usage): Show --march=<arch>.
(md_apply_fix3): Adjust val for BFD_RELOC_CRIS_LAPCQ_OFFSET.
(md_pcrel_from): BFD_RELOC_CRIS_LAPCQ_OFFSET is PC-relative too.
(s_syntax) <struct syntaxes>: Properly constify member operand.
* config/tc-cris.h (TARGET_MACH): Define.
(cris_mach): Declare.
* doc/as.texinfo (Overview) <CRIS>: Add --march=...
* doc/c-cris.texi (CRIS-Symbols): New node for built-in symbols.
(CRIS-Opts): Document --march=...
(CRIS-Pseudos): Document .arch.
2004-11-04 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (set_intel_syntax): Allow % in symbol names when
intel syntax and no register prefix, allow $ in symbol names when
intel syntax.
(set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX.
(intel_float_operand): Add fourth return value indicating math control
operations. Make classification more precise.
(md_assemble): Complain if memory operand of mov[sz]x has no size
specified.
(parse_insn): Translate word operands to floating point instructions
operating on integers as well as control instructions to short ones
as expected by AT&T syntax. Translate 'd' suffix to short one only for
floating point instructions operating on non-integer operands.
(match_template): Remove fldcw special case. Adjust q-suffix handling
to permit it on fild/fistp/fisttp in AT&T mode.
(process_suffix): Don't guess DefaultSize insns' suffix from
stackop_size for certain floating point control instructions. Guess
suffix for branch and [ls][gi]dt based on flag_code. Split error
messages for Intel and AT&T syntax, and make the condition more strict
for the former. Adjust suppressing of generation of operand size
overrides.
(intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE,
OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add
more error checking.
* config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR
SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines.
gas/testsuite/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* gas/i386/i386.exp: Execute new tests intelbad and intelok.
* gas/i386/intelbad.[sl]: New test to check for various things not
permitted in Intel mode.
* gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d:
Adjust for change to segment register store.
* gas/i386/intelok.[sd]: New test to check various Intel mode specific
things get handled correctly.
* gas/i386/x86_64.[sd]: Remove unsupported constructs referring to
'high' and 'low' parts of an operand, which the parser previously
accepted while neither telling that it's not supported nor that it
ignored the remainder of the line following these supposed keywords.
include/opcode/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386.h (sldx_Suf): Remove.
(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
(q_FP): Define, implying no REX64.
(x_FP, sl_FP): Imply FloatMF.
(i386_optab): Split reg and mem forms of moving from segment registers
so that the memory forms can ignore the 16-/32-bit operand size
distinction. Adjust a few others for Intel mode. Remove *FP uses from
all non-floating-point instructions. Unite 32- and 64-bit forms of
movsx, movzx, and movd. Adjust floating point operations for the above
changes to the *FP macros. Add DefaultSize to floating point control
insns operating on larger memory ranges. Remove left over comments
hinting at certain insns being Intel-syntax ones where the ones
actually meant are already gone.
opcodes/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
(indirEb): Remove.
(Mp): Use f_mode rather than none at all.
(t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
replaces what previously was x_mode; x_mode now means 128-bit SSE
operands.
(dis386): Make far jumps and calls have an 'l' prefix only in AT&T
mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
pinsrw's second operand is Edqw.
(grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
mode when an operand size override is present or always suffixing.
More instructions will need to be added to this group.
(putop): Handle new macro chars 'C' (short/long suffix selector),
'I' (Intel mode override for following macro char), and 'J' (for
adding the 'l' prefix to far branches in AT&T mode). When an
alternative was specified in the template, honor macro character when
specified for Intel mode.
(OP_E): Handle new *_mode values. Correct pointer specifications for
memory operands. Consolidate output of index register.
(OP_G): Handle new *_mode values.
(OP_I): Handle const_1_mode.
(OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
respective opcode prefix bits have been consumed.
(OP_EM, OP_EX): Provide some default handling for generating pointer
specifications.
(get_flags): New function.
(get_number_of_bits): Edit comments, update numeric values to supported sizes.
(process_label_constant): Don't support the colon format (SYMBOL:[s|m|l]).
(set_cons_rparams): Support argument type 'arg_rbase'.
(get_operandtype): Bug fix in 'rbase' operand type parsing.
(handle_LoadStor): Bug fix, first handle post-increment mode.
(getreg_image): Remove redundant code, update according to latest CRX spec.
(print_constant): Bug fix relate to 3-word instructions.
(assemble_insn): Bug fix, when matching instructions, verify also instruction type (not only mnemonic).
Add various error checking.
(preprocess_reglist): Support HI/LO and user registers.
PR 474
* config/tc-ia64.c (emit_one_bundle): Decrement md.num_slots_in_use
after reporting template error during manual bundling. Reported
by Michael Dupont, michaelx.dupont@intel.com.
* elf32-xtensa.c (elf_xtensa_get_private_bfd_flags): Delete.
(narrow_instruction, widen_instruction): Remove unnecessary calls to
xtensa_format_encode.
(ebb_propose_action): Inline call to ebb_add_proposed_action.
(ebb_add_proposed_action): Delete.
gas ChangeLog
* config/tc-xtensa.c (xtensa_frequency_pseudo): Use set_subseg_freq.
(is_entry_opcode, is_movi_opcode, is_the_loop_opcode, is_jx_opcode,
is_windowed_return_opcode): Delete.
(xtensa_frob_label): Use get_subseg_target_freq.
(md_assemble): Inline call to is_entry_opcode.
(xtensa_handle_align): Inline call to get_frag_is_literal.
(relaxation_requirements): Inline call to is_jx_opcode.
(emit_single_op): Inline call to is_movi_opcode.
(xg_assemble_vliw_tokens): Inline calls to get_frag_is_insn,
get_frag_is_no_transform, is_entry_opcode, and
set_frag_is_specific_opcode. Use get_subseg_total_freq.
(xtensa_fix_a0_b_retw_frags, xtensa_fix_b_j_loop_end_frags,
xtensa_fix_close_loop_end_frags, relax_frag_immed, convert_frag_immed):
Inline calls to get_frag_is_no_transform.
(next_instrs_are_b_retw): Inline call to is_windowed_return_opcode.
(xtensa_fix_short_loop_frags): Inline calls to is_the_loop_opcode and
get_frag_is_no_transform.
(convert_frag_immed_finish_loop): Inline calls to get_expression_value
and set_frag_is_no_transform.
(get_expression_value): Delete.
(subseg_map struct): Rename cur_total_freq to total_freq. Rename
cur_target_freq to target_freq.
(get_subseg_info): Split out code to create a new map entry into ...
(add_subseg_info): ... this new function.
(get_last_insn_flags): Check if get_subseg_info succeeded.
(set_last_insn_flags): Call add_subseg_info if needed.
(get_subseg_total_freq, get_subseg_target_freq, set_subseg_freq): New.
(xtensa_reorder_segments): Compute last_sec while counting sections.
Remove call to get_last_sec.
(get_last_sec): Delete.
(cache_literal_section): Inline call to retrieve_literal_seg and its
callees, seg_present and add_seg_list.
(retrieve_literal_seg, seg_present, add_seg_list): Delete.
(get_frag_is_insn, get_frag_is_no_transform,
set_frag_is_specific_opcode, set_frag_is_no_transform): Delete.
* config/tc-xtensa.h (MAX_SLOTS): Reduce from 31 to 15.
* elf32-xtensa.c: Use ISO C90 formatting.
gas ChangeLog
* config/tc-xtensa.c: Use ISO C90 formatting.
* config/tc-xtensa.h: Likewise.
* config/xtensa-istack.h: Likewise.
* config/xtensa-relax.c: Likewise.
* config/xtensa-relax.h: Likewise.
ld ChangeLog
* emultempl/xtensaelf.em: Use ISO C90 formatting.
opcodes ChangeLog
* xtensa-dis.c: Use ISO C90 formatting.
bfd/
* elf32-arm.h: Support EABI version 4 objects.
binutils/
* readelf.c (decode_ARM_machine_flags): Support EABI version 4.
gas/
* config/tc-arm.c (md_begin): Change EF_ARM_EABI_VER3 to
EF_ARM_EABI_VER4.
(arm_eabis): Ditto.
* doc/c-arm.texi: Document that we actually support -meabi=4, not
-meabi=3.
include/
* elf/arm.h (EF_ARM_EABI_VER4): Define.
* config.bfd: Include 64-bit support for i[3-7]86-*-solaris2*.
* elf64-x86-64.c (elf64_x86_64_section_from_shdr): New function.
(elf_backend_section_from_shdr): Define.
binutils/
* readelf.c (get_x86_64_section_type_name): New function.
(get_section_type_name): Use it.
gas/
* config/tc-i386.c: Include "elf/x86-64.h".
(i386_elf_section_type): New function.
* config/tc-i386.h (md_elf_section_type): Define.
(i386_elf_section_type): New prototype.
gas/testsuite/
* gas/i386/i386.exp: Don't run divide test for targets where '/'
is a comment. Run x86-64-unwind for 64-bit ELF targets.
* gas/i386/x86-64-unwind.d, gas/i386/x86-64-unwind.s: New.
include/
* elf/common.h (PT_SUNW_EH_FRAME): Define.
* elf/x86-64.h (SHT_X86_64_UNWIND): Define.
ld/
* configure.tgt: Include elf_x86_64 for i[3-7]86-*-solaris2*.
* elf32-xtensa.c (elf32xtensa_size_opt): New global variable.
(xtensa_default_isa): Global variable moved here from xtensa-isa.c.
(elf32xtensa_no_literal_movement): New global variable.
(elf_howto_table): Add entries for new relocations.
(elf_xtensa_reloc_type_lookup): Handle new relocations.
(property_table_compare): When addresses are equal, compare sizes and
various property flags.
(property_table_matches): New.
(xtensa_read_table_entries): Extend to read new property tables. Add
output_addr parameter to indicate that output addresses should be used.
Use bfd_get_section_limit.
(elf_xtensa_find_property_entry): New.
(elf_xtensa_in_literal_pool): Use elf_xtensa_find_property_entry.
(elf_xtensa_check_relocs): Handle new relocations.
(elf_xtensa_do_reloc): Use bfd_get_section_limit. Handle new
relocations. Use new xtensa-isa.h functions.
(build_encoding_error_message): Remove encode_result parameter. Add
new target_address parameter used to detect alignment errors.
(elf_xtensa_relocate_section): Use bfd_get_section_limit. Clean up
error handling. Use new is_operand_relocation function.
(elf_xtensa_combine_prop_entries, elf_xtensa_merge_private_bfd_data):
Use underbar macro for error messages. Formatting.
(get_const16_opcode): New.
(get_l32r_opcode): Add a separate flag for initialization.
(get_relocation_opnd): Operand number is no longer explicit in the
relocation. Change to decode the opcode and analyze its operands.
(get_relocation_slot): New.
(get_relocation_opcode): Add bfd parameter. Use bfd_get_section_limit.
Use new xtensa-isa.h functions to handle multislot instructions.
(is_l32r_relocation): Add bfd parameter. Use is_operand_relocation.
(get_asm_simplify_size, is_alt_relocation, is_operand_relocation,
insn_decode_len, insn_decode_opcode, check_branch_target_aligned,
check_loop_aligned, check_branch_target_aligned_address, narrowable,
widenable, narrow_instruction, widen_instruction, op_single_fmt_table,
get_single_format, init_op_single_format_table): New.
(elf_xtensa_do_asm_simplify): Add error_message parameter and use it
instead of calling _bfd_error_handler. Use new xtensa-isa.h functions.
(contract_asm_expansion): Add error_message parameter and pass it to
elf_xtensa_do_asm_simplify. Replace use of R_XTENSA_OP0 relocation
with R_XTENSA_SLOT0_OP.
(get_expanded_call_opcode): Extend to handle either L32R or CONST16
instructions. Use new xtensa-isa.h functions.
(r_reloc struct): Add new virtual_offset field.
(r_reloc_init): Add contents and content_length parameters. Set
virtual_offset field to zero. Add contents to target_offset field for
partial_inplace relocations.
(r_reloc_is_defined): Check for null.
(print_r_reloc): New debug function.
(source_reloc struct): Replace xtensa_operand field with pair of the
opcode and the operand position. Add is_abs_literal field.
(init_source_reloc): Specify operand by opcode/position pair. Set
is_abs_literal field.
(source_reloc_compare): When target_offsets are equal, compare other
fields to make sorting predictable.
(literal_value struct): Add is_abs_literal field.
(value_map_hash_table struct): Add has_last_loc and last_loc fields.
(init_literal_value): New.
(is_same_value): Replace with ...
(literal_value_equal): ... this function. Add comparisons of
virtual_offset and is_abs_literal fields.
(value_map_hash_table_init): Use bfd_zmalloc. Check for allocation
failure. Initialize has_last_loc field.
(value_map_hash_table_delete): New.
(hash_literal_value): Rename to ...
(literal_value_hash): ... this. Include is_abs_literal flag and
virtual_offset field in the hash value.
(get_cached_value): Rename to ...
(value_map_get_cached_value): ... this. Update calls to
literal_value_hash and literal_value_equal.
(add_value_map): Check for allocation failure. Update calls to
value_map_get_cached_value and literal_value_hash.
(text_action, text_action_list, text_action_t): New types.
(find_fill_action, compute_removed_action_diff, adjust_fill_action,
text_action_add, text_action_add_literal, offset_with_removed_text,
offset_with_removed_text_before_fill, find_insn_action,
print_action_list, print_removed_literals): New.
(offset_with_removed_literals): Delete.
(xtensa_relax_info struct): Add is_relaxable_asm_section, action_list,
fix_array, fix_array_count, allocated_relocs, relocs_count, and
allocated_relocs_count fields.
(init_xtensa_relax_info): Initialize new fields.
(reloc_bfd_fix struct): Add new translated field.
(reloc_bfd_fix_init): Add translated parameter and use it to set the
translated field.
(fix_compare, cache_fix_array): New.
(get_bfd_fix): Remove fix_list parameter and get all relax_info for the
section via get_xtensa_relax_info. Use cache_fix_array to set up
sorted fix_array and use bsearch instead of linear search.
(section_cache_t): New struct.
(init_section_cache, section_cache_section, clear_section_cache): New.
(ebb_t, ebb_target_enum, proposed_action, ebb_constraint): New types.
(init_ebb_constraint, free_ebb_constraint, init_ebb, extend_ebb_bounds,
extend_ebb_bounds_forward, extend_ebb_bounds_backward,
insn_block_decodable_len, ebb_propose_action, ebb_add_proposed_action):
New.
(retrieve_contents): Use bfd_get_section_limit.
(elf_xtensa_relax_section): Add relocations_analyzed flag. Update call
to compute_removed_literals. Free value_map_hash_table when no longer
needed.
(analyze_relocations): Check is_relaxable_asm_section flag. Call
compute_text_actions for all sections.
(find_relaxable_sections): Mark sections as relaxable if they contain
ASM_EXPAND relocations that can be optimized. Adjust r_reloc_init
call. Increment relax_info src_count field only for appropriate
relocation types. Remove is_literal_section check.
(collect_source_relocs): Use bfd_get_section_limit. Adjust calls to
r_reloc_init and find_associated_l32r_irel. Check
is_relaxable_asm_section flag. Handle L32R instructions with absolute
literals. Pass is_abs_literal flag to init_source_reloc.
(is_resolvable_asm_expansion): Use bfd_get_section_limit. Check for
CONST16 instructions. Adjust calls to r_reloc_init and
pcrel_reloc_fits. Handle weak symbols conservatively.
(find_associated_l32r_irel): Add bfd parameter and pass it to
is_l32r_relocation.
(compute_text_actions, compute_ebb_proposed_actions,
compute_ebb_actions, check_section_ebb_pcrels_fit,
check_section_ebb_reduces, text_action_add_proposed,
compute_fill_extra_space): New.
(remove_literals): Replace with ...
(compute_removed_literals): ... this function. Call
init_section_cache. Use bfd_get_section_limit. Sort internal_relocs.
Call xtensa_read_table_entries to get the property table. Skip
relocations other than R_XTENSA_32 and R_XTENSA_PLT. Use new
is_removable_literal, remove_dead_literal, and
identify_literal_placement functions.
(get_irel_at_offset): Rewrite to use bsearch on sorted relocations
instead of linear search.
(is_removable_literal, remove_dead_literal,
identify_literal_placement): New.
(relocations_reach): Update check for literal not referenced by any
PC-relative relocations. Adjust call to pcrel_reloc_fits.
(coalesce_shared_literal, move_shared_literal): New.
(relax_section): Use bfd_get_section_limit. Call
translate_section_fixes. Update calls to r_reloc_init and
offset_with_removed_text. Check new is_relaxable_asm_section flag.
Add call to pin_internal_relocs. Add special handling for
R_XTENSA_ASM_SIMPLIFY and R_XTENSA_DIFF* relocs. Use virtual_offset
info to calculate new addend_displacement variable. Replace code for
deleting literals with more general code to perform the actions
determined by the action_list for the section.
(translate_section_fixes, translate_reloc_bfd_fix): New.
(translate_reloc): Check new is_relaxable_asm_section flag. Call
find_removed_literal only if is_operand_relocation. Update call to
offset_with_removed_text. Use new target_offset and removed_bytes
variables.
(move_literal): New.
(relax_property_section): Use bfd_get_section_limit. Set new
is_full_prop_section flag and handle new property tables. Update calls
to r_reloc_init and offset_with_removed_text. Check
is_relaxable_asm_section flag. Handle expansion of zero-sized
unreachable entries, with use of offset_with_removed_text_before_fill.
For relocatable links, combine entries only for literal tables.
(relax_section_symbols): Check is_relaxable_asm_section flag. Update
calls to offset_with_removed_text. Translate st_size field for
function symbols.
(do_fix_for_relocatable_link): Change to return bfd_boolean to indicate
failure. Add contents parameter. Update call to get_bfd_fix. Update
call to r_reloc_init. Call _bfd_error_handler and return FALSE for
R_XTENSA_ASM_EXPAND relocs.
(do_fix_for_final_link): Add input_bfd and contents parameters. Update
call to get_bfd_fix. Include offset from contents for partial_inplace
relocations.
(is_reloc_sym_weak): New.
(pcrel_reloc_fits): Use new xtensa-isa.h functions.
(prop_sec_len): New.
(xtensa_is_property_section): Handle new property sections.
(is_literal_section): Delete.
(internal_reloc_compare): When r_offset matches, compare r_info and
r_addend to make sorting predictable.
(internal_reloc_matches): New.
(xtensa_get_property_section_name): Handle new property sections.
(xtensa_get_property_predef_flags): New.
(xtensa_callback_required_dependence): Use bfd_get_section_limit.
Update calls to xtensa_isa_init, is_l32r_relocation, and r_reloc_init.
* xtensa-isa.c (xtensa_default_isa): Moved to elf32-xtensa.c.
(xtisa_errno, xtisa_error_msg): New variables.
(xtensa_isa_errno, xtensa_isa_error_msg): New.
(xtensa_insnbuf_alloc): Add error handling.
(xtensa_insnbuf_to_chars): Add num_chars parameter. Update to
use xtensa_format_decode. Add error handling.
(xtensa_insnbuf_from_chars): Add num_chars parameter. Decode the
instruction length to find the number of bytes to copy.
(xtensa_isa_init): Add error handling. Replace calls to
xtensa_load_isa and xtensa_extend_isa with code to initialize lookup
tables in the xtensa_modules structure.
(xtensa_check_isa_config, xtensa_add_isa, xtensa_load_isa,
xtensa_extend_isa): Delete.
(xtensa_isa_free): Change to only free lookup tables.
(opname_lookup_compare): Replace with ...
(xtensa_isa_name_compare): ... this function. Use strcasecmp.
(xtensa_insn_maxlength): Rename to ...
(xtensa_isa_maxlength): ... this.
(xtensa_insn_length): Delete.
(xtensa_insn_length_from_first_byte): Replace with ...
(xtensa_isa_length_from_chars): ... this function.
(xtensa_num_opcodes): Rename to ...
(xtensa_isa_num_opcodes): ... this.
(xtensa_isa_num_pipe_stages, xtensa_isa_num_formats,
xtensa_isa_num_regfiles, xtensa_isa_num_stages,
xtensa_isa_num_sysregs, xtensa_isa_num_interfaces,
xtensa_isa_num_funcUnits, xtensa_format_name, xtensa_format_lookup,
xtensa_format_decode, xtensa_format_encode, xtensa_format_length,
xtensa_format_num_slots, xtensa_format_slot_nop_opcode,
xtensa_format_get_slot, xtensa_format_set_slot): New functions.
(xtensa_opcode_lookup): Add error handling.
(xtensa_decode_insn): Replace with ...
(xtensa_opcode_decode): ... this function, with new format and
slot parameters. Add error handling.
(xtensa_encode_insn): Replace with ...
(xtensa_opcode_encode): ... this function, which does the encoding via
one of the entries in the "encode_fns" array. Add error handling.
(xtensa_opcode_name): Add error handling.
(xtensa_opcode_is_branch, xtensa_opcode_is_jump, xtensa_opcode_is_loop,
xtensa_opcode_is_call): New.
(xtensa_num_operands): Replace with ...
(xtensa_opcode_num_operands): ... this function. Add error handling.
(xtensa_opcode_num_stateOperands,
xtensa_opcode_num_interfaceOperands, xtensa_opcode_num_funcUnit_uses,
xtensa_opcode_funcUnit_use, xtensa_operand_name,
xtensa_operand_is_visible): New.
(xtensa_get_operand, xtensa_operand_kind): Delete.
(xtensa_operand_inout): Add error handling and special-case for
"sout" operands.
(xtensa_operand_get_field, xtensa_operand_set_field): Rewritten to
operate on one slot of an instruction. Added error handling.
(xtensa_operand_encode): Handle default operands with no encoding
functions. Check for success by comparing against decoded value.
Add error handling.
(xtensa_operand_decode): Handle default operands. Return decoded value
through argument pointer. Add error handling.
(xtensa_operand_is_register, xtensa_operand_regfile,
xtensa_operand_num_regs, xtensa_operand_is_known_reg): New.
(xtensa_operand_isPCRelative): Rename to ...
(xtensa_operand_is_PCrelative): ... this. Add error handling.
(xtensa_operand_do_reloc, xtensa_operand_undo_reloc): Return value
through argument pointer. Add error handling.
(xtensa_stateOperand_state, xtensa_stateOperand_inout,
xtensa_interfaceOperand_interface, xtensa_regfile_lookup,
xtensa_regfile_lookup_shortname, xtensa_regfile_name,
xtensa_regfile_shortname, xtensa_regfile_view_parent,
xtensa_regfile_num_bits, xtensa_regfile_num_entries,
xtensa_state_lookup, xtensa_state_name, xtensa_state_num_bits,
xtensa_state_is_exported, xtensa_sysreg_lookup,
xtensa_sysreg_lookup_name, xtensa_sysreg_name, xtensa_sysreg_number,
xtensa_sysreg_is_user, xtensa_interface_lookup, xtensa_interface_name,
xtensa_interface_num_bits, xtensa_interface_inout,
xtensa_interface_has_side_effect, xtensa_funcUnit_lookup,
xtensa_funcUnit_name, xtensa_funcUnit_num_copies): New.
* xtensa-modules.c: Rewrite to use new data structures.
* reloc.c (BFD_RELOC_XTENSA_DIFF8, BFD_RELOC_XTENSA_DIFF16,
BFD_RELOC_XTENSA_DIFF32, BFD_RELOC_XTENSA_SLOT0_OP,
BFD_RELOC_XTENSA_SLOT1_OP, BFD_RELOC_XTENSA_SLOT2_OP,
BFD_RELOC_XTENSA_SLOT3_OP, BFD_RELOC_XTENSA_SLOT4_OP,
BFD_RELOC_XTENSA_SLOT5_OP, BFD_RELOC_XTENSA_SLOT6_OP,
BFD_RELOC_XTENSA_SLOT7_OP, BFD_RELOC_XTENSA_SLOT8_OP,
BFD_RELOC_XTENSA_SLOT9_OP, BFD_RELOC_XTENSA_SLOT10_OP,
BFD_RELOC_XTENSA_SLOT11_OP, BFD_RELOC_XTENSA_SLOT12_OP,
BFD_RELOC_XTENSA_SLOT13_OP, BFD_RELOC_XTENSA_SLOT14_OP,
BFD_RELOC_XTENSA_SLOT0_ALT, BFD_RELOC_XTENSA_SLOT1_ALT,
BFD_RELOC_XTENSA_SLOT2_ALT, BFD_RELOC_XTENSA_SLOT3_ALT,
BFD_RELOC_XTENSA_SLOT4_ALT, BFD_RELOC_XTENSA_SLOT5_ALT,
BFD_RELOC_XTENSA_SLOT6_ALT, BFD_RELOC_XTENSA_SLOT7_ALT,
BFD_RELOC_XTENSA_SLOT8_ALT, BFD_RELOC_XTENSA_SLOT9_ALT,
BFD_RELOC_XTENSA_SLOT10_ALT, BFD_RELOC_XTENSA_SLOT11_ALT,
BFD_RELOC_XTENSA_SLOT12_ALT, BFD_RELOC_XTENSA_SLOT13_ALT,
BFD_RELOC_XTENSA_SLOT14_ALT): Add new relocations.
* Makefile.am (xtensa-isa.lo, xtensa-modules.lo): Update dependencies.
* Makefile.in: Regenerate.
* bfd-in2.h: Likewise.
* libbfd.h: Likewise.
gas ChangeLog
* config/tc-xtensa.c (absolute_literals_supported): New global flag.
(UNREACHABLE_MAX_WIDTH): Define.
(XTENSA_FETCH_WIDTH): Delete.
(cur_vinsn, xtensa_fetch_width, xt_saved_debug_type, past_xtensa_end,
prefer_const16, prefer_l32r): New global variables.
(LIT4_SECTION_NAME): Define.
(lit4_state struct): Add lit4_seg_name and lit4_seg fields.
(XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define.
(frag_flags struct): New.
(xtensa_block_info struct): Move from tc-xtensa.h. Add flags field.
(subseg_map struct): Add cur_total_freq and cur_target_freq fields.
(bitfield, bit_is_set, set_bit, clear_bit): Define.
(MAX_FORMATS): Define.
(op_placement_info struct, op_placement_table): New.
(O_pltrel, O_hi16, O_lo16): Define.
(directiveE enum): Rename directive_generics to directive_transform.
Delete directive_relax. Add directive_schedule,
directive_absolute_literals, and directive_last_directive.
(directive_info): Rename "generics" to "transform". Delete "relax".
Add "schedule" and "absolute-literals".
(directive_state): Adjust entries to match changes in directive_info.
(xtensa_relax_statesE, RELAX_IMMED_MAXSTEPS): Move to tc-xtensa.h.
(xtensa_const16_opcode, xtensa_movi_opcode, xtensa_movi_n_opcode,
xtensa_l32r_opcode, xtensa_nop_opcode, xtensa_rsr_lcount_opcode): New.
(xtensa_j_opcode, xtensa_rsr_opcode): Delete.
(align_only_targets, software_a0_b_retw_interlock,
software_avoid_b_j_loop_end, maybe_has_b_j_loop_end,
software_avoid_short_loop, software_avoid_close_loop_end,
software_avoid_all_short_loops, specific_opcode): Delete.
(warn_unaligned_branch_targets): New.
(workaround_a0_b_retw, workaround_b_j_loop_end, workaround_short_loop,
workaround_close_loop_end, workaround_all_short_loops): Default FALSE.
(option_[no_]link_relax, option_[no_]transform,
option_[no_]absolute_literals, option_warn_unaligned_targets,
option_prefer_l32r, option_prefer_const16, option_target_hardware):
New enum values.
(option_[no_]align_only_targets, option_literal_section_name,
option_text_section_name, option_data_section_name,
option_bss_section_name, option_eb, option_el): Delete.
(md_longopts): Add entries for: [no-]transform, [no-]absolute-literals,
warn-unaligned-targets, prefer-l32r, prefer-const16, [no-]link-relax,
and target-hardware. Delete entries for [no-]target-align-only,
literal-section-name, text-section-name, data-section-name, and
bss-section-name.
(md_parse_option): Handle new options and remove old ones. Accept but
ignore [no-]density options. Warn for [no-]generics and [no-]relax
and treat them as [no-]transform.
(md_show_usage): Add new options and remove old ones.
(xtensa_setup_hw_workarounds): New.
(md_pseudo_table): Change "word" entry to use xtensa_elf_cons. Add
"long", "short", "loc" and "frequency" entries.
(use_generics): Rename to ...
(use_transform): ... this function. Add past_xtensa_end check.
(use_longcalls): Add past_xtensa_end check.
(code_density_available, can_relax): Delete.
(do_align_targets): New.
(get_directive): Accept dashes in directive names. Warn about
[no-]generics and [no-]relax directives and treat them as
[no-]transform.
(xtensa_begin_directive): Call md_flush_pending_output only for some
directives. Check for directives inside instruction bundles. Warn
about deprecated ".begin literal" usage. Warn and ignore [no-]density
directives. Handle new directives. Check generating_literals flag
for literal_prefix.
(xtensa_end_directive): Check for directives inside instruction
bundles. Warn and ignore [no-]density directives. Handle new
directives. Call xtensa_set_frag_assembly_state.
(xtensa_loc_directive_seen, xtensa_dwarf2_directive_loc,
xtensa_dwarf2_emit_insn): New.
(xtensa_literal_position): Call md_flush_pending_output. Do not check
use_literal_section flag.
(xtensa_literal_pseudo): Call md_flush_pending_output. Handle absolute
literals. Use xtensa_elf_cons to parse the expression.
(xtensa_literal_prefix): Do not check use_literal_section. Support
".lit4" sections for absolute literals. Change prefix convention to
replace ".text" (or ".t" in a linkonce section). No need to call
subseg_set.
(xtensa_frequency_pseudo, xtensa_elf_cons, xtensa_elf_suffix): New.
(expression_end): Handle closing braces and colons.
(PLT_SUFFIX, plt_suffix): Delete.
(expression_maybe_register): Use new xtensa-isa.h functions. Use
xtensa_elf_suffix instead of checking for plt suffix, and handle O_lo16
and O_hi16 expressions as well.
(tokenize_arguments): Handle closing braces and colons.
(parse_arguments): Use new xtensa-isa.h functions. Handle "invisible"
operands and paired register syntax.
(get_invisible_operands): New.
(xg_translate_sysreg_op): Handle new Xtensa LX RSR/WSR/XSR syntax. Use
new xtensa-isa.h functions.
(xtensa_translate_old_userreg_ops, xtensa_translate_zero_immed): New.
(xg_translate_idioms): Check if inside bundle. Use use_transform.
Handle new Xtensa LX RSR/WSR/XSR syntax. Remove code to widen density
instructions. Use xtensa_translate_zero_immed.
(operand_is_immed, operand_is_pcrel_label): Delete.
(get_relaxable_immed): Use new xtensa-isa.h functions.
(get_opcode_from_buf): Add slot parameter. Use new xtensa-isa.h
functions.
(xtensa_print_insn_table, print_vliw_insn): New.
(is_direct_call_opcode): Use new xtensa-isa.h functions.
(is_call_opcode, is_loop_opcode, is_conditional_branch_opcode,
is_branch_or_jump_opcode): Delete.
(is_movi_opcode, decode_reloc, encode_reloc, encode_alt_reloc): New.
(opnum_to_reloc, reloc_to_opnum): Delete.
(xtensa_insnbuf_set_operand, xtensa_insnbuf_get_operand): Use new
xtensa-isa.h functions. Operate on one slot of an instruction.
(xtensa_insnbuf_set_immediate_field, is_negatable_branch,
xg_get_insn_size): Delete.
(xg_get_build_instr_size): Use xg_get_single_size.
(xg_is_narrow_insn, xg_is_single_relaxable_insn): Update calls to
xg_build_widen_table. Use xg_get_single_size.
(xg_get_max_narrow_insn_size): Delete.
(xg_get_max_insn_widen_size, xg_get_max_insn_widen_literal_size,
xg_is_relaxable_insn): Update calls to xg_build_widen_table. Use
xg_get_single_size.
(xg_build_to_insn): Record the loc field. Handle OP_OPERAND_HI16U and
OP_OPERAND_LOW16U. Check xg_valid_literal_expression.
(xg_expand_to_stack, xg_expand_narrow): Update calls to
xg_build_widen_table. Use xg_get_single_size.
(xg_immeds_fit): Use new xtensa-isa.h functions. Update call to
xg_check_operand.
(xg_symbolic_immeds_fit): Likewise. Also handle O_lo16 and O_hi16, and
treat weak symbols conservatively.
(xg_check_operand): Use new xtensa-isa.h functions.
(is_dnrange): Delete.
(xg_assembly_relax): Inline previous calls to tinsn_copy.
(xg_finish_frag): Specify separate relax states for the frag and slot0.
(is_branch_jmp_to_next, xg_add_branch_and_loop_targets): Use new
xtensa-isa.h functions.
(xg_instruction_matches_option_term, xg_instruction_matches_or_options,
xg_instruction_matches_options): New.
(xg_instruction_matches_rule): Handle O_register expressions. Call
xg_instruction_matches_options.
(transition_rule_cmp): New.
(xg_instruction_match): Update call to xg_build_simplify_table.
(xg_build_token_insn): Record loc fields.
(xg_simplify_insn): Check is_specific_opcode field and
density_supported flag.
(xg_expand_assembly_insn): Skip checking code_density_available. Use
new xtensa-isa.h functions. Call use_transform instead of can_relax.
(xg_assemble_literal): Add error handling for O_big. Call
record_alignment. Handle O_pltrel.
(xg_valid_literal_expression): New.
(xg_assemble_literal_space): Add slot parameter. Remove call to
set_expr_symbol_offset. Add call to record_alignment. Update call to
xg_finish_frag.
(xg_emit_insn): Delete.
(xg_emit_insn_to_buf): Add format parameter. Update calls to
xg_add_opcode_fix and xtensa_insnbuf_to_chars.
(xg_add_opcode_fix): Change opcode parameter to tinsn and add format
and slot parameters. Handle new "alternate" relocations for absolute
literals and CONST16 instructions. Check for bad uses of O_lo16 and
O_hi16. Use new xtensa-isa.h functions.
(xg_assemble_tokens): Delete.
(is_register_writer): Use new xtensa-isa.h functions.
(is_bad_loopend_opcode): Check for xtensa_rsr_lcount_opcode instead of
old-style RSR from LCOUNT.
(next_frag_opcode): Delete.
(next_frag_opcode_is_loop, next_frag_format_size, frag_format_size,
update_next_frag_state): New.
(update_next_frag_nop_state): Delete.
(next_frag_pre_opcode_bytes): Use next_frag_opcode_is_loop.
(xtensa_mark_literal_pool_location): Check use_literal_section flag and
the state of the absolute-literals directive. Add calls to
record_alignment and xtensa_set_frag_assembly_state. Call
xtensa_switch_to_non_abs_literal_fragment instead of
xtensa_switch_to_literal_fragment.
(build_nop): New.
(assemble_nop): Use build_nop. Update call to xtensa_insnbuf_to_chars.
(get_expanded_loop_offset): Change check for undefined opcode to an
assertion.
(xtensa_set_frag_assembly_state, relaxable_section,
xtensa_find_unmarked_state_frags, xtensa_find_unaligned_branch_targets,
xtensa_find_unaligned_loops, xg_apply_tentative_value): New.
(md_begin): Update call to xtensa_isa_init. Initialize linkrelax to 1.
Set lit4_seg_name. Call xg_init_vinsn. Initialize new global opcodes.
Call init_op_placement_info_table and xtensa_set_frag_assembly_state.
(xtensa_init_fix_data): New.
(xtensa_frob_label): Reset label symbol to the current frag. Check
do_align_targets and generating_literals flag. Propagate frequency
info to new alignment frag. Call xtensa_set_frag_assembly_state.
(xtensa_unrecognized_line): New.
(xtensa_flush_pending_output): Check if inside a bundle. Add a call
to xtensa_set_frag_assembly_state.
(error_reset_cur_vinsn): New.
(md_assemble): Remove check for literal frag. Remove call to
istack_init. Call use_transform instead of use_generics. Parse
explicit instruction format specifiers. Move code for
a0_b_retw_interlock workaround to xg_assemble_vliw_tokens. Call
error_reset_cur_vinsn on errors. Add call to get_invisible_operands.
Add dwarf2_where call. Remote automatic alignment for ENTRY
instructions. Move call to xtensa_clear_insn_labels to the end.
Rearrange to handle bundles.
(xtensa_cons_fix_new): Delete.
(xtensa_handle_align): New.
(xtensa_frag_init): Call xtensa_set_frag_assembly_state. Remove
assignment to is_no_density field.
(md_pcrel_from): Use new xtensa-isa.h functions. Use decode_reloc
instead of reloc_to_opnum. Handle "alternate" relocations.
(xtensa_force_relocation, xtensa_check_inside_bundle,
xtensa_elf_section_change_hook): New.
(xtensa_symbol_new_hook): Delete.
(xtensa_fix_adjustable): Check for difference of symbols with an
offset. Check for external and weak symbols.
(md_apply_fix3): Remove cases for XTENSA_OP{0,1,2} relocs.
(md_estimate_size_before_relax): Return expansion for the first slot.
(tc_gen_reloc): Handle difference of symbols by producing
XTENSA_DIFF{8,16,32} relocs and by writing the value of the difference
into the output. Handle new XTENSA_SLOT*_OP relocs by storing the
tentative values into the output when linkrelax is set.
(XTENSA_PROP_SEC_NAME): Define.
(xtensa_post_relax_hook): Call xtensa_find_unmarked_state_frags.
Create literal tables only if using literal sections. Create new
property tables instead of old instruction tables. Check for unaligned
branch targets and loops.
(finish_vinsn, find_vinsn_conflicts, check_t1_t2_reads_and_writes,
new_resource_table, clear_resource_table, resize_resource_table,
resources_available, reserve_resources, release_resources,
opcode_funcUnit_use_unit, opcode_funcUnit_use_stage,
resources_conflict, xg_find_narrowest_format, relaxation_requirements,
bundle_single_op, emit_single_op, xg_assemble_vliw_tokens): New.
(xtensa_end): Call xtensa_flush_pending_output. Set past_xtensa_end
flag. Update checks for workaround options. Call
xtensa_mark_narrow_branches and xtensa_mark_zcl_first_insns.
(xtensa_cleanup_align_frags): Add special case for branch targets.
Check for and mark unreachable frags.
(xtensa_fix_target_frags): Remove use of align_only_targets flag.
Use RELAX_LOOP_END_BYTES in special case for negatable branch at the
end of a zero-overhead loop body.
(frag_can_negate_branch): Handle instructions with multiple slots.
Use new xtensa-isa.h functions
(xtensa_mark_narrow_branches, is_narrow_branch_guaranteed_in_range,
xtensa_mark_zcl_first_insns): New.
(xtensa_fix_a0_b_retw_frags, xtensa_fix_b_j_loop_end_frags): Error if
transformations are disabled.
(next_instrs_are_b_retw): Use new xtensa-isa.h functions. Handle
multislot instructions.
(xtensa_fix_close_loop_end_frags, xtensa_fix_short_loop_frags):
Likewise. Also error if transformations are disabled.
(unrelaxed_frag_max_size): New.
(unrelaxed_frag_min_insn_count, unrelax_frag_has_b_j): Use new
xtensa-isa.h functions.
(xtensa_sanity_check, is_empty_loop, is_local_forward_loop): Use
xtensa_opcode_is_loop instead of is_loop_opcode.
(get_text_align_power): Replace as_fatal with assertion.
(get_text_align_fill_size): Iterate instead of using modulus when
use_nops is false.
(get_noop_aligned_address): Assert that this is for a machine-dependent
RELAX_ALIGN_NEXT_OPCODE frag. Use next_frag_opcode_is_loop,
xg_get_single_size, and frag_format_size.
(get_widen_aligned_address): Rename to ...
(get_aligned_diff): ... this function. Add max_diff parameter.
Remove handling of rs_align/rs_align_code frags. Use
next_frag_format_size, get_text_align_power, get_text_align_fill_size,
next_frag_opcode_is_loop, and xg_get_single_size. Compute max_diff
and pass it back to caller.
(xtensa_relax_frag): Use relax_frag_loop_align. Add code for new
RELAX_SLOTS, RELAX_MAYBE_UNREACHABLE, RELAX_MAYBE_DESIRE_ALIGN,
RELAX_FILL_NOP, and RELAX_UNREACHABLE frag types. Check relax_seen.
(relax_frag_text_align): Rename to ...
(relax_frag_loop_align): ... this function. Assume loops can only be
in the first slot of an instruction.
(relax_frag_add_nop): Use assemble_nop instead of constructing an OR
instruction. Remove call to frag_wane.
(relax_frag_narrow): Rename to ...
(relax_frag_for_align): ... this function. Extend to handle
RELAX_FILL_NOP and RELAX_UNREACHABLE, as well as RELAX_SLOTS with
RELAX_NARROW for the first slot.
(find_address_of_next_align_frag, bytes_to_stretch): New.
(future_alignment_required): Use find_address_of_next_align_frag and
bytes_to_stretch. Look ahead to subsequent frags to make smarter
alignment decisions.
(relax_frag_immed): Add format, slot, and estimate_only parameters.
Check if transformations are enabled for b_j_loop_end workaround.
Use new xtensa-isa.h functions and handle multislot instructions.
Update call to xg_assembly_relax.
(md_convert_frag): Handle new RELAX_SLOTS, RELAX_UNREACHABLE,
RELAX_MAYBE_UNREACHABLE, RELAX_MAYBE_DESIRE_ALIGN, and RELAX_FILL_NOP
frag types.
(convert_frag_narrow): Add segP, format and slot parameters. Call
convert_frag_immed for branch instructions. Adjust calls to
tinsn_from_chars, tinsn_immed_from_frag, and xg_emit_insn_to_buf. Use
xg_get_single_size and xg_get_single_format.
(convert_frag_fill_nop): New.
(convert_frag_immed): Add format and slot parameters. Handle multislot
instructions and use new xtensa-isa.h functions. Update calls to
tinsn_immed_from_frag and xg_assembly_relax. Check if transformations
enabled for b_j_loop_end workaround. Use build_nop instead of
assemble_nop. Check is_specific_opcode flag. Check for unreachable
frags. Use xg_get_single_size. Handle O_pltrel.
(fix_new_exp_in_seg): Remove check for old plt flag.
(convert_frag_immed_finish_loop): Update calls to tinsn_from_chars and
xtensa_insnbuf_to_chars. Call tinsn_immed_from_frag. Change check
for loop opcode to an assertion. Mark all frags up to the end of the
loop as not transformable.
(get_last_insn_flags, set_last_insn_flags): Use get_subseg_info.
(get_subseg_info): New.
(xtensa_move_literals): Call xtensa_set_frag_assembly_state. Add null
check for dest_seg.
(xtensa_switch_to_literal_fragment): Rewrite to handle absolute
literals and use xtensa_switch_to_non_abs_literal_fragment otherwise.
(xtensa_switch_to_non_abs_literal_fragment): New.
(cache_literal_section): Add is_code parameter and pass it through to
retrieve_literal_seg.
(retrieve_literal_seg): Add is_code parameter and use it to set the
flags on the literal section. Handle case where head parameter is 0.
(get_frag_is_no_transform, set_frag_is_specific_opcode,
set_frag_is_no_transform): New.
(xtensa_create_property_segments): Add end_property_function parameter
and pass it through to add_xt_block_frags. Call bfd_get_section_flags
and skip SEC_DEBUGGING and !SEC_ALLOC sections.
(xtensa_create_xproperty_segments, section_has_xproperty): New.
(add_xt_block_frags): Add end_property_function parameter and call it
if it is non-zero. Call xtensa_frag_flags_init.
(xtensa_frag_flags_is_empty, xtensa_frag_flags_init,
get_frag_property_flags, frag_flags_to_number,
xtensa_frag_flags_combinable, xt_block_aligned_size,
xtensa_xt_block_combine, add_xt_prop_frags,
init_op_placement_info_table, opcode_fits_format_slot,
xg_get_single_size, xg_get_single_format): New.
(istack_push): Inline call to tinsn_copy.
(tinsn_copy): Delete.
(tinsn_has_invalid_symbolic_operands): Handle O_hi16 and O_lo16 and
CONST16 opcodes. Handle O_big, O_illegal, and O_absent.
(tinsn_has_complex_operands): Handle O_hi16 and O_lo16.
(tinsn_to_insnbuf): Use xg_get_single_format and new xtensa-isa.h
functions. Handle invisible operands.
(tinsn_to_slotbuf): New.
(tinsn_check_arguments): Use new xtensa-isa.h functions.
(tinsn_from_chars): Add slot parameter. Rewrite using xg_init_vinsn,
vinsn_from_chars, and xg_free_vinsn.
(tinsn_from_insnbuf): New.
(tinsn_immed_from_frag): Add slot parameter and handle multislot
instructions. Handle symbol differences.
(get_num_stack_text_bytes): Use xg_get_single_size.
(xg_init_vinsn, xg_clear_vinsn, vinsn_has_specific_opcodes,
xg_free_vinsn, vinsn_to_insnbuf, vinsn_from_chars, expr_is_register,
get_expr_register, set_expr_symbol_offset_diff): New.
* config/tc-xtensa.h (MAX_SLOTS): Define.
(xtensa_relax_statesE): Move from tc-xtensa.c. Add
RELAX_CHECK_ALIGN_NEXT_OPCODE, RELAX_MAYBE_DESIRE_ALIGN, RELAX_SLOTS,
RELAX_FILL_NOP, RELAX_UNREACHABLE, RELAX_MAYBE_UNREACHABLE, and
RELAX_NONE types.
(RELAX_IMMED_MAXSTEPS): Move from tc-xtensa.c.
(xtensa_frag_type struct): Add is_assembly_state_set,
use_absolute_literals, relax_seen, is_unreachable, is_specific_opcode,
is_align, is_text_align, alignment, and is_first_loop_insn fields.
Replace is_generics and is_relax fields by is_no_transform field.
Delete is_text and is_longcalls fields. Change text_expansion and
literal_expansion to arrays of MAX_SLOTS entries. Add arrays of
per-slot information: literal_frags, slot_subtypes, slot_symbols,
slot_sub_symbols, and slot_offsets. Add fr_prev field.
(xtensa_fix_data struct): New.
(xtensa_symfield_type struct): Delete plt field.
(xtensa_block_info struct): Move definition to tc-xtensa.h. Add
forward declaration here.
(xt_section_type enum): Delete xt_insn_sec. Add xt_prop_sec.
(XTENSA_SECTION_RENAME): Undefine.
(TC_FIX_TYPE, TC_INIT_FIX_DATA, TC_FORCE_RELOCATION, NO_PSEUDO_DOT,
tc_unrecognized_line, md_do_align, md_elf_section_change_hook,
HANDLE_ALIGN, TC_LINKRELAX_FIXUP, SUB_SEGMENT_ALIGN): Define.
(TC_CONS_FIX_NEW, tc_symbol_new_hook): Delete.
(unit_num_copies_func, opcode_num_units_func,
opcode_funcUnit_use_unit_func, opcode_funcUnit_use_stage_func): New.
(resource_table struct): New.
* config/xtensa-istack.h (MAX_INSN_ARGS): Increase from 6 to 10.
(TInsn struct): Add keep_wide, loc, fixup, record_fix, subtype,
literal_space, symbol, sub_symbol, offset, and literal_frag fields.
(tinsn_copy): Delete prototype.
(vliw_insn struct): New.
* config/xtensa-relax.c (insn_pattern_struct): Add options field.
(widen_spec_list): Add option conditions for density and boolean
instructions. Add expansions using CONST16 and conditions for using
CONST16 vs. L32R. Use new Xtensa LX RSR/WSR syntax. Add entries for
predicted branches.
(simplify_spec_list): Add option conditions for density instructions.
Add entry for NOP instruction.
(append_transition): Add cmp function pointer parameter and use it to
insert the new entry in order.
(operand_function_LOW16U, operand_function_HI16U): New.
(xg_has_userdef_op_fn, xg_apply_userdef_op_fn): Handle
OP_OPERAND_LOW16U and OP_OPERAND_HI16U.
(enter_opname, split_string): Use xstrdup instead of strdup.
(init_insn_pattern): Initialize new options field.
(clear_req_or_option_list, clear_req_option_list,
clone_req_or_option_list, clone_req_option_list, parse_option_cond):
New.
(parse_insn_pattern): Parse option conditions.
(transition_applies): New.
(build_transition): Use new xtensa-isa.h functions. Fix incorrectly
swapped last arguments in calls to append_constant_value_condition.
Call clone_req_option_list. Add warning about invalid opcode.
Handle LOW16U and HI16U function names.
(build_transition_table): Add cmp parameter and use it in calls to
append_transition. Use new xtensa-isa.h functions. Check
transition_applies before adding entries.
(xg_build_widen_table, xg_build_simplify_table): Add cmp parameter and
pass it through to build_transition_table.
* config/xtensa-relax.h (ReqOrOptionList, ReqOrOption, ReqOptionList,
ReqOption, transition_cmp_fn): New types.
(OpType enum): Add OP_OPERAND_LOW16U and OP_OPERAND_HI16U.
(transition_rule struct): Add options field.
* doc/as.texinfo (Overview): Update Xtensa options.
* doc/c-xtensa.texi (Xtensa Options): Delete --[no-]density,
--[no-]relax, and --[no-]generics options. Update descriptions of
--text-section-literals and --[no-]longcalls. Add
--[no-]absolute-literals and --[no-]transform.
(Xtensa Syntax): Add description of syntax for FLIX instructions.
Remove use of "generic" and "specific" terminology for opcodes.
(Xtensa Registers): Generalize the syntax description to include
user-defined register files.
(Xtensa Automatic Alignment): Update.
(Xtensa Branch Relaxation): Mention limitation of unconditional jumps.
(Xtensa Call Relaxation): Linker can now remove most of the overhead.
(Xtensa Directives): Remove confusing rules about precedence.
(Density Directive, Relax Directive): Delete.
(Schedule Directive): New.
(Generics Directive): Rename to ...
(Transform Directive): ... this node.
(Literal Directive): Update for absolute literals. Missing
literal_position directive is now an error.
(Literal Position Directive): Update for absolute literals.
(Freeregs Directive): Delete.
(Absolute Literals Directive): New.
(Frame Directive): Minor editing.
* Makefile.am (DEPTC_xtensa_elf, DEPOBJ_xtensa_elf, DEP_xtensa_elf):
Update dependencies.
* Makefile.in: Regenerate.
gas/testsuite ChangeLog
* gas/xtensa/all.exp: Adjust expected error message for j_too_far.
Change entry_align test to expect an error.
* gas/xtensa/entry_misalign2.s: Use no-transform instead of
no-generics directives.
include ChangeLog
* xtensa-config.h (XSHAL_USE_ABSOLUTE_LITERALS,
XCHAL_HAVE_PREDICTED_BRANCHES, XCHAL_INST_FETCH_WIDTH): New.
(XCHAL_EXTRA_SA_SIZE, XCHAL_EXTRA_SA_ALIGN): Delete.
* xtensa-isa-internal.h (ISA_INTERFACE_VERSION): Delete.
(config_sturct struct): Delete.
(XTENSA_OPERAND_IS_REGISTER, XTENSA_OPERAND_IS_PCRELATIVE,
XTENSA_OPERAND_IS_INVISIBLE, XTENSA_OPERAND_IS_UNKNOWN,
XTENSA_OPCODE_IS_BRANCH, XTENSA_OPCODE_IS_JUMP,
XTENSA_OPCODE_IS_LOOP, XTENSA_OPCODE_IS_CALL,
XTENSA_STATE_IS_EXPORTED, XTENSA_INTERFACE_HAS_SIDE_EFFECT): Define.
(xtensa_format_encode_fn, xtensa_get_slot_fn, xtensa_set_slot_fn): New.
(xtensa_insn_decode_fn): Rename to ...
(xtensa_opcode_decode_fn): ... this.
(xtensa_immed_decode_fn, xtensa_immed_encode_fn, xtensa_do_reloc_fn,
xtensa_undo_reloc_fn): Update.
(xtensa_encoding_template_fn): Delete.
(xtensa_opcode_encode_fn, xtensa_format_decode_fn,
xtensa_length_decode_fn): New.
(xtensa_format_internal, xtensa_slot_internal): New types.
(xtensa_operand_internal): Delete operand_kind, inout, isPCRelative,
get_field, and set_field fields. Add name, field_id, regfile,
num_regs, and flags fields.
(xtensa_arg_internal): New type.
(xtensa_iclass_internal): Change operands field to array of
xtensa_arg_internal. Add num_stateOperands, stateOperands,
num_interfaceOperands, and interfaceOperands fields.
(xtensa_opcode_internal): Delete length, template, and iclass fields.
Add iclass_id, flags, encode_fns, num_funcUnit_uses, and funcUnit_uses.
(opname_lookup_entry): Delete.
(xtensa_regfile_internal, xtensa_interface_internal,
xtensa_funcUnit_internal, xtensa_state_internal,
xtensa_sysreg_internal, xtensa_lookup_entry): New.
(xtensa_isa_internal): Replace opcode_table field with opcodes field.
Change type of opname_lookup_table. Delete num_modules,
module_opcode_base, module_decode_fn, config, and has_density fields.
Add num_formats, formats, format_decode_fn, length_decode_fn,
num_slots, slots, num_fields, num_operands, operands, num_iclasses,
iclasses, num_regfiles, regfiles, num_states, states,
state_lookup_table, num_sysregs, sysregs, sysreg_lookup_table,
max_sysreg_num, sysreg_table, num_interfaces, interfaces,
interface_lookup_table, num_funcUnits, funcUnits and
funcUnit_lookup_table fields.
(xtensa_isa_module, xtensa_isa_modules): Delete.
(xtensa_isa_name_compare): New prototype.
(xtisa_errno, xtisa_error_msg): New.
* xtensa-isa.h (XTENSA_ISA_VERSION): Define.
(xtensa_isa): Change type.
(xtensa_operand): Delete.
(xtensa_format, xtensa_regfile, xtensa_state, xtensa_sysreg,
xtensa_interface, xtensa_funcUnit, xtensa_isa_status,
xtensa_funcUnit_use): New types.
(libisa_module_specifier): Delete.
(xtensa_isa_errno, xtensa_isa_error_msg): New prototypes.
(xtensa_insnbuf_free, xtensa_insnbuf_to_chars,
xtensa_insnbuf_from_chars): Update prototypes.
(xtensa_load_isa, xtensa_extend_isa, xtensa_default_isa,
xtensa_insn_maxlength, xtensa_num_opcodes, xtensa_decode_insn,
xtensa_encode_insn, xtensa_insn_length,
xtensa_insn_length_from_first_byte, xtensa_num_operands,
xtensa_operand_kind, xtensa_encode_result,
xtensa_operand_isPCRelative): Delete.
(xtensa_isa_init, xtensa_operand_inout, xtensa_operand_get_field,
xtensa_operand_set_field, xtensa_operand_encode,
xtensa_operand_decode, xtensa_operand_do_reloc,
xtensa_operand_undo_reloc): Update prototypes.
(xtensa_isa_maxlength, xtensa_isa_length_from_chars,
xtensa_isa_num_pipe_stages, xtensa_isa_num_formats,
xtensa_isa_num_opcodes, xtensa_isa_num_regfiles, xtensa_isa_num_states,
xtensa_isa_num_sysregs, xtensa_isa_num_interfaces,
xtensa_isa_num_funcUnits, xtensa_format_name, xtensa_format_lookup,
xtensa_format_decode, xtensa_format_encode, xtensa_format_length,
xtensa_format_num_slots, xtensa_format_slot_nop_opcode,
xtensa_format_get_slot, xtensa_format_set_slot, xtensa_opcode_decode,
xtensa_opcode_encode, xtensa_opcode_is_branch, xtensa_opcode_is_jump,
xtensa_opcode_is_loop, xtensa_opcode_is_call,
xtensa_opcode_num_operands, xtensa_opcode_num_stateOperands,
xtensa_opcode_num_interfaceOperands, xtensa_opcode_num_funcUnit_uses,
xtensa_opcode_funcUnit_use, xtensa_operand_name,
xtensa_operand_is_visible, xtensa_operand_is_register,
xtensa_operand_regfile, xtensa_operand_num_regs,
xtensa_operand_is_known_reg, xtensa_operand_is_PCrelative,
xtensa_stateOperand_state, xtensa_stateOperand_inout,
xtensa_interfaceOperand_interface, xtensa_regfile_lookup,
xtensa_regfile_lookup_shortname, xtensa_regfile_name,
xtensa_regfile_shortname, xtensa_regfile_view_parent,
xtensa_regfile_num_bits, xtensa_regfile_num_entries,
xtensa_state_lookup, xtensa_state_name, xtensa_state_num_bits,
xtensa_state_is_exported, xtensa_sysreg_lookup,
xtensa_sysreg_lookup_name, xtensa_sysreg_name, xtensa_sysreg_number,
xtensa_sysreg_is_user, xtensa_interface_lookup, xtensa_interface_name,
xtensa_interface_num_bits, xtensa_interface_inout,
xtensa_interface_has_side_effect, xtensa_funcUnit_lookup,
xtensa_funcUnit_name, xtensa_funcUnit_num_copies): New prototypes.
* elf/xtensa.h (R_XTENSA_DIFF8, R_XTENSA_DIFF16, R_XTENSA_DIFF32,
R_XTENSA_SLOT*_OP, R_XTENSA_SLOT*_ALT): New relocations.
(XTENSA_PROP_SEC_NAME): Define.
(property_table_entry): Add flags field.
(XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define.
ld ChangeLog
* ld.texinfo (Xtensa): Describe new linker relaxation to optimize
assembler-generated longcall sequences. Describe new --size-opt
option.
* emulparams/elf32xtensa.sh (OTHER_SECTIONS): Add .xt.prop section.
* emultempl/xtensaelf.em (remove_section,
replace_insn_sec_with_prop_sec, replace_instruction_table_sections,
elf_xtensa_after_open): New.
(OPTION_OPT_SIZEOPT, OPTION_LITERAL_MOVEMENT,
OPTION_NO_LITERAL_MOVEMENT): Define.
(elf32xtensa_size_opt, elf32xtensa_no_literal_movement): New globals.
(PARSE_AND_LIST_LONGOPTS): Add size-opt and [no-]literal-movement.
(PARSE_AND_LIST_OPTIONS): Add --size-opt.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_OPT_SIZEOPT,
OPTION_LITERAL_MOVEMENT, and OPTION_NO_LITERAL_MOVEMENT.
(LDEMUL_AFTER_OPEN): Set to elf_xtensa_after_open.
* scripttempl/elfxtensa.sc: Update with changes from elf.sc.
* Makefile.am (eelf32xtensa.c): Update dependencies.
* Makefile.in: Regenerate.
ld/testsuite ChangeLog
* ld-xtensa/lcall1.s: Use .literal directive.
* ld-xtensa/lcall2.s: Align function entry.
* ld-xtensa/coalesce2.s: Likewise.
opcodes ChangeLog
* xtensa-dis.c (state_names): Delete.
(fetch_data): Use xtensa_isa_maxlength.
(print_xtensa_operand): Replace operand parameter with opcode/operand
pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
(print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
instruction bundles. Use xmalloc instead of malloc.
to build the second and third fixups for a composite relocation.
(macro_read_relocs): New function.
(macro_build): Use it.
(s_cpsetup): Pass all three composite relocation codes to macro_build.
Simplify fragging code accordingly.
(s_gpdword): Use fix_new rather than fix_new_exp for the second part
of the composite relocation. Set fx_tcbit in both fixups.
* configure.in (bfd_elf32_bigarm_symbian_vec): Add it.
(bfd_elf32_littlearm_symbian_vec): Likewise.
* configure: Regenerated.
* elf-bfd.h (elf_backend_data): Add dynamic_sec_flags.
* elf32-arm.h (PLT_HEADER_SIZE): Do not define.
(PLT_ENTRY_SIZE): Likewise.
(bfd_vma_elf32_arm_symbian_plt_entry): New
variable.
(elf32_arm_link_hash_table): Add plt_header_size, plt_entry_size,
and symbian_p.
(create_got_section): Don't create sections when generating BPABI
objects.
(elf32_arm_create_dynamic_sections): Tidy.
(elf32_arm_link_hash_table_create): Set plt_header_size,
plt_entry_size, and symbian_p.
(elf32_arm_check_relocs): Do not mark .rel.dyn as loadable when
generating BPABI objects.
(allocate_dynrelocs): Use htab->plt_header_size, not
PLT_HEADER_SIZE. Do not add to .got.plt when
generating BPABI objects.
(elf32_arm_finish_dynamic_symbol): Generate Symbian OS PLTs.
* elfarm-nabi.c: Add SymbianOS target vectors.
* elflink.c (_bfd_elf_create_got_section): Use dynamic_sec_flags.
(_bfd_elf_link_create_dynamic_sections): Likewise.
* elfxx-target.h (ELF_DYNAMIC_SEC_FLAGS): New macro.
(elfNN_bed): Use it.
* targets.c (bfd_elf32_bigarm_symbian_vec): New variable.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(_bfd_target_vector): Add them.
* Makefile.am (TARG_ENV_HFILES): Add te-symbian.h.
* Makefile.in: Regenerated.
* configure.in: Set em for arm*-*-symbianelf*.
* configure: Regenerated.
* config/tc-arm.c (elf32_arm_target_format): Use Symbian target
vectors when appropriate.
* config/te-symbian.h: New file.
* Makefile.am (ALL_EMULATIONS): Add earmsymbian.o.
(earmsymbian.c): New target.
* configure.tgt: Use armsymbian emulation for arm*-*-symbianelf*.
* Makefile.in: Regenerated.
* aclocal.m4: Likewise.
* configure: Likewise.
* emulparams/armsymbian.sh: New file.
argument, don't do anything if current section is not
.gnu.linkonce.t.* and linkonce_empty is set.
(generate_unwind_image, dot_endp): Adjust callers, call
start_unwind_section (*, 1) if nothing will be put into the
section.
* config.bfd (hppa*-*-netbsd*): Set targ_defvec to
bfd_elf32_hppa_nbsd_vec. Add bfd_elf32_hppa_linux_vec
to targ_selvecs.
* configure.in (bfd_elf32_hppa_nbsd_vec): Add case.
* configure: Regenerate.
* elf32-hppa.c (elf32_hppa_object_p): Add "elf32-hppa-netbsd"
case that accepts OSABI=NetBSD and OSABI=SysV.
(elf32_hppa_set_gp): For "elf32-hppa-netbsd", set the GP to
the base of .got or .data (if .got does not exist).
(elf32_hppa_post_process_headers): For elf32-hppa-netbsd,
set OSABI=NetBSD.
(TARGET_BIG_SYM): Add bfd_elf32_hppa_nbsd_vec case.
(TARGET_BIG_NAME): Add "elf32-hppa-netbsd" case.
* targets.c (bfd_elf32_hppa_nbsd_vec): Add extern declaration.
(_bfd_target_vector): Add bfd_elf32_hppa_nbsd_vec.
gas:
* config/tc-hppa.h (TARGET_FORMAT): Set to "elf32-hppa-netbsd"
for TE_NetBSD.
ld:
* emulparams/hppanbsd.sh (OUTPUT_FORMAT): Set to "elf32-hppa-netbsd".
2004-07-26 H.J. Lu <hongjiu.lu@intel.com>
* elf-bfd.h (bfd_elf_section_data): Add a pointer for the
linked-to section.
(elf_linked_to_section): New.
* elf.c (assign_section_numbers): Set up sh_link for
SHF_LINK_ORDER.
* elfxx-ia64.c (elfNN_ia64_final_write_processing): Set sh_info
to sh_link for SHT_IA_64_UNWIND sections.
gas/
2004-07-26 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-ia64.c (start_unwind_section): Set the linked-to
section.
(ia64_elf_section_change_hook): Set the linked-to section for
SHT_IA_64_UNWIND.
no associated relocation.
(mips_ip): Cancel the expression after use for the Q format
specifier.
(parse_relocation): Return no relocation for unsupported
operators.
(my_getSmallExpression): Return no relocation if no relocation
operators are used.
bfd:
* elf32-sh.c: Include ../opcodes/sh-opc.h .
* Makefile.am: Ran make dep-am .
* Makefile.in: Ran make dep-in .
gas:
* config/tc-sh.c (md_assemble): Change isspace to ISSPACE.
(md_parse_option): Remove redundant -isa testing.
Make bfd_arch variable const.
(md_show_usage): Make bfd_arch variable const.
* bfd/cofflink.c (_bfd_coff_generic_relocate_section): Resolve PE weak
externals properly.
* src/gas/config/obj-coff.c (obj_coff_weak): New .weak syntax for PE weak
externals.
* binutils/doc/binutils.texi (nm): Clarify weak symbol description.
* gas/config/tc-i386.c (tc_gen_reloc): Use addend for weak symbols in TE_PE.
* gas/doc/as.texinfo (Weak): Document PE weak symbols.
* ld/ld.texinfo (WIN32): Document PE weak symbols.
(reloc_needs_lo_p): Only return true if HAVE_IN_PLACE_ADDENDS.
(mips_frob_file): Rework so that only a single pass through the
relocs is needed. Allow %lo()s to have higher offsets than their
corresponding %hi()s or %got()s.
testsuite/
* gas/mips/elf{,el}-rel.d: Adjust so that the earliest %hi() matches
the earliest %lo().
* gas/mips/elf-rel11.d: Don't expect the relocs to be reordered.
* gas/mips/elf-rel20.[sd]: New test.
* gas/mips/mips.exp: Run it.
bfd:
* Makefile.am: Regenerate dependencies.
* Makefile.in: Regenerate.
* archures.c: Add bfd_mach_sh3_nommu .
* bfd-in2.h: Regenerate.
* cpu-sh.c: Add sh3-nommu architecture.
(bfd_to_arch_table): Create new table.
(sh_get_arch_from_bfd_mach): Create new function.
(sh_get_arch_up_from_bfd_mach): Create new function.
(sh_merge_bfd_arch): Create new function.
* elf32-sh.c (sh_ef_bfd_table): Add table.
(sh_elf_check_relocs): Replace switch statement with
use of sh_ef_bfd_table .
(sh_elf_get_flags_from_mach): Add new function.
(sh_find_elf_flags): Likewise.
(sh_elf_copy_private_data): Replace most of non-elf contents
with a call to sh_merge_bfd_arch() .
gas:
* Makefile.am: Regenerate dependecies.
* Makefile.in: Regenerate.
* config/tc-sh.c (valid_arch): Make unsigned.
(preset_target_arch): Likewise.
(md_begin): Use new architecture flags system.
(get_specific): Likewise.
(assemble_ppi): Likewise.
(md_assemble): Likewise. Also fix error check for bad opcodes.
(md_parse_option): Likewise. Also generate -isa values according
to the table in bfd/cpu-sh.c instead of just constants. Also
allow <arch>-up ISA variants.
(sh_elf_final_processing): Replace if-else chain with a call to
sh_find_elf_flags().
* testsuite/gas/sh/arch: New directory.
* testsuite/gas/sh/arch/arch.exp: New test script.
* testsuite/gas/sh/arch/arch_expected.txt: New file.
* testsuite/gas/sh/arch/sh.s: New file.
* testsuite/gas/sh/arch/sh2.s: New file.
* testsuite/gas/sh/arch/sh-dsp.s: New file.
* testsuite/gas/sh/arch/sh2e.s: New file.
* testsuite/gas/sh/arch/sh3-nommu.s: New file.
* testsuite/gas/sh/arch/sh3.s: New file.
* testsuite/gas/sh/arch/sh3-dsp.s: New file.
* testsuite/gas/sh/arch/sh3e.s: New file.
* testsuite/gas/sh/arch/sh4-nommu-nofpu.s: New file.
* testsuite/gas/sh/arch/sh4-nofpu.s: New file.
* testsuite/gas/sh/arch/sh4.s: New file.
* testsuite/gas/sh/arch/sh4a-nofpu.s: New file.
* testsuite/gas/sh/arch/sh4al-dsp.s: New file.
* testsuite/gas/sh/arch/sh4a.s: New file.
include/elf:
* sh.h (EF_SH_HAS_DSP): Remove.
(EF_SH_HAS_FP): Remove.
(EF_SH_MERGE_MACH): Remove.
(EF_SH4_NOFPU): Convert to decimal.
(EF_SH4A_NOFPU): Likewise.
(EF_SH4_NOMMU_NOFPU): Likewise.
(EF_SH3_NOMMU): Add new macro.
(EF_SH_BFD_TABLE): Likewise.
(sh_find_elf_flags): Add prototype.
(sh_elf_get_flags_from_mach): Likewise.
opcodes:
* sh-dis.c (target_arch): Make unsigned.
(print_insn_sh): Replace (most of) switch with a call to
sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
* sh-opc.h: Redefine architecture flags values.
Add sh3-nommu architecture.
Reorganise <arch>_up macros so they make more visual sense.
(SH_MERGE_ARCH_SET): Define new macro.
(SH_VALID_BASE_ARCH_SET): Likewise.
(SH_VALID_MMU_ARCH_SET): Likewise.
(SH_VALID_CO_ARCH_SET): Likewise.
(SH_VALID_ARCH_SET): Likewise.
(SH_MERGE_ARCH_SET_VALID): Likewise.
(SH_ARCH_SET_HAS_FPU): Likewise.
(SH_ARCH_SET_HAS_DSP): Likewise.
(SH_ARCH_UNKNOWN_ARCH): Likewise.
(sh_get_arch_from_bfd_mach): Add prototype.
(sh_get_arch_up_from_bfd_mach): Likewise.
(sh_get_bfd_mach_from_arch_set): Likewise.
(sh_merge_bfd_arc): Likewise.
ld:
* testsuite/ld-sh/arch/arch.exp: New test script.
* testsuite/ld-sh/arch/arch_expected.txt: New file.
* testsuite/ld-sh/arch/sh.s: New file.
* testsuite/ld-sh/arch/sh2.s: New file.
* testsuite/ld-sh/arch/sh-dsp.s: New file.
* testsuite/ld-sh/arch/sh2e.s: New file.
* testsuite/ld-sh/arch/sh3-nommu.s: New file.
* testsuite/ld-sh/arch/sh3.s: New file.
* testsuite/ld-sh/arch/sh3-dsp.s: New file.
* testsuite/ld-sh/arch/sh3e.s: New file.
* testsuite/ld-sh/arch/sh4-nommu-nofpu.s: New file.
* testsuite/ld-sh/arch/sh4-nofpu.s: New file.
* testsuite/ld-sh/arch/sh4.s: New file.
* testsuite/ld-sh/arch/sh4a-nofpu.s: New file.
* testsuite/ld-sh/arch/sh4al-dsp.s: New file.
* testsuite/ld-sh/arch/sh4a.s: New file.
