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2005-01-31  Jan Beulich  <jbeulich@novell.com>

	* config/tc-ia64.c (parse_operands): Also handle alloc without first
	input being ar.pfs.

gas/testsuite/
2005-01-31  Jan Beulich  <jbeulich@novell.com>

	* gas/ia64/pseudo.[ds]: New.
	* gas/ia64/ia64.exp: Run new test.

opcodes/
2005-01-31  Jan Beulich  <jbeulich@novell.com>

	* ia64-gen.c (NELEMS): Define.
	(shrink): Generate alias with missing second predicate register when
	opcode has two outputs and these are both predicates.
	* ia64-opc-i.c (FULL17): Define.
	(ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
	here to generate output template.
	(TBITCM, TNATCM): Undefine after use.
	* ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
	first input. Add ld16 aliases without ar.csd as second output. Add
	st16 aliases without ar.csd as second input. Add cmpxchg aliases
	without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
	ar.ccv as third/fourth inputs. Consolidate through...
	(CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
	CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
	* ia64-asmtab.c: Regenerate.
This commit is contained in:
Jan Beulich 2005-01-31 08:48:32 +00:00
parent e901b190a9
commit 60b9a61772
11 changed files with 6085 additions and 4996 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
gas/ChangeLog
View file

@ -1,3 +1,8 @@
2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (parse_operands): Also handle alloc without first
input being ar.pfs.
2005-01-28 Christian Groessler <chris@groessler.org>
* config/tc-z8k.c (md_assemble): Improve error detection.

34
gas/config/tc-ia64.c
View file

@ -5782,7 +5782,8 @@ parse_operands (idesc)
assert (strlen (idesc->name) <= 128);
strcpy (mnemonic, idesc->name);
if (idesc->operands[2] == IA64_OPND_SOF)
if (idesc->operands[2] == IA64_OPND_SOF
|| idesc->operands[1] == IA64_OPND_SOF)
{
/* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
can't parse the first operand until we have parsed the
@ -5825,20 +5826,23 @@ parse_operands (idesc)
return 0;
}
if (idesc->operands[2] == IA64_OPND_SOF)
if (idesc->operands[2] == IA64_OPND_SOF
|| idesc->operands[1] == IA64_OPND_SOF)
{
/* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
know (strcmp (idesc->name, "alloc") == 0);
if (num_operands == 5 /* first_arg not included in this count! */
&& CURR_SLOT.opnd[2].X_op == O_constant
&& CURR_SLOT.opnd[3].X_op == O_constant
&& CURR_SLOT.opnd[4].X_op == O_constant
&& CURR_SLOT.opnd[5].X_op == O_constant)
i = (CURR_SLOT.opnd[1].X_op == O_register
&& CURR_SLOT.opnd[1].X_add_number == REG_AR + AR_PFS) ? 2 : 1;
if (num_operands == i + 3 /* first_arg not included in this count! */
&& CURR_SLOT.opnd[i].X_op == O_constant
&& CURR_SLOT.opnd[i + 1].X_op == O_constant
&& CURR_SLOT.opnd[i + 2].X_op == O_constant
&& CURR_SLOT.opnd[i + 3].X_op == O_constant)
{
sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
CURR_SLOT.opnd[3].X_add_number,
CURR_SLOT.opnd[4].X_add_number,
CURR_SLOT.opnd[5].X_add_number);
sof = set_regstack (CURR_SLOT.opnd[i].X_add_number,
CURR_SLOT.opnd[i + 1].X_add_number,
CURR_SLOT.opnd[i + 2].X_add_number,
CURR_SLOT.opnd[i + 3].X_add_number);
/* now we can parse the first arg: */
saved_input_pointer = input_line_pointer;
@ -5848,10 +5852,10 @@ parse_operands (idesc)
--num_outputs; /* force error */
input_line_pointer = saved_input_pointer;
CURR_SLOT.opnd[2].X_add_number = sof;
CURR_SLOT.opnd[3].X_add_number
= sof - CURR_SLOT.opnd[4].X_add_number;
CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
CURR_SLOT.opnd[i].X_add_number = sof;
CURR_SLOT.opnd[i + 1].X_add_number
= sof - CURR_SLOT.opnd[i + 2].X_add_number;
CURR_SLOT.opnd[i + 2] = CURR_SLOT.opnd[i + 3];
}
}

5
gas/testsuite/ChangeLog
View file

@ -1,3 +1,8 @@
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/pseudo.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
2005-01-27 Jan Beulich <jbeulich@novell.com>
* gas/ia64/nop_x.[ds]: New.

1
gas/testsuite/gas/ia64/ia64.exp
View file

@ -24,6 +24,7 @@ if [istarget "ia64-*"] then {
run_dump_test "opc-i"
run_dump_test "opc-m"
run_dump_test "opc-x"
run_dump_test "pseudo"
run_dump_test "nop_x"
run_dump_test "mov-ar"

26
gas/testsuite/gas/ia64/pseudo.d Normal file
View file

@ -0,0 +1,26 @@
# objdump: -d
# name: ia64 pseudo-ops
.*: +file format .*
Disassembly of section \.text:
0+0 <_start>:
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+alloc r8=ar\.pfs,0,0,0
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+cmp\.eq p6,p0=r0,r0
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+cmp\.eq p7,p0=0,r0
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+cmp4\.eq p8,p0=r0,r0
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+nop\.. 0x0
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+cmp4\.eq p9,p0=0,r0
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+cmp8xchg16\.acq r9=\[r0\],r0,ar\.csd,ar\.ccv
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+cmpxchg4\.acq r10=\[r0\],r0,ar\.ccv
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+fclass\.m p10,p0=f0,0x1
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+nop\.. 0x0
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+fcmp\.eq\.s0 p11,p0=f0,f0
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+nop\.. 0x0
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+ld16 r11,ar\.csd=\[r0\]
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+nop\.. 0x0
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+mov pr=r0,0xfffffffffffffffe
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+st16 \[r0\]=r0,ar\.csd
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+tbit\.z p0,p12=r0,0
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+tnat\.z p0,p13=r0(;;)?

15
gas/testsuite/gas/ia64/pseudo.s Normal file
View file

@ -0,0 +1,15 @@
_start:
alloc r8 = 0, 0, 0, 0
cmp.eq p6 = r0, r0
cmp.eq p7 = 0, r0
cmp4.eq p8 = r0, r0
cmp4.eq p9 = 0, r0
cmp8xchg16.acq r9 = [r0], r0
cmpxchg4.acq r10 = [r0], r0
fclass.m p10 = f0, @pos
fcmp.eq p11 = f0, f0
ld16 r11 = [r0]
mov pr = r0
st16 [r0] = r0
tbit.nz p12 = r0, 0
tnat.nz p13 = r0

18
opcodes/ChangeLog
View file

@ -1,3 +1,21 @@
2005-01-31 Jan Beulich <jbeulich@novell.com>
* ia64-gen.c (NELEMS): Define.
(shrink): Generate alias with missing second predicate register when
opcode has two outputs and these are both predicates.
* ia64-opc-i.c (FULL17): Define.
(ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
here to generate output template.
(TBITCM, TNATCM): Undefine after use.
* ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
first input. Add ld16 aliases without ar.csd as second output. Add
st16 aliases without ar.csd as second input. Add cmpxchg aliases
without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
ar.ccv as third/fourth inputs. Consolidate through...
(CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
* ia64-asmtab.c: Regenerate.
2005-01-27 Andrew Cagney <cagney@gnu.org>
* configure: Regenerate to track ../gettext.m4 change.

10868
opcodes/ia64-asmtab.c
View file

File diff suppressed because it is too large Load diff

22
opcodes/ia64-gen.c
View file

@ -56,6 +56,7 @@
const char * program_name = NULL;
int debug = 0;
#define NELEMS(a) (sizeof (a) / sizeof ((a)[0]))
#define tmalloc(X) (X *) xmalloc (sizeof (X))
/* The main opcode table entry. Each entry is a unique combination of
@ -2725,7 +2726,26 @@ shrink (table)
int curr_opcode;
for (curr_opcode = 0; table[curr_opcode].name != NULL; curr_opcode++)
add_opcode_entry (table + curr_opcode);
{
add_opcode_entry (table + curr_opcode);
if (table[curr_opcode].num_outputs == 2
&& ((table[curr_opcode].operands[0] == IA64_OPND_P1
&& table[curr_opcode].operands[1] == IA64_OPND_P2)
|| (table[curr_opcode].operands[0] == IA64_OPND_P2
&& table[curr_opcode].operands[1] == IA64_OPND_P1)))
{
struct ia64_opcode *alias = tmalloc(struct ia64_opcode);
unsigned i;
*alias = table[curr_opcode];
for (i = 2; i < NELEMS (alias->operands); ++i)
alias->operands[i - 1] = alias->operands[i];
alias->operands[NELEMS (alias->operands) - 1] = IA64_OPND_NIL;
--alias->num_outputs;
alias->flags |= PSEUDO;
add_opcode_entry (alias);
}
}
}

6
opcodes/ia64-opc-i.c
View file

@ -95,6 +95,8 @@
(bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \
(mOp | mX3 | mXb | mIh | mWh | mTag13)
#define FULL17 ((ia64_insn)0x10ff001fc0LL)
/* Used to initialise unused fields in ia64_opcode struct,
in order to stop gcc from complaining. */
#define EMPTY 0,0,NULL
@ -126,6 +128,8 @@ struct ia64_opcode ia64_opcodes_i[] =
#undef MOV
{"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY},
{"mov", I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY},
/* Don't remove one of the seemingly redundant FULL17-s. */
{"mov", I, FULL17 | OpX3 (0, 3) | FULL17, {PR, R2}, PSEUDO, 0, NULL},
{"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}, EMPTY},
{"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY},
{"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY},
@ -181,6 +185,7 @@ struct ia64_opcode ia64_opcodes_i[] =
{"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)},
{"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)},
#undef TBIT
#undef TBITCM
#define TNAT(a,b,c,d) \
I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY
#define TNATCM(a,b,c,d) \
@ -202,6 +207,7 @@ struct ia64_opcode ia64_opcodes_i[] =
{"tnat.nz.or.andcm", TNAT (1, 1, 1, 1)},
{"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)},
#undef TNAT
#undef TNATCM
{"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}, EMPTY},
{"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}, EMPTY},

81
opcodes/ia64-opc-m.c
View file

@ -110,6 +110,7 @@ struct ia64_opcode ia64_opcodes_m[] =
{"mov", M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV, 0, NULL},
{"alloc", M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|MOD_RRBS, 0, NULL},
{"alloc", M, OpX3 (1, 6), {R1, SOF, SOL, SOR}, PSEUDO|FIRST|NO_PRED|MOD_RRBS, 0, NULL},
{"mov", M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV, 0, NULL},
{"mov", M, OpX3X6b (1, 0, 0x29), {PSR_UM, R2}, EMPTY},
@ -176,8 +177,11 @@ struct ia64_opcode ia64_opcodes_m[] =
{"ld8.nt1", M, OpMXX6aHint (4, 0, 0, 0x03, 1), {R1, MR3}, EMPTY},
{"ld8.nta", M, OpMXX6aHint (4, 0, 0, 0x03, 3), {R1, MR3}, EMPTY},
{"ld16", M2, OpMXX6aHint (4, 0, 1, 0x28, 0), {R1, AR_CSD, MR3}, EMPTY},
{"ld16", M, OpMXX6aHint (4, 0, 1, 0x28, 0), {R1, MR3}, PSEUDO, 0, NULL},
{"ld16.nt1", M2, OpMXX6aHint (4, 0, 1, 0x28, 1), {R1, AR_CSD, MR3}, EMPTY},
{"ld16.nt1", M, OpMXX6aHint (4, 0, 1, 0x28, 1), {R1, MR3}, PSEUDO, 0, NULL},
{"ld16.nta", M2, OpMXX6aHint (4, 0, 1, 0x28, 3), {R1, AR_CSD, MR3}, EMPTY},
{"ld16.nta", M, OpMXX6aHint (4, 0, 1, 0x28, 3), {R1, MR3}, PSEUDO, 0, NULL},
{"ld1.s", M, OpMXX6aHint (4, 0, 0, 0x04, 0), {R1, MR3}, EMPTY},
{"ld1.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x04, 1), {R1, MR3}, EMPTY},
{"ld1.s.nta", M, OpMXX6aHint (4, 0, 0, 0x04, 3), {R1, MR3}, EMPTY},
@ -239,8 +243,11 @@ struct ia64_opcode ia64_opcodes_m[] =
{"ld8.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x17, 1), {R1, MR3}, EMPTY},
{"ld8.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x17, 3), {R1, MR3}, EMPTY},
{"ld16.acq", M2, OpMXX6aHint (4, 0, 1, 0x2c, 0), {R1, AR_CSD, MR3}, EMPTY},
{"ld16.acq", M, OpMXX6aHint (4, 0, 1, 0x2c, 0), {R1, MR3}, PSEUDO, 0, NULL},
{"ld16.acq.nt1", M2, OpMXX6aHint (4, 0, 1, 0x2c, 1), {R1, AR_CSD, MR3}, EMPTY},
{"ld16.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x2c, 1), {R1, MR3}, PSEUDO, 0, NULL},
{"ld16.acq.nta", M2, OpMXX6aHint (4, 0, 1, 0x2c, 3), {R1, AR_CSD, MR3}, EMPTY},
{"ld16.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x2c, 3), {R1, MR3}, PSEUDO, 0, NULL},
{"ld8.fill", M, OpMXX6aHint (4, 0, 0, 0x1b, 0), {R1, MR3}, EMPTY},
{"ld8.fill.nt1", M, OpMXX6aHint (4, 0, 0, 0x1b, 1), {R1, MR3}, EMPTY},
{"ld8.fill.nta", M, OpMXX6aHint (4, 0, 0, 0x1b, 3), {R1, MR3}, EMPTY},
@ -409,7 +416,9 @@ struct ia64_opcode ia64_opcodes_m[] =
{"st8", M, OpMXX6aHint (4, 0, 0, 0x33, 0), {MR3, R2}, EMPTY},
{"st8.nta", M, OpMXX6aHint (4, 0, 0, 0x33, 3), {MR3, R2}, EMPTY},
{"st16", M, OpMXX6aHint (4, 0, 1, 0x30, 0), {MR3, R2, AR_CSD}, EMPTY},
{"st16", M, OpMXX6aHint (4, 0, 1, 0x30, 0), {MR3, R2}, PSEUDO, 0, NULL},
{"st16.nta", M, OpMXX6aHint (4, 0, 1, 0x30, 3), {MR3, R2, AR_CSD}, EMPTY},
{"st16.nta", M, OpMXX6aHint (4, 0, 1, 0x30, 3), {MR3, R2}, PSEUDO, 0, NULL},
{"st1.rel", M, OpMXX6aHint (4, 0, 0, 0x34, 0), {MR3, R2}, EMPTY},
{"st1.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x34, 3), {MR3, R2}, EMPTY},
{"st2.rel", M, OpMXX6aHint (4, 0, 0, 0x35, 0), {MR3, R2}, EMPTY},
@ -419,44 +428,56 @@ struct ia64_opcode ia64_opcodes_m[] =
{"st8.rel", M, OpMXX6aHint (4, 0, 0, 0x37, 0), {MR3, R2}, EMPTY},
{"st8.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x37, 3), {MR3, R2}, EMPTY},
{"st16.rel", M, OpMXX6aHint (4, 0, 1, 0x34, 0), {MR3, R2, AR_CSD}, EMPTY},
{"st16.rel", M, OpMXX6aHint (4, 0, 1, 0x34, 0), {MR3, R2}, PSEUDO, 0, NULL},
{"st16.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x34, 3), {MR3, R2, AR_CSD}, EMPTY},
{"st16.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x34, 3), {MR3, R2}, PSEUDO, 0, NULL},
{"st8.spill", M, OpMXX6aHint (4, 0, 0, 0x3b, 0), {MR3, R2}, EMPTY},
{"st8.spill.nta", M, OpMXX6aHint (4, 0, 0, 0x3b, 3), {MR3, R2}, EMPTY},
#define CMPXCHG(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV}, EMPTY
#define CMPXCHG_P(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2}, PSEUDO, 0, NULL
#define CMPXCHG16(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CSD, AR_CCV}, EMPTY
{"cmpxchg1.acq", CMPXCHG (0x00, 0)},
{"cmpxchg1.acq.nt1", CMPXCHG (0x00, 1)},
{"cmpxchg1.acq.nta", CMPXCHG (0x00, 3)},
{"cmpxchg2.acq", CMPXCHG (0x01, 0)},
{"cmpxchg2.acq.nt1", CMPXCHG (0x01, 1)},
{"cmpxchg2.acq.nta", CMPXCHG (0x01, 3)},
{"cmpxchg4.acq", CMPXCHG (0x02, 0)},
{"cmpxchg4.acq.nt1", CMPXCHG (0x02, 1)},
{"cmpxchg4.acq.nta", CMPXCHG (0x02, 3)},
{"cmpxchg8.acq", CMPXCHG (0x03, 0)},
{"cmpxchg8.acq.nt1", CMPXCHG (0x03, 1)},
{"cmpxchg8.acq.nta", CMPXCHG (0x03, 3)},
{"cmp8xchg16.acq", CMPXCHG16 (0x20, 0)},
{"cmp8xchg16.acq.nt1", CMPXCHG16 (0x20, 1)},
{"cmp8xchg16.acq.nta", CMPXCHG16 (0x20, 3)},
{"cmpxchg1.rel", CMPXCHG (0x04, 0)},
{"cmpxchg1.rel.nt1", CMPXCHG (0x04, 1)},
{"cmpxchg1.rel.nta", CMPXCHG (0x04, 3)},
{"cmpxchg2.rel", CMPXCHG (0x05, 0)},
{"cmpxchg2.rel.nt1", CMPXCHG (0x05, 1)},
{"cmpxchg2.rel.nta", CMPXCHG (0x05, 3)},
{"cmpxchg4.rel", CMPXCHG (0x06, 0)},
{"cmpxchg4.rel.nt1", CMPXCHG (0x06, 1)},
{"cmpxchg4.rel.nta", CMPXCHG (0x06, 3)},
{"cmpxchg8.rel", CMPXCHG (0x07, 0)},
{"cmpxchg8.rel.nt1", CMPXCHG (0x07, 1)},
{"cmpxchg8.rel.nta", CMPXCHG (0x07, 3)},
{"cmp8xchg16.rel", CMPXCHG16 (0x24, 0)},
{"cmp8xchg16.rel.nt1", CMPXCHG16 (0x24, 1)},
{"cmp8xchg16.rel.nta", CMPXCHG16 (0x24, 3)},
#define CMPXCHG16_P(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2}, PSEUDO, 0, NULL
#define CMPXCHG_acq 0
#define CMPXCHG_rel 4
#define CMPXCHG_1 0
#define CMPXCHG_2 1
#define CMPXCHG_4 2
#define CMPXCHG_8 3
#define CMPXCHGn(n, s) \
{"cmpxchg"#n"."#s, CMPXCHG (CMPXCHG_##n|CMPXCHG_##s, 0)}, \
{"cmpxchg"#n"."#s, CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 0)}, \
{"cmpxchg"#n"."#s".nt1", CMPXCHG (CMPXCHG_##n|CMPXCHG_##s, 1)}, \
{"cmpxchg"#n"."#s".nt1", CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 1)}, \
{"cmpxchg"#n"."#s".nta", CMPXCHG (CMPXCHG_##n|CMPXCHG_##s, 3)}, \
{"cmpxchg"#n"."#s".nta", CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 3)}
#define CMP8XCHG16(s) \
{"cmp8xchg16."#s, CMPXCHG16 (0x20|CMPXCHG_##s, 0)}, \
{"cmp8xchg16."#s, CMPXCHG16_P (0x20|CMPXCHG_##s, 0)}, \
{"cmp8xchg16."#s".nt1", CMPXCHG16 (0x20|CMPXCHG_##s, 1)}, \
{"cmp8xchg16."#s".nt1", CMPXCHG16_P (0x20|CMPXCHG_##s, 1)}, \
{"cmp8xchg16."#s".nta", CMPXCHG16 (0x20|CMPXCHG_##s, 3)}, \
{"cmp8xchg16."#s".nta", CMPXCHG16_P (0x20|CMPXCHG_##s, 3)}
#define CMPXCHG_ALL(s) CMPXCHGn(1, s), \
CMPXCHGn(2, s), \
CMPXCHGn(4, s), \
CMPXCHGn(8, s), \
CMP8XCHG16(s)
CMPXCHG_ALL(acq),
CMPXCHG_ALL(rel),
#undef CMPXCHG
#undef CMPXCHG_P
#undef CMPXCHG16
#undef CMPXCHG16_P
#undef CMPXCHG_acq
#undef CMPXCHG_rel
#undef CMPXCHG_1
#undef CMPXCHG_2
#undef CMPXCHG_4
#undef CMPXCHG_8
#undef CMPXCHGn
#undef CMPXCHG16
#undef CMPXCHG_ALL
{"xchg1", M, OpMXX6aHint (4, 0, 1, 0x08, 0), {R1, MR3, R2}, EMPTY},
{"xchg1.nt1", M, OpMXX6aHint (4, 0, 1, 0x08, 1), {R1, MR3, R2}, EMPTY},
{"xchg1.nta", M, OpMXX6aHint (4, 0, 1, 0x08, 3), {R1, MR3, R2}, EMPTY},