Doug Evans committed the change above, but forgot to update one of
the callers of get_raw_print_options, at mt-tdep.c. This commit fixes
this.
2013-07-10 Sergio Durigan Junior <sergiodj@redhat.com>
* mt-tdep.c (mt_registers_info): Call
get_no_prettyformat_print_options instead of
get_raw_print_options (regression by last patch from Doug
Evans).
This patch adds some tests that evidence a regression fixed by
the following patch from Pedro Alves:
[PATCH] ada-lang.c:coerce_unspec_val_to_type: Preserve laziness
http://www.sourceware.org/ml/gdb-patches/2013-07/msg00178.html
gdb/testsuite/ChangeLog:
* gdb.ada/arrayptr/foo.adb: Add some code defining an access
to a packed array.
* gdb.ada/arrayptr.exp: Add a few tests using that new access
to packed array.
ada-lang.c:coerce_unspec_val_to_type does:
if (value_lazy (val)
|| TYPE_LENGTH (type) > TYPE_LENGTH (value_type (val)))
result = allocate_value_lazy (type);
else
{
result = allocate_value (type);
memcpy (value_contents_raw (result), value_contents (val),
TYPE_LENGTH (type));
}
set_value_component_location (result, val);
set_value_bitsize (result, value_bitsize (val));
set_value_bitpos (result, value_bitpos (val));
set_value_address (result, value_address (val));
set_value_optimized_out (result, value_optimized_out (val));
Notice that before value_optimized_out was made to auto-fetch lazy
values, VAL would end up still lazy if it was lazy on entry. It's not
really a problem here if VAL is lazy, and VAL->optimized_out is 0,
because RESULT is also left lazy. IOW, this just wants to copy the
VAL->optimized_out flag to RESULT->optimized_out, nothing else.
As a side-effect of the change in value_optimized_out, the following
testcase now regresses. Consider:
type Small is range -64 .. 63;
for Small'Size use 7;
type Arr is array (1..10) of Small;
pragma Pack (Arr);
type Arr_Ptr is access Arr;
An_Arr_Ptr : Arr_Ptr := new Arr'(10, 20, 30, 40, 50, 60, 62, 63,
-23, 42);
Trying to print one element of An_Arr_Ptr yields:
(gdb) p an_arr_ptr(3)
Cannot access memory at address 0x0
The patch adds the value_optimized_out_const function for that,
allowing us to avoid trying to fetch a value at a dummy address.
(I found this out by grepping for set_value_optimized_out and trying
to convert the uses I found to instead allocate the value with
allocate_optimized_out_value.)
Tested on x86_64 Fedora 17.
gdb/
2013-07-09 Pedro Alves <palves@redhat.com>
* ada-lang.c (coerce_unspec_val_to_type): Use
value_optimized_out_const.
* value.c (value_optimized_out_const): New function.
* value.h (value_optimized_out_const): New declaration.
If enough information is provided by the compiler, the debugger
now prints the entry value of various parameters:
(gdb) continue
Continuing.
Breakpoint 2, pck.call_me (w=w@entry=50) at [...]
20 Last_Word := W;
This patch adjusts the expected output to allow an optional
"w@entry=" in the parameter value.
gdb/testsuite/ChangeLog:
* gdb.ada/small_reg_param.exp: Accept optional entry value
for parameter "w".
Enum values rename as well. All uses updated.
* valprint.h (value_print_options): Rename member pretty to
pretty format. Rename member prettyprint_arrays to
prettyformat_arrays. Rename member prettyprint_structs to
prettyformat_structs. All uses updated.
(get_no_prettyformat_print_options): Renamed from
get_raw_print_options.
* valprint.c (get_no_prettyformat_print_options): Renamed from
get_raw_print_options. All callers updated.
(show_prettyformat_structs): Renamed from show_prettyprint_structs.
All callers updated.
(show_prettyformat_arrays): Renamed from show_prettyprint_arrays.
All callers updated.
(_initialize_valprint): Improve help text for "set print pretty" and
"set print arrays".
testsuite/
* gdb.base/default.exp: Update expected output of "show print array"
and "show print pretty".
2013-07-09 Tristan Gingold <gingold@adacore.com>
* configure.com: Add new defines to match changes in configure.
gas/
2013-07-09 Tristan Gingold <gingold@adacore.com>
* configure.com: Define HAVE_SYS_TYPES_H and HAVE_UNISTD_H
* hosts/alphavms.h: Include config.h and ansidecl.h, remove useless
macros.
* configure.com: Adjust to match changes in configure.
* makefile.vms (OBJS): Update list.
* config/tc-mips.c (mips_ip): Unconditionally parse an expression
for 'A' and assume that the constant has been elided if the result
is an O_register.
gas/testsuite/
* gas/mips/la.s, gas/mips/la.d, gas/mips/la-svr4pic.d,
gas/mips/la-xgot.d: Add tests for bracketed addresses.
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
(M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
(M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
(M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
(M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
(M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
(M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
(M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
(M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
(M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
(M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
(M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
(M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
Rename to...
(M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
(M_USD_AB): ...these.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
and SD A(B) macros up.
* micromips-opc.c (micromips_opcodes): Likewise.
gas/
* config/tc-mips.c (gprel16_reloc_p): New function.
(macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
BFD_RELOC_UNUSED.
(offset_high_part, small_offset_p): New functions.
(nacro): Use them. Remove *_OB and *_DOB cases. For single-
register load and store macros, handle the 16-bit offset case first.
If a 16-bit offset is not suitable for the instruction we're
generating, load it into the temporary register using
ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
M_L_DAB code once the address has been constructed. For double load
and store macros, again handle the 16-bit offset case first.
If the second register cannot be accessed from the same high
part as the first, load it into AT using ADDRESS_ADDI_INSN.
Fix the handling of LD in cases where the first register is the
same as the base. Also handle the case where the offset is
not 16 bits and the second register cannot be accessed from the
same high part as the first. For unaligned loads and stores,
fuse the offbits == 12 and old "ab" handling. Apply this handling
whenever the second offset needs a different high part from the first.
Construct the offset using ADDRESS_ADDI_INSN where possible,
for offbits == 16 as well as offbits == 12. Use offset_reloc
when constructing the individual loads and stores.
(mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
and offset_reloc before matching against a particular opcode.
Handle elided 'A' constants. Allow 'A' constants to use
relocation operators.
gas/testsuite/
* gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for
truncated constants.
* gas/mips/ldstla-32-shared.d: Likewise.
* gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding
16-bit constants to the base.
* gas/mips/micromips@mcu.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips.d, gas/mips/micromips-insn32.d,
gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise.
Allow the full 16-bit offset range to be used for SB, LB and LBU in
USH and ULH sequences. Fix the expected output for LD and SD when
the two LW and SW offsets need different high parts.
* gas/mips/eva.s: Test PREFE with relocation operators.
* gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit
constants. Update after eva.s change.
* gas/mips/micromips@eva.d: Likewise.
* gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s,
gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d,
gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s,
gas/mips/ulh-reloc.d: New tests.
* gas/mips/mips.exp: Run them.
* mips.h: Remove documentation of "[" and "]". Update documentation
of "k" and the MDMX formats.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
MDMX-like instructions.
* mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
printing "Q" operands for INSN_5400 instructions.
gas/
* config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
(mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
gas/testsuite/
* gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test.
* gas/mips/mips.exp: Run it.
* mips.h: Update documentation of "+s" and "+S".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
"+S" for "cins".
* mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
Combine cases.
gas/
* config/tc-mips.c (mips_ip): Preserve the real bit number for "+p".
Require the msb to be <= 31 for "+s". Check that the size is <= 31
for both "+s" and "+S".
* mips.h: Document "+i".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
"jalx".
* mips16-opc.c (mips16_opcodes): Likewise.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_mips16_insn_arg)
(print_insn_mips16): Handle "+i".
(print_insn_micromips): Likewise. Conditionally preserve the
ISA bit for "a" but not for "+i".
gas/
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
(mips_ip, mips16_ip): Handle "+i".
* mips.h: Remove documentation of "+D" and "+T".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
and "+T" handling. Check for a "0" suffix when deciding whether to
use coprocessor 0 names. In that case, also check for ",H" selectors.
gas/
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
(mips_ip): Remove "+D" and "+T" handling.
gas/testsuite/
* gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names
for LWC0 and SWC0.
ARM uses @ as a comment character, but % seems to be usable by all
existing ifunc enabled architectures.
gdb/testsuite/ChangeLog:
2013-07-05 Will Newton <will.newton@linaro.org>
* gdb.base/gnu-ifunc-lib.c: Use %function instead of @function
in asm syntax to allow building on ARM.
