More comments added.
(md_begin): Removed "construct symbols for each register name".
Because register names conflicts with GCC generated function
names.
(avr_operand): Now constant numbers can be used as a register
identifiers (0 as r0, 31 as r31).
(md_assemble): use skip_space () before parsing instruction
operands.
(md_assemble): Handle opcodes with optional operands (lpm,elpm).
(avr_operand): Handle 'a', 'v' and 'z' constraint letters needed
for `fmul', `movw' and `lpm R,Z' instructions.
(avr_operands): Warn if current opcode is a two-word instruction
and previous opcode was cpse/sbic/sbis/sbrc/sbrs.
(avr_opcodes): New commands added.
(REGISTER_P): Check 'a' and 'v' constraint letters.
(mcu_types): New MCU added.
bfd:
* Makefile.am (coff64-rs6000.lo): New rule.
* Makefile.in: Regenerate.
* coff-rs6000.c (xcoff_mkobject, xcoff_copy_private_bfd_data,
xcoff_is_local_label_name, xcoff_rtype2howto,
xcoff_reloc_type_lookup, xcoff_slurp_armap, xcoff_archive_p,
xcoff_read_ar_hdr, xcoff_openr_next_archived_file, xcoff_write_armap,
xcoff_write_archive_contents): No longer static, and prefix with _bfd_.
(NO_COFF_SYMBOLS): Define.
(xcoff64_swap_sym_in, xcoff64_swap_sym_out, xcoff64_swap_aux_in,
xcoff64_swap_aux_out): New functions; handle xcoff symbol tables
internally.
(MINUS_ONE): New macro.
(xcoff_howto_tabl, xcoff_reloc_type_lookup): Add 64 bit POS
relocation.
(coff_SWAP_sym_in, coff_SWAP_sym_out, coff_SWAP_aux_in,
coff_SWAP_aux_out): Map to the new functions.
* coff64-rs6000.c: New file.
* libcoff.h (bfd_coff_backend_data): Add new fields
_bfd_coff_force_symnames_in_strings and
_bfd_coff_debug_string_prefix_length.
(bfd_coff_force_symnames_in_strings,
bfd_coff_debug_string_prefix_length): New macros for above fields.
* coffcode.h (coff_set_arch_mach_hook): Handle XCOFF64 magic.
Set machine to 620 for XCOFF64. Use bfd_coff_swap_sym_in instead
of using coff_swap_sym_in directly.
(FORCE_SYMNAMES_IN_STRINGS): New macro, defined for XCOFF64.
(coff_set_flags) Set magic for XCOFF64.
(coff_compute_section_file_positions): Add symbol name length to
string section length if bfd_coff_debug_string_prefix_length is
true.
(coff_write_object_contents): Don't do reloc overflow for XCOFF64.
(coff_slurp_line_table): Use bfd_coff_swap_lineno_in instead of
using coff_swap_lineno_in directly.
(bfd_coff_backend_data): Add _bfd_coff_force_symnames_in_strings
and _bfd_coff_debug_string_prefix_length fields.
* coffgen.c (coff_fix_symbol_name, coff_write_symbols): Force
symbol names into strings table when
bfd_coff_force_symnames_in_strings is true.
* coffswap.h (MAX_SCNHDR_NRELOC, MAX_SCNHDR_NLNNO, GET_RELOC_VADDR,
SET_RELOC_VADDR): New macros.
(coff_swap_reloc_in, coff_swap_reloc_out): Use above macros.
(coff_swap_aux_in, coff_swap_aux_out): Remove RS6000COFF_C
code.
(coff_swap_aouthdr_in, coff_swap_aouthdr_out): Handle XCOFF64
changes within RS6000COFF_C specific code.
(coff_swap_scnhdr_out): Use PUT_SCNHDR_NLNNO, PUT_SCNHDR_NRELOC,
MAX_SCNHDR_NRELOC, and MAX_SCNHDR_NLNNO.
* reloc.c (bfd_perform_relocation, bfd_install_relocation):
Extend existing hack on target name.
* xcofflink.c (XCOFF_XVECP): Extend existing hack on
target name.
* coff-tic54x.c (ticof): Keep up to date with new fields
in bfd_coff_backend_data.
* config.bfd: Add bfd_powerpc_64_arch to targ_arch and define
targ_selvecs to include rs6000coff64_vec for rs6000.
* configure.in: Add rs6000coff64_vec case.
* cpu-powerpc.c: New bfd_arch_info_type.
gas:
* as.c (parse_args): Allow md_parse_option to override -a listing
option.
* config/obj-coff.c (add_lineno): Change type of offset parameter
from "int" to "bfd_vma."
* config/tc-ppc.c (md_pseudo_table): Add "llong" and "machine."
(ppc_mach, ppc_subseg_align, ppc_target_format): New.
(ppc_change_csect): Align correctly for XCOFF64.
(ppc_machine): New function, which discards "ppc_machine" line.
(ppc_tc): Cons for 8 when code is 64 bit.
(md_apply_fix3): Don't check operand->insert. Handle 64 bit
relocations.
(md_parse_option): Handle -a64 and -a32.
(ppc_xcoff64): New.
* config/tc-ppc.h (TARGET_MACH): Define.
(TARGET_FORMAT): Move to function.
(SUB_SEGMENT_ALIGN): Use ppc_subseg_align.
include:
* include/coff/rs6k64.h: New file.
opcodes:
* configure.in: Add bfd_powerpc_64_arch.
* disassemble.c (disassembler): Use print_insn_big_powerpc for
64 bit code.
* sh-opc.c (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs.
stc GBR,@-<REG_N> is available for arch_sh1_up.
Group parallel processing insn with identical mnemonics together.
Make three-operand psha / pshl come first.
gas:
* config/tc-sh.c (get_operands): There's no third operand if the
first operand is an immediate.
opcodes:
* sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4.
Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
(sh_arg_type): Add A_PC.
(sh_table): Update entries using immediates. Add repeat.
* sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4.
Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
gas:
* config/tc-sh.c (immediate): Delete.
(sh_operand_info): Add immediate member.
(parse_reg): Use A_PC for pc.
(parse_exp): Add second argument 'op'. All callers changed.
(parse_at): Expect pc to be coded as A_PC.
Use immediate field in *op.
(insert): Add fourth argument 'op'. All callers changed.
(build_relax): Add second argument 'op'. All callers changed.
(insert_loop_bounds): New function.
(build_Mytes): Remove DISP_4.
Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT.
(assemble_ppi): Use immediate field in *operand.
(sh_force_relocation): Handle BFD_RELOC_SH_LOOP_{START,END}.
(md_apply_fix): Likewise.
(tc_gen_reloc): Likewise. Check for a pcrel BFD_RELOC_SH_LABEL.
include/coff:
* sh.h (R_SH_LOOP_START, R_SH_LOOP_END): Define.
include/elf:
* sh.h (R_SH_LOOP_START, R_SH_LOOP_END): New RELOC_NUMBERs.
bfd:
* reloc.c (_bfd_relocate_contents): Add BFD_RELOC_SH_LOOP_START and
BFD_RELOC_SH_LOOP_END.
* elf32-sh.c (sh_elf_howto_tab): Change special_func to
sh_elf_ignore_reloc for all entries that sh_elf_reloc used to ignore.
Add entries for R_SH_LOOP_START and R_SH_LOOP_END.
(sh_elf_reloc_loop): New function.
(sh_elf_reloc): No need to test for always-to-be-ignored relocs
any more.
(sh_rel): Add entries for BFD_RELOC_SH_LOOP_{START,END}.
(sh_elf_relocate_section): Handle BFD_RELOC_SH_LOOP_{START,END}.
* bfd-in2.h, libbfd.h: Regenerate.
not supported by the current arch, only change the name if
its contents are the same as prev_name.
(get_specific): If the the architecture doesn't match, fail.
* elf32-mips.c (mips_elf_next_relocation): Rename from
mips_elf_next_lo16_relocation, and generalize to look
for any relocation type.
(elf_mips_howto_table): Make R_MIPS_PC16 pcrel_offset.
(elf_mips_gnu_rel_hi16): Howto for R_MIPS_GNU_REL_HI16.
(elf_mips_gnu_rel_lo16): Howto for R_MIPS_GNU_REL_LO16.
(elf_mips_gnu_rel16_s2): Howto for R_MIPS_GNU_REL16_S2.
(elf_mips_gnu_pcrel64): Howto for R_MIPS_PC64.
(elf_mips_gnu_pcrel32): Howto for R_MIPS_PC32.
(bfd_elf32_bfd_reloc_type_lookup): Add new relocs.
(mips_rtype_to_howto): Likewise.
(mips_elf_calculate_relocation): Handle new relocs.
(_bfd_mips_elf_relocate_section): REL_HI16/REL_LO16 relocs
are paired. The addend for R_MIPS_GNU_REL16_S2
is shifted right two bits.
In gas/:
* config/tc-mips.c (mips_ip): Don't put stuff in .rodata
when embedded-pic.
* config/tc-mips.c (SWITCH_TABLE): The ELF embedded-pic
implementation doesn't have special handling for switch
statements.
(macro_build): Allow for code in sections other than .text.
(macro): Likewise.
(mips_ip): Likewise.
(md_apply_fix): Do pc-relative relocation madness for MIPS ELF.
Don't perform relocs if we will be outputting them.
(tc_gen_reloc): For ELF, just use fx_addnumber for pc-relative
relocations. Allow BFD_RELOC_16_PCREL_S2 relocs when
embedded-pic.
In gas/testsuite/:
* gas/mips/empic.d: New file.
* gas/mips/empic.s: New file.
* gas/mips/mips16-e.d: New file.
* gas/mips/mips16-e.s: New file.
* gas/mips/mips16-f.d: New file.
* gas/mips/mips16-f.s: New file.
* gas/mips/mips.exp: Add empic, mips16-e. Add mips16-f as an
expected failure.
In include/elf:
* mips.h: Add R_MIPS_GNU_REL_HI16, R_MIPS_GNU_REL_LO16,
R_MIPS_GNU_REL16_S2, R_MIPS_PC64 and R_MIPS_PC32 relocation
numbers.
the errors exposed by this addition. These were intel mode
"fi... word ptr", "fi... dword ptr", "jmp Imm seg, Imm offset", "out dx,al".
The failure with intel "out dx,al" was also present in att "out al,dx".
Extend testsuite to catch this case too.
* config/tc-mips.c (mips_gp32): New variable.
(macro_build) Use mips_gp32.
(mips_ip): Ditto.
(md_longopts): Add "-mgp32" and "-mgp64".
(md_parse_option): Add OPTION_GP32 and OPTION_GP64.
Reinstate bits of sh4 support that got accidentally deleted.
Add sh-dsp support.
bfd:
* archures.c (bfd_mach_sh2, bfd_mach_sh_dsp): New macros.
(bfd_mach_sh3_dsp): Likewise.
(bfd_mach_sh4): Reinstate.
(bfd_default_scan): Recognize 7410, 7708, 7729 and 7750.
* bfd-in2.h: Regenerate.
* coff-sh.c (struct sh_opcode): flags is no longer short.
(USESAS, USESAS_REG, USESR8, SETSAS, SETSAS_REG): New macros.
(sh_opcode41, sh_opcode42): Integrate as sh_opcode41.
(sh_opcode01, sh_opcode02, sh_opcode40): Add sh-dsp opcodes.
(sh_opcode41, sh_opcode4, sh_opcode80): Likewise.
(sh_opcodes): No longer const.
(sh_dsp_opcodef0, sh_dsp_opcodef): New arrays.
(sh_insn_uses_reg): Check for USESAS and USESR8.
(sh_insn_sets_reg, sh_insns_conflict): Check for SETSAS.
(_bfd_sh_align_load_span): Return early for SH4.
Modify sh_opcodes lookup table for sh-dsp / sh3-dsp.
Take into account that field b of a parallel processing insn
could be mistaken for a separate insn.
* cpu-sh.c (arch_info_struct): New array elements for
sh2, sh-dsp and sh3-dsp.
Reinstate element for sh4.
(SH2_NEXT, SH_DSP_NEXT, SH3_DSP_NEXT): New macros.
(SH4_NEXT): Reinstate.
(SH3_NEXT, SH3E_NEXT): Adjust.
* elf-bfd.h (_sh_elf_set_mach_from_flags): Declare.
* elf32-sh.c (sh_elf_set_private_flags): New function.
(sh_elf_copy_private_data, sh_elf_set_mach_from_flags): Likewise.
(sh_elf_merge_private_data): New function.
(elf_backend_object_p, bfd_elf32_bfd_set_private_bfd_flags): Define.
(bfd_elf32_bfd_copy_private_bfd_data): Define.
(bfd_elf32_bfd_merge_private_bfd_data): Change to
sh_elf_merge_private_data.
gas:
* config/tc-sh.c ("elf/sh.h"): Include.
(sh_dsp, valid_arch, reg_x, reg_y, reg_efg): New static variables.
(md.begin): Initialize target_arch.
Only include opcodes in has table that match selected architecture.
(parse_reg): Recognize register names for sh-dsp.
(parse_at): Recognize post-modify addressing.
(get_operands): The leading space is now optional.
(get_specific): Remove FDREG_N support. Add support for sh-dsp
arguments. Update valid_arch.
(build_Mytes): Add support for SDT_REG_N.
(find_cooked_opcode): New function, broken out of md_assemble.
(assemble_ppi, sh_elf_final_processing): New functions.
(md_assemble): Use find_cooked_opcode and assemble_ppi.
(md_longopts, md_parse_option): New option: -dsp.
* config/tc-sh.h (elf_tc_final_processing): Define.
(sh_elf_final_processing): Declare.
include/elf:
* sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros.
(EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise.
(EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise.
opcodes:
* sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
(print_insn_ppi): Likewise.
(print_insn_shx): Use info->mach to select appropriate insn set.
Add support for sh-dsp. Remove FD_REG_N support.
* sh-opc.h (sh_nibble_type): Add new values for sh-dsp support.
(sh_arg_type): Likewise. Remove FD_REG_N.
(sh_dsp_reg_nums): New enum.
(arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros.
(arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise.
(arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise.
(arch_sh3_dsp_up): Likewise.
(sh_opcode_info): New field: arch.
(sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
D_REG_N. Fill in arch field. Add sh-dsp insns.
already defined.
* config/tc-ppc.h [OBJ_XCOFF] (OBJ_COPY_SYMBOL_ATTRIBUTES):
New macro.
* config/tc-ppc.c (ppc_fix_adjustable): Don't look at the frag
of a symbol when we really care about its value.
assembler. ie. You will be able to do "as --em=i386aout" on an x86
linux-elf assembler to generate aout format object files, rather than
using a separate assembler. The aout emulation is enabled by giving
"--enable-targets=i386-linuxaout" to configure.
Oh yeah, there's a couple of fixes too. Error messages shouldn't be
passed to printf in the format arg just in case someone puts a `%' in
the message.
if it is defined.
* config/obj-elf.c (elf_set_index): Add ATTRIBUTE_UNUSED.
* config/obj-elf.c (elf_frob_file_after_relocs): Don't pass NULL
to bfd_set_section_contents.
* mips.h (OPCODE_IS_MEMBER): New.
For gas:
* config/tc-mips.c (macro_build): Use OPCODE_IS_MEMBER.
(mips_ip): Use OPCODE_IS_MEMBER.
For opcodes:
* mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER.
(ISA_HAS_64_BIT_REGS) New.
(gpr_interlocks,md_begin,reg_needs_delay,append_insn,
mips_emit_delays,macro_build,load_register,load_addresss,
macro,macro2,mips_ip,s_cprestore,s_cpadd): Simplify
and/or use new ISA_xxx macros in expressions involving
ISA, particularly mips_opts.isa.
* config/tc-m32r.c (enable_m32rx): New static global.
(enable_special,warn_explicit_parallel_conflicts,optimize): Ditto.
(allow_m32rx): New function.
(M32R_SHORTOPTS): Add `O'.
(md_longopts): Add --m32rx plus several warning options.
(md_parse_option): Handle new options.
(md_show_usage): Print them.
(md_begin): Enable m32rx.
(OPERAND_IS_COND_BIT): New macro.
(first_writes_to_seconds_operands): New function.
(writes_to_pc,can_make_parallel,make_parallel): New functions.
(target_make_parallel,assemble_two_insns): New functions.
(md_assemble): Recognize "insn1 -> insn2" and "insn1 || insn2".
If optimizing and m32rx, try to make consecutive insns parallel.
* config/tc-i386.c (md_shortopts): Check OBJ_MAYBE_ELF as well as
OBJ_ELF. If ELF, add "sq".
(md_parse_option): If ELF, ignore -s and -q.
(md_show_usage): Mention ELF options.
debug_line.
(md_pseudo_table): Add .file and .line pseudo-ops for OBJ_ELF.
(md_assemble): Call dwarf2_where for OBJ_ELF.
(pa_ip): Call dwarf2_gen_line_info for OBJ_ELF.
(pa_end_of_source): New function.
* tc-hppa.h (md_end): Define for OBJ_ELF.
* config/obj-coff.c (obj_coff_endef): Don't merge labels, or
symbols which do not have a constant value, or tags with
non-tags. Remove the symbol from the list before adding it at the
end.
* config/obj-coff.c (obj_coff_endef) [BFD_ASSEMBLER]: Handle .ef
C_FCN symbol differently if TE_PE.
(obj_coff_line) [BFD_ASSEMBLER]: Always use the line number which
appears in the pseudo-op, rather coff_line_base which is only set
for a .bf symbol.
* config/atof-ieee.c (atof_ieee): Change what_kind to int.
* config/atof-vax.c (flonum_gen2vax): Change format_letter to
int.
(md_atof): Return NULL rather than 0.
* config/tc-i386.c (md_atof): Change type to int.
candidate instruction. Require registers for register arguments
when in strict mode. Require assemble-time constants for
constants when in strict mode.
(pa_get_absolute_expression): Require a constant when in strict
mode.
(pa_build_unwind_subspace): Remove #if 0 wrapper. Select a
suitable relocation based on the size of the target's pointer.
Always Use subsegment zero for the unwinders.
(pa_level): Handle "2.0w".
next_set_end even if the end symbol is being discarded.
* gasp.c: Add ATTRIBUTE_UNUSED as needed for non-BFD_ASSEMBLER.
* output-file.c, symbols.c, config/tc-i386.c: Likewise.
* config/obj-coff.c: Likewise.
(seg_info_type): Remove.
(seg_info_off_by_4): Change to array of segT.
(s_get_segment): Adjust accordingly.
(obj_pseudo_table): Fully initialize sentinel entry.
* config/tc-sparc.c (md_longopts): Add --no-undeclared-regs option.
(sparc_ip): Warn if %g2 or %g3 register is used and not covered
by .register pseudo-op if -64 and --no-undeclared-regs.
(s_register, sparc_adjust_symtab): New functions.
* config/tc-sparc.h (tc_adjust_symtab, sparc_adjust_symtab):
Declare sparc_adjust_symtab as tc_adjust_symtab.
* doc/c-sparc.texi: Add description of #ignore special literal
for .register pseudo-op.
* config/tc-sparc.c (sparc_ip): Allow OLO10 relocations
on -64 and not pic.
(output_insn): Put OLO10's secondary addend into tc_fix_data.
(md_apply_fix3): Handle BFD_RELOC_SPARC_OLO10.
(tc_gen_reloc): Return two relocs for OLO10, LO10 and SPARC13.
* config/tc-sparc.h (RELOC_EXPANSION_POSSIBLE,
MAX_RELOC_EXPANSION): Define.
(TC_FIX_TYPE, TC_INIT_FIX_DATA, TC_FIX_DATA_PRINT): Likewise.
as appropriate. Fill in structure initializations. Add variable
initializations. Add casts.
* dwarf2dbg.c (print_stats): Change i to size_t.
* listing.c (listing_listing): Change list_line to unsigned int.
and subspaces for ELF.
(GDB_DEBUG_SPACE_NAME): Delete definition for ELF.
(GDB_STRINGS_SUBSPACE_NAME): Likewise.
(GDB_SYMBOLS_SUBSPACE_NAME): Likewise
(UNWIND_SECTION_NAME): Likewise.
(space/subspace related structures): Conditionalize definitions
on OBJ_SOM.
(space/subspace directives and support routines): Conditionalize
definitions and references/uses on OBJ_SOM.
(label_symbol_struct): For ELF, track the symbol's segment. For
SOM track its space.
(pa_define_label, pa_undefine_label, pa_get_label): Corresponding
changes.
(USE_ALIASES): Kill for both SOM & ELF.
(pa_def_subspaces, pa_def_spaces): Corresponding changes.
(pa_space, pa_subspace): Corresponding changes.
(pa_spaces_begin): Corresponding chagnes.
(md_begin): Do not muck around with space/subspace stuff for
OBJ_ELF.
(md_apply_fix): Temporarily disable argument relocation stuff
for OBJ_ELF.
(tc_gen_reloc): Temporarily disable relocation generation for
OBJ_ELF
(pa_build_unwind_subspace): Similarly.
* write.c (fixup_segment): Don't add symbol value for i960 ELF.
* config/tc-i960.c (s_leafproc): Don't call tc_set_bal_of_cal if
OBJ_ELF.
(md_apply_fix): Simplify BFD_ASSEMBLER handling.
* config/tc-sparc.c (sparc_ip): Don't use side-effect expression
with isoctal.
* config/tc-sparc.c (synthetize_setuw, synthetize_setsw,
synthetize_setx): New functions.
(md_assemble): Broken the special cases into the above
functions. Make compiler happy if sizeof(bfd_vma)==4.
Fix sethi generated from set/setuw. If instructions have a relloc,
always clear the fields to be relocated in the opcode.
(sparc_ip): Remove special_case global variable.
* itbl-ops.c (itbl_get_reg_val): Add pval parameter. Return
indication of success rather than a value.
(itbl_get_val): Likewise.
(itbl_get_field): Use strcspn. Change delimiters to include
parens.
* itbl-ops.h (itbl_get_reg_val): Update declaration.
(itbl_get_val): Likewise.
* config/tc-mips.c (mips_ip): Update call to itbl_get_reg_val.
* config/tc-sparc.c (md_assemble): Fix up setx, support setsw.
Optimize set if sizeof(bfd_vma) == 64.
(sparc_ip): Fix sethi - without %hi() it should generate
R_SPARC_32 reloc, not R_SPARC_HI22.
(tc_gen_reloc): Handle BFD_RELOC_SPARC22.
* config/tc-sparc.c (md_begin): Handle native wordsize aliases.
(s_ncons): New function.
(native_op_table): New table.
(sparc_ip): Be more strict on %hi() etc.; prepare assembler for
R_SPARC_OLO10 handling.
creation logic from obj_elf_create_section.
* config/obj-elf.c (elf_pseudo_tab): Add pushsection/popsection.
(section_stack): New.
(special_sections): Make const.
(obj_elf_section): Gut and rewrite parsing.
(obj_elf_change_section): New function broken out of obj_elf_section.
(obj_elf_parse_section_letters): Likewise.
(obj_elf_section_word): Likewise.
(obj_elf_section_type): Likewise.
(obj_elf_previous): Treat as a toggle.
(obj_elf_popsection): New.
* config/tc-ppc.c (ppc_section_word): Take str+len not ptr_str.
(ppc_section_type): Likewise.
* config/tc-ppc.h: Likewise.
* expr.h (struct expressionS): Don't make X_op a bitfield.
* config/tc-alpha.c: Update for symbol handling changes.
(md_apply_fix) [case GPREL]: Use now_seg instead of absolute_section.
(load_expression, emit_ir_load, emit_loadstore, emit_jsrjmp): Likewise.
* config/tc-i960.c: Several minor changes to add ELF and
BFD_ASSEMBLER support.
* config/tc-i960.h: Likewise.
* configure.in (i960-*-elf*): New target.
* aclocal.m4, configure: Rebuild.
Move bitfield overflow checks to after the md_apply_fix call in
fixup_segment so that md_apply_fix has a chance to modify value.
Handle 8 and 16-bit pcrel relocs for i386.
Prototypes and other minor code cleanups.
