Add ATPCS register naming support

This commit is contained in:
Nick Clifton 2000-01-31 22:14:50 +00:00
parent 2c1c4c6219
commit 557537a556
5 changed files with 54 additions and 33 deletions

View file

@ -1,5 +1,9 @@
2000-01-31 Geoff Keating <geoffk@cygnus.com>
2000-01-31 Nick Clifton <nickc@cygnus.com>
* config/tc-arm.c (reg_table): Add support for ATPCS register
naming conventions.
2000-01-31 Geoff Keating <geoffk@cygnus.com>
* config/obj-coff.h (OBJ_COPY_SYMBOL_ATTRIBUTES): Don't define if
already defined.
* config/tc-ppc.h [OBJ_XCOFF] (OBJ_COPY_SYMBOL_ATTRIBUTES):

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@ -857,20 +857,22 @@ struct reg_entry
#define REG_LR 14
#define REG_SP 13
/* These are the standard names; Users can add aliases with .req */
/* These are the standard names. Users can add aliases with .req */
static CONST struct reg_entry reg_table[] =
{
/* Processor Register Numbers */
/* Processor Register Numbers. */
{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
{"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
{"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
{"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
/* APCS conventions */
/* APCS conventions. */
{"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
{"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
{"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
{"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
/* FP Registers */
/* ATPCS additions to APCS conventions. */
{"wr", 7}, {"v8", 11},
/* FP Registers. */
{"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
{"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
{"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
@ -881,6 +883,13 @@ static CONST struct reg_entry reg_table[] =
{"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
{"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
{"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
/* ATPCS additions to float register names. */
{"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
{"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
{"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
{"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
/* FIXME: At some point we need to add VFP register names. */
/* Array terminator. */
{NULL, 0}
};

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@ -1,3 +1,11 @@
2000-01-31 Nick Clifton <nickc@cygnus.com>
* gas/arm/inst.s: Include test of ATPCS register naming
conventions.
* gas/arm/float.s: Include test of ATPCS register naming
conventions.
Fri Jan 21 12:48:06 2000 H.J. Lu <hjl@gnu.org>
* gas/i386/general.l: Support a.out.

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@ -4,21 +4,21 @@
mvfeqe f3, f5
mvfeqd f4, #1.0
mvfs f4, f7
mvfsp f0, f1
mvfdm f3, f4
mvfez f7, f7
mvfsp s0, s1
mvfdm s3, s4
mvfez s7, s7
adfe f0, f1, #2.0
adfeqe f1, f2, #0.5
adfsm f3, f4, f5
adfeqe f1, s2, #0.5
adfsm f3, f4, s5
sufd f0, f0, #2.0
sufs f1, f2, #10.0
sufneez f3, f4, f5
sufd d0, f0, #2.0
sufs d1, d2, #10.0
sufneez d3, d4, d5
rsfs f1, f1, #0.0
rsfdp f3, f0, #5.0
rsfled f7, f6, f0
rsfled f7, s6, f0
mufd f0, f0, f0
mufez f1, f2, #3.0
@ -34,9 +34,9 @@
powd f0, f2, f3
pows f1, f3, #0e1e1
powcsez f4, f7, #1
powcsez f4, d7, #1
rpws f7, f6, f7
rpws f7, d6, f7
rpweqd f0, f1, f2
rpwem f2, f2, f3

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@ -9,25 +9,25 @@
mov r8, r9, asr r10
mov r11, r12, asl r13
mov r14, r15, rrx
moval r1, r2
moveq r2, r3
movne r4, r5
movlt r6, r7
movge r8, r9
movle r10, r11
movgt r12, r13
moval a2, a3
moveq a3, a4
movne v1, v2
movlt v3, v4
movge v5, v6
movle v7, v8
movgt ip, sp
movcc r1, r2
movcs r1, r3
movmi r3, r6
movpl r7, r9
movpl wr, sb
movvs r1, r8
movvc r9, r1, lsr #31
movhi r8, r15
movls r15, r14
movvc SB, r1, lsr #31
movhi r8, pc
movls PC, lr
movhs r9, r8
movul r1, r3
movs r0, r8
movuls r0, r7
movuls r0, WR
add r0, r1, #10
add r2, r3, r4
@ -129,10 +129,10 @@
mulne r0, r1, r0
mullss r9, r8, r7
mla r1, r9, r10, r11
mlas r3, r4, r9, r12
mlalt r9, r8, r7, r13
mlages r4, r1, r3, r14
mla r1, r9, sl, fp
mlas r3, r4, r9, IP
mlalt r9, r8, r7, SP
mlages r4, r1, r3, LR
ldr r0, [r1]
ldr r1, [r1, r2]
@ -165,7 +165,7 @@ bar:
ldmia r0, {r1}
ldmeqib r2, {r3, r4, r5}
ldmalda r3, {r0-r15}^
ldmdb r11!, {r0-r8, r10}
ldmdb FP!, {r0-r8, SL}
ldmed r1, {r0, r1, r2}|0xf0
ldmfd r2, {r3, r4}+{r5, r6, r7, r8}
ldmea r3, 3