Maciej W. Rozycki
2b0c8b40ed
include/opcode/
...
* mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
(INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
(INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
(INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
(INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
(INSN2_READ_GPR_MMN): Likewise.
(INSN2_READ_FPR_D): Change the bit used.
(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
(INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
(INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
(INSN2_COND_BRANCH): Likewise.
(INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
(INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
(INSN2_MOD_GPR_MN): Likewise.
gas/
* config/tc-mips.c (gpr_mod_mask): Remove INSN2_MOD_GPR_MB,
INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG,
INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MM,
INSN2_MOD_GPR_MN, INSN2_MOD_GPR_MP and INSN2_MOD_GPR_MQ opcode
register use checks.
(gpr_read_mask): Add INSN2_READ_GPR_MC, INSN2_READ_GPR_ME
INSN2_READ_GPR_MG, INSN2_READ_GPR_MJ, INSN2_READ_GPR_MMN,
INSN2_READ_GPR_MP and INSN2_READ_GPR_MQ opcode register use
checks.
(gpr_write_mask): Replace INSN2_WRITE_GPR_S opcode register
use flag with INSN_WRITE_GPR_S. Add INSN2_WRITE_GPR_MB,
INSN2_WRITE_GPR_MHI, INSN2_WRITE_GPR_MJ and INSN2_WRITE_GPR_MP
opcode register use checks.
(can_swap_branch_p): Enable microMIPS branch swapping.
(append_insn): Likewise.
gas/testsuite/
* gas/mips/micromips.d: Update according to changes to enable
microMIPS branch swapping.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips@jal-svr4pic.d: Likewise.
* gas/mips/micromips@loc-swap.d: Likewise.
* gas/mips/micromips@loc-swap-dis.d: Likewise.
opcodes/
* micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
(MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
(MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
(RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
(RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
(WR_s): Update macro.
(micromips_opcodes): Update register use flags of: "addiu",
"addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
"and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
"jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
"lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
"nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
"swm" and "xor" instructions.
2011-08-09 14:25:29 +00:00
David S. Miller
ea783ef3a0
include/opcode/
...
* sparc.h: Document new format codes '4', '5', and '('.
(OPF_LOW4, RS3): New macros.
opcodes/
* sparc-dis.c (v9a_ast_reg_names): Add "cps".
(X_RS3): New macro.
(print_insn_sparc): Handle '4', '5', and '(' format codes.
Accept %asr numbers below 28.
* sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
instructions.
gas/
* config/tc-sparc.c (v9a_asr_table): Add "cps".
(sparc_ip): Handle '4', '5' and '(' format codes.
gas/testsuite
* gas/sparc/hpcvis3.d: New test.
* gas/sparc/hpcvis3.s: New test source.
* gas/sparc/sparc.exp: Run new test.
2011-08-05 16:52:50 +00:00
Quentin Neill
3929df0978
opcodes/
...
2011-08-02 Quentin Neill <quentin.neill@amd.com>
* i386-dis.c (xop_table): Remove spurious bextr insn.
2011-08-02 19:58:06 +00:00
H.J. Lu
d7921315ba
Check R_X86_64_32 overflow and allow R_X86_64_64 for x32.
...
bfd/
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
PR ld/13048
* archures.c (bfd_mach_i386_intel_syntax): New.
(bfd_mach_i386_i8086): Updated.
(bfd_mach_i386_i386): Likewise.
(bfd_mach_x86_64): Likewise.
(bfd_mach_x64_32): Likewise.
(bfd_mach_i386_i386_intel_syntax): Likewise.
(bfd_mach_x86_64_intel_syntax): Likewise.
(bfd_mach_x64_32_intel_syntax): Likewise.
(bfd_mach_l1om): Likewise.
(bfd_mach_l1om_intel_syntax): Likewise.
(bfd_mach_k1om): Likewise.
(bfd_mach_k1om_intel_syntax): Likewise.
* bfd-in2.h: Regenerated.
* cpu-i386.c (bfd_i386_compatible): Check mach instead of
bits_per_address.
(bfd_x64_32_arch_intel_syntax): Set bits_per_address to 64.
(bfd_x64_32_arch): Likewise.
* elf64-x86-64.c: Include "libiberty.h".
(x86_64_elf_howto_table): Append x32 R_X86_64_32.
(elf_x86_64_rtype_to_howto): Support x32 R_X86_64_32.
(elf_x86_64_reloc_type_lookup): Likewise.
(elf_x86_64_reloc_name_lookup): Likewise.
(elf_x86_64_relocate_section): Likewise.
(elf_x86_64_check_relocs): Allow R_X86_64_64 relocations for x32.
gas/
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
PR ld/13048
* config/tc-i386.c (handle_quad): Removed.
(md_pseudo_table): Remove "quad".
(tc_gen_reloc): Don't check BFD_RELOC_64 for disallow_64bit_reloc.
(x86_dwarf2_addr_size): New.
* config/tc-i386.h (x86_dwarf2_addr_size): New.
(DWARF2_ADDR_SIZE): Likewise.
gas/testsuite/
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
PR ld/13048
* gas/i386/ilp32/ilp32.exp: Don't run inval.
* gas/i386/ilp32/inval.l: Removed.
* gas/i386/ilp32/inval.s: Likewise.
* gas/i386/ilp32/quad.d: Expect R_X86_64_64 instead of
R_X86_64_32.
* gas/i386/ilp32/x86-64-pcrel.s: Add tests for movabs.
* gas/i386/ilp32/x86-64-pcrel.d: Updated.
ld/testsuite/
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
PR ld/13048
* ld-x86-64/ilp32-6.d: New.
* ld-x86-64/ilp32-6.s: Likewise.
* ld-x86-64/ilp32-7.d: Likewise.
* ld-x86-64/ilp32-7.s: Likewise.
* ld-x86-64/ilp32-8.d: Likewise.
* ld-x86-64/ilp32-8.s: Likewise.
* ld-x86-64/ilp32-9.d: Likewise.
* ld-x86-64/ilp32-9.s: Likewise.
* ld-x86-64/x86-64.exp: Run ilp32-6, ilp32-7, ilp32-8 and ilp32-9.
opcodes/
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
PR ld/13048
* i386-dis.c (print_insn): Optimize info->mach check.
2011-08-01 23:04:23 +00:00
H.J. Lu
00f51a41a8
Add Disp32S to 64bit call.
...
gas/testsuite/
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
PR gas/13046
* gas/i386/x86-64-branch.s: Add tests for direct branch.
* gas/i386/x86-64-branch.d: Updated.
* gas/i386/ilp32/x86-64-branch.d: Likewise.
opcodes/
2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
PR gas/13046
* i386-opc.tbl: Add Disp32S to 64bit call.
* i386-tbl.h: Regenerated.
2011-08-01 19:25:48 +00:00
Richard Sandiford
f65c50ad0c
Fix misapplied patch.
2011-07-24 14:57:31 +00:00
Richard Sandiford
df58fc944d
bfd/
...
2011-02-25 Chao-ying Fu <fu@mips.com>
Ilie Garbacea <ilie@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* archures.c (bfd_mach_mips_micromips): New macro.
* cpu-mips.c (I_micromips): New enum value.
(arch_info_struct): Add bfd_mach_mips_micromips.
* elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New
prototype.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(gprel16_reloc_p): Handle microMIPS ASE.
(literal_reloc_p): New function.
* elf32-mips.c (elf_micromips_howto_table_rel): New variable.
(_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(mips_elf_gprel32_reloc): Update comment.
(micromips_reloc_map): New variable.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(mips_elf32_rtype_to_howto): Likewise.
(mips_info_to_howto_rel): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
(bfd_elf32_bfd_relax_section): Likewise.
* elf64-mips.c (micromips_elf64_howto_table_rel): New variable.
(micromips_elf64_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf64_bfd_reloc_name_lookup): Likewise.
(mips_elf64_rtype_to_howto): Likewise.
(bfd_elf64_bfd_is_target_special_symbol): Define.
* elfn32-mips.c (elf_micromips_howto_table_rel): New variable.
(elf_micromips_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf32_bfd_reloc_name_lookup): Likewise.
(mips_elf_n32_rtype_to_howto): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
* elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro.
(LA25_LUI_MICROMIPS_2): Likewise.
(LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise.
(LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise.
(TLS_RELOC_P): Handle microMIPS ASE.
(mips_elf_create_stub_symbol): Adjust value of stub symbol if
target is a microMIPS function.
(micromips_reloc_p): New function.
(micromips_reloc_shuffle_p): Likewise.
(got16_reloc_p, call16_reloc_p): Handle microMIPS ASE.
(got_disp_reloc_p, got_page_reloc_p): New functions.
(got_ofst_reloc_p): Likewise.
(got_hi16_reloc_p, got_lo16_reloc_p): Likewise.
(call_hi16_reloc_p, call_lo16_reloc_p): Likewise.
(hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE.
(micromips_branch_reloc_p): New function.
(tls_gd_reloc_p, tls_ldm_reloc_p): Likewise.
(tls_gottprel_reloc_p): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE.
(mips_tls_got_index, mips_elf_got_page): Likewise.
(mips_elf_create_local_got_entry): Likewise.
(mips_elf_relocation_needs_la25_stub): Likewise.
(mips_elf_calculate_relocation): Likewise.
(mips_elf_perform_relocation): Likewise.
(_bfd_mips_elf_symbol_processing): Likewise.
(_bfd_mips_elf_add_symbol_hook): Likewise.
(_bfd_mips_elf_link_output_symbol_hook): Likewise.
(mips_elf_add_lo16_rel_addend): Likewise.
(_bfd_mips_elf_check_relocs): Likewise.
(mips_elf_adjust_addend): Likewise.
(_bfd_mips_elf_relocate_section): Likewise.
(mips_elf_create_la25_stub): Likewise.
(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
(_bfd_mips_elf_gc_sweep_hook): Likewise.
(_bfd_mips_elf_is_target_special_symbol): New function.
(mips_elf_relax_delete_bytes): Likewise.
(opcode_descriptor): New structure.
(RA): New macro.
(OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise.
(b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables.
(beq_insn_32): Likewise.
(b_insn_16, bz_insn_16): New variables.
(BZC32_REG_FIELD): New macro.
(bz_rs_insns_32, bz_rt_insns_32): New variables.
(bzc_insns_32, bz_insns_16):Likewise.
(BZ16_REG, BZ16_REG_FIELD): New macros.
(jal_insn_32_bd16, jal_insn_32_bd32): New variables.
(jal_x_insn_32_bd32): Likewise.
(j_insn_32, jalr_insn_32): Likewise.
(ds_insns_32_bd16, ds_insns_32_bd32): Likewise.
(jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise.
(JR16_REG): New macro.
(ds_insns_16_bd16): New variable.
(lui_insn): Likewise.
(addiu_insn, addiupc_insn): Likewise.
(ADDIUPC_REG_FIELD): New macro.
(MOVE32_RD, MOVE32_RS): Likewise.
(MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise.
(move_insns_32, move_insns_16): New variables.
(nop_insn_32, nop_insn_16): Likewise.
(MATCH): New macro.
(find_match): New function.
(check_br16_dslot, check_br32_dslot): Likewise.
(check_br16, check_br32): Likewise.
(IS_BITSIZE): New macro.
(check_4byte_branch): New function.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16
and microMIPS modules together.
(_bfd_mips_elf_print_private_bfd_data): Handle microMIPS ASE.
* reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation.
(BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_GPREL16): Likewise.
(BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise.
(BFD_RELOC_MICROMIPS_HI16_S): Likewise.
(BFD_RELOC_MICROMIPS_LO16): Likewise.
(BFD_RELOC_MICROMIPS_LITERAL): Likewise.
(BFD_RELOC_MICROMIPS_GOT16): Likewise.
(BFD_RELOC_MICROMIPS_CALL16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_HI16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_LO16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_SUB): Likewise.
(BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise.
(BFD_RELOC_MICROMIPS_GOT_OFST): Likewise.
(BFD_RELOC_MICROMIPS_GOT_DISP): Likewise.
(BFD_RELOC_MICROMIPS_HIGHEST): Likewise.
(BFD_RELOC_MICROMIPS_HIGHER): Likewise.
(BFD_RELOC_MICROMIPS_SCN_DISP): Likewise.
(BFD_RELOC_MICROMIPS_JALR): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GD): Likewise.
(BFD_RELOC_MICROMIPS_TLS_LDM): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
binutils/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* readelf.c (get_machine_flags): Handle microMIPS ASE.
(get_mips_symbol_other): Likewise.
gas/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.h (mips_segment_info): Add one bit for
microMIPS.
(TC_LABEL_IS_LOCAL): New macro.
(mips_label_is_local): New prototype.
* config/tc-mips.c (S0, S7): New macros.
(emit_branch_likely_macro): New variable.
(mips_set_options): Add micromips.
(mips_opts): Initialise micromips to -1.
(file_ase_micromips): New variable.
(CPU_HAS_MICROMIPS): New macro.
(hilo_interlocks): Set for microMIPS too.
(gpr_interlocks): Likewise.
(cop_interlocks): Likewise.
(cop_mem_interlocks): Likewise.
(HAVE_CODE_COMPRESSION): New macro.
(micromips_op_hash): New variable.
(micromips_nop16_insn, micromips_nop32_insn): New variables.
(NOP_INSN): Handle microMIPS ASE.
(mips32_to_micromips_reg_b_map): New macro.
(mips32_to_micromips_reg_c_map): Likewise.
(mips32_to_micromips_reg_d_map): Likewise.
(mips32_to_micromips_reg_e_map): Likewise.
(mips32_to_micromips_reg_f_map): Likewise.
(mips32_to_micromips_reg_g_map): Likewise.
(mips32_to_micromips_reg_l_map): Likewise.
(mips32_to_micromips_reg_n_map): Likewise.
(mips32_to_micromips_reg_h_map): New variable.
(mips32_to_micromips_reg_m_map): Likewise.
(mips32_to_micromips_reg_q_map): Likewise.
(micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_to_32_reg_b_map): New macro.
(micromips_to_32_reg_c_map): Likewise.
(micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map): Likewise.
(micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map): Likewise.
(micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_n_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): New macros.
(RELAX_DELAY_SLOT_16BIT): New macro.
(RELAX_DELAY_SLOT_SIZE_FIRST): Likewise.
(RELAX_DELAY_SLOT_SIZE_SECOND): Likewise.
(RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros.
(RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_AT): Likewise.
(RELAX_MICROMIPS_U16BIT, RELAX_MICROMIPS_UNCOND): Likewise.
(RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR16): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise.
(RELAX_MICROMIPS_TOOFAR32): Likewise.
(RELAX_MICROMIPS_MARK_TOOFAR32): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise.
(INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE.
(mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p,
fsize and insns.
(mips_mark_labels): New function.
(mips16_small, mips16_ext): Remove variables, replacing with...
(forced_insn_size): ... this.
(append_insn, mips16_ip): Update accordingly.
(micromips_insn_length): New function.
(insn_length): Return the length of microMIPS instructions.
(mips_record_mips16_mode): Rename to...
(mips_record_compressed_mode): ... this. Handle microMIPS ASE.
(install_insn): Handle microMIPS ASE.
(reglist_lookup): New function.
(is_size_valid, is_delay_slot_valid): Likewise.
(md_begin): Handle microMIPS ASE.
(md_assemble): Likewise. Update for append_insn interface change.
(micromips_reloc_p): New function.
(got16_reloc_p): Handle microMIPS ASE.
(hi16_reloc_p): Likewise.
(lo16_reloc_p): Likewise.
(jmp_reloc_p): New function.
(jalr_reloc_p): Likewise.
(matching_lo_reloc): Handle microMIPS ASE.
(insn_uses_reg, reg_needs_delay): Likewise.
(mips_move_labels): Likewise.
(mips16_mark_labels): Rename to...
(mips_compressed_mark_labels): ... this. Handle microMIPS ASE.
(gpr_mod_mask): New function.
(gpr_read_mask, gpr_write_mask): Handle microMIPS ASE.
(fpr_read_mask, fpr_write_mask): Likewise.
(insns_between, nops_for_vr4130, nops_for_insn): Likewise.
(fix_loongson2f_nop, fix_loongson2f_jump): Likewise.
(MICROMIPS_LABEL_CHAR): New macro.
(micromips_target_label, micromips_target_name): New variables.
(micromips_label_name, micromips_label_expr): New functions.
(micromips_label_inc, micromips_add_label): Likewise.
(mips_label_is_local): Likewise.
(micromips_map_reloc): Likewise.
(can_swap_branch_p): Handle microMIPS ASE.
(append_insn): Add expansionp argument. Handle microMIPS ASE.
(start_noreorder, end_noreorder): Handle microMIPS ASE.
(macro_start, macro_warning, macro_end): Likewise.
(brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables.
(mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise.
(BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros.
(MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise.
(macro_build): Handle microMIPS ASE. Update for append_insn
interface change.
(mips16_macro_build): Update for append_insn interface change.
(macro_build_jalr): Handle microMIPS ASE.
(macro_build_lui): Likewise. Simplify.
(load_register): Handle microMIPS ASE.
(load_address): Likewise.
(move_register): Likewise.
(macro_build_branch_likely): New function.
(macro_build_branch_ccl): Likewise.
(macro_build_branch_rs): Likewise.
(macro_build_branch_rsrt): Likewise.
(macro): Handle microMIPS ASE.
(validate_micromips_insn): New function.
(expr_const_in_range): Likewise.
(mips_ip): Handle microMIPS ASE.
(options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS.
(md_longopts): Add mmicromips and mno-micromips.
(md_parse_option): Handle OPTION_MICROMIPS and
OPTION_NO_MICROMIPS.
(mips_after_parse_args): Handle microMIPS ASE.
(md_pcrel_from): Handle microMIPS relocations.
(mips_force_relocation): Likewise.
(md_apply_fix): Likewise.
(mips_align): Handle microMIPS ASE.
(s_mipsset): Likewise.
(s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers.
(s_dtprel_internal): Likewise.
(s_gpword, s_gpdword): Likewise.
(s_insn): Handle microMIPS ASE.
(s_mips_stab): Likewise.
(relaxed_micromips_32bit_branch_length): New function.
(relaxed_micromips_16bit_branch_length): New function.
(md_estimate_size_before_relax): Handle microMIPS ASE.
(mips_fix_adjustable): Likewise.
(tc_gen_reloc): Handle microMIPS relocations.
(mips_relax_frag): Handle microMIPS ASE.
(md_convert_frag): Likewise.
(mips_frob_file_after_relocs): Likewise.
(mips_elf_final_processing): Likewise.
(mips_nop_opcode): Likewise.
(mips_handle_align): Likewise.
(md_show_usage): Handle microMIPS options.
* symbols.c (TC_LABEL_IS_LOCAL): New macro.
(S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check.
* doc/as.texinfo (Target MIPS options): Add -mmicromips and
-mno-micromips.
(-mmicromips, -mno-micromips): New options.
* doc/c-mips.texi (-mmicromips, -mno-micromips): New options.
(MIPS ISA): Document .set micromips and .set nomicromips.
(MIPS insn): Update for microMIPS support.
gas/testsuite/
2011-02-25 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
* gas/mips/micromips.d: New test.
* gas/mips/micromips-branch-delay.d: Likewise.
* gas/mips/micromips-branch-relax.d: Likewise.
* gas/mips/micromips-branch-relax-pic.d: Likewise.
* gas/mips/micromips-size-1.d: Likewise.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New stderr output.
* gas/mips/micromips-branch-delay.l: Likewise.
* gas/mips/micromips-branch-relax.l: Likewise.
* gas/mips/micromips-branch-relax-pic.l: Likewise.
* gas/mips/micromips-size-0.l: New list test.
* gas/mips/micromips-size-1.l: New stderr output.
* gas/mips/micromips.s: New test source.
* gas/mips/micromips-branch-delay.s: Likewise.
* gas/mips/micromips-branch-relax.s: Likewise.
* gas/mips/micromips-size-0.s: Likewise.
* gas/mips/micromips-size-1.s: Likewise.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/dli.s: Use .p2align.
* gas/mips/elf_ase_micromips.d: New test.
* gas/mips/elf_ase_micromips-2.d: Likewise.
* gas/mips/micromips@abs.d: Likewise.
* gas/mips/micromips@add.d: Likewise.
* gas/mips/micromips@alnv_ps-swap.d: Likewise.
* gas/mips/micromips@and.d: Likewise.
* gas/mips/micromips@beq.d: Likewise.
* gas/mips/micromips@bge.d: Likewise.
* gas/mips/micromips@bgeu.d: Likewise.
* gas/mips/micromips@blt.d: Likewise.
* gas/mips/micromips@bltu.d: Likewise.
* gas/mips/micromips@branch-likely.d: Likewise.
* gas/mips/micromips@branch-misc-1.d: Likewise.
* gas/mips/micromips@branch-misc-2-64.d: Likewise.
* gas/mips/micromips@branch-misc-2.d: Likewise.
* gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
* gas/mips/micromips@branch-misc-2pic.d: Likewise.
* gas/mips/micromips@branch-misc-4-64.d: Likewise.
* gas/mips/micromips@branch-misc-4.d: Likewise.
* gas/mips/micromips@branch-self.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@daddi.d: Likewise.
* gas/mips/micromips@dli.d: Likewise.
* gas/mips/micromips@elf-jal.d: Likewise.
* gas/mips/micromips@elf-rel2.d: Likewise.
* gas/mips/micromips@elfel-rel2.d: Likewise.
* gas/mips/micromips@elf-rel4.d: Likewise.
* gas/mips/micromips@jal-svr4pic.d: Likewise.
* gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise.
* gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise.
* gas/mips/micromips@li.d: Likewise.
* gas/mips/micromips@loc-swap-dis.d: Likewise.
* gas/mips/micromips@loc-swap.d: Likewise.
* gas/mips/micromips@mips1-fp.d: Likewise.
* gas/mips/micromips@mips32-cp2.d: Likewise.
* gas/mips/micromips@mips32-imm.d: Likewise.
* gas/mips/micromips@mips32-sf32.d: Likewise.
* gas/mips/micromips@mips32.d: Likewise.
* gas/mips/micromips@mips32r2-cp2.d: Likewise.
* gas/mips/micromips@mips32r2-fp32.d: Likewise.
* gas/mips/micromips@mips32r2-sync.d: Likewise.
* gas/mips/micromips@mips32r2.d: Likewise.
* gas/mips/micromips@mips4-branch-likely.d: Likewise.
* gas/mips/micromips@mips4-fp.d: Likewise.
* gas/mips/micromips@mips4.d: Likewise.
* gas/mips/micromips@mips5.d: Likewise.
* gas/mips/micromips@mips64-cp2.d: Likewise.
* gas/mips/micromips@mips64.d: Likewise.
* gas/mips/micromips@mips64r2.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips@relax-at.d: Likewise.
* gas/mips/micromips@relax.d: Likewise.
* gas/mips/micromips@rol-hw.d: Likewise.
* gas/mips/micromips@uld2-eb.d: Likewise.
* gas/mips/micromips@uld2-el.d: Likewise.
* gas/mips/micromips@ulh2-eb.d: Likewise.
* gas/mips/micromips@ulh2-el.d: Likewise.
* gas/mips/micromips@ulw2-eb-ilocks.d: Likewise.
* gas/mips/micromips@ulw2-el-ilocks.d: Likewise.
* gas/mips/cache.d: Likewise.
* gas/mips/daddi.d: Likewise.
* gas/mips/mips32-imm.d: Likewise.
* gas/mips/pref.d: Likewise.
* gas/mips/elf-rel27.d: Handle microMIPS ASE.
* gas/mips/l_d.d: Likewise.
* gas/mips/l_d-n32.d: Likewise.
* gas/mips/l_d-n64.d: Likewise.
* gas/mips/ld.d: Likewise.
* gas/mips/ld-n32.d: Likewise.
* gas/mips/ld-n64.d: Likewise.
* gas/mips/s_d.d: Likewise.
* gas/mips/s_d-n32.d: Likewise.
* gas/mips/s_d-n64.d: Likewise.
* gas/mips/sd.d: Likewise.
* gas/mips/sd-n32.d: Likewise.
* gas/mips/sd-n64.d: Likewise.
* gas/mips/mips32.d: Update immediates.
* gas/mips/micromips@mips32-cp2.s: New test source.
* gas/mips/micromips@mips32-imm.s: Likewise.
* gas/mips/micromips@mips32r2-cp2.s: Likewise.
* gas/mips/micromips@mips64-cp2.s: Likewise.
* gas/mips/cache.s: Likewise.
* gas/mips/daddi.s: Likewise.
* gas/mips/mips32-imm.s: Likewise.
* gas/mips/elf-rel4.s: Handle microMIPS ASE.
* gas/mips/lb-pic.s: Likewise.
* gas/mips/ld.s: Likewise.
* gas/mips/mips32.s: Likewise.
* gas/mips/mips.exp: Add the micromips arch. Exclude mips16e
from micromips. Run mips32-imm.
* gas/mips/jal-mask-11.d: New test.
* gas/mips/jal-mask-12.d: Likewise.
* gas/mips/micromips@jal-mask-11.d: Likewise.
* gas/mips/jal-mask-1.s: Source for the new tests.
* gas/mips/jal-mask-21.d: New test.
* gas/mips/jal-mask-22.d: Likewise.
* gas/mips/micromips@jal-mask-12.d: Likewise.
* gas/mips/jal-mask-2.s: Source for the new tests.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/mips16-e.d: Add --special-syms to `objdump'.
* gas/mips/tmips16-e.d: Likewise.
* gas/mips/mipsel16-e.d: Likewise.
* gas/mips/tmipsel16-e.d: Likewise.
* gas/mips/and.s: Adjust padding.
* gas/mips/beq.s: Likewise.
* gas/mips/bge.s: Likewise.
* gas/mips/bgeu.s: Likewise.
* gas/mips/blt.s: Likewise.
* gas/mips/bltu.s: Likewise.
* gas/mips/branch-misc-2.s: Likewise.
* gas/mips/jal.s: Likewise.
* gas/mips/li.s: Likewise.
* gas/mips/mips4.s: Likewise.
* gas/mips/mips4-fp.s: Likewise.
* gas/mips/relax.s: Likewise.
* gas/mips/and.d: Update accordingly.
* gas/mips/elf-jal.d: Likewise.
* gas/mips/jal.d: Likewise.
* gas/mips/li.d: Likewise.
* gas/mips/relax-at.d: Likewise.
* gas/mips/relax.d: Likewise.
include/elf/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (R_MICROMIPS_min): New relocations.
(R_MICROMIPS_26_S1): Likewise.
(R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise.
(R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise.
(R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise.
(R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise.
(R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise.
(R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise.
(R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise.
(R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise.
(R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise.
(R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise.
(R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise.
(R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise.
(R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise.
(R_MICROMIPS_TLS_GOTTPREL): Likewise.
(R_MICROMIPS_TLS_TPREL_HI16): Likewise.
(R_MICROMIPS_TLS_TPREL_LO16): Likewise.
(R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise.
(R_MICROMIPS_max): Likewise.
(EF_MIPS_ARCH_ASE_MICROMIPS): New macro.
(STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise.
(ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise.
(STO_MICROMIPS): Likewise.
(ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise.
(ELF_ST_IS_COMPRESSED): Likewise.
(STO_MIPS_PLT, STO_MIPS_PIC): Rework.
(ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise.
(STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise.
include/opcode/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
(OP_MASK_CODE10, OP_SH_CODE10): Likewise.
(OP_MASK_TRAP, OP_SH_TRAP): Likewise.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
(OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
(OP_MASK_RS3, OP_SH_RS3): Likewise.
(OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
(OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
(OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
(OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
(OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
(OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
(OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
(OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
(OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
(OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
(OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
(OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
(OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
(OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
(INSN_WRITE_GPR_S): New macro.
(INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
(INSN2_READ_FPR_D): Likewise.
(INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
(INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
(INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
(INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
(INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
(CPU_MICROMIPS): New macro.
(M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
(M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
(M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
(M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
(M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
(M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
(M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
(M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
(M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
(M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
(M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
(M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
(M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
(MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
(MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
(MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
(MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
(MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
(MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
(MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
(MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
(MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
(MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
(MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
(MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
(MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
(MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
(MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
(MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
(MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
(MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
(MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
(MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
(MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
(MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
(MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
(MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
(MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
(MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
(MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
(MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
(MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
(MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
(MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
(MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
(MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
(MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
(MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
(MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
(MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
(MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
(MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
(MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
(MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
(MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
(MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
(MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
(MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
(MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
(MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
(MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
(MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
(MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
(MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
(MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
(MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
(MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
(MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
(MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
(MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
(MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
(MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
(MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
(MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
(MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
(MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
(MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
(MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
(MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
(MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
(MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
(MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
(MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
(MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
(MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
(MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
(MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
(micromips_opcodes): New declaration.
(bfd_micromips_num_opcodes): Likewise.
ld/testsuite/
2011-02-25 Catherine Moore <clm@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* lib/ld-lib.exp (run_dump_test): Support distinct assembler
flags for the same source named multiple times.
* ld-mips-elf/jalx-1.s: New test source.
* ld-mips-elf/jalx-1.d: New test output.
* ld-mips-elf/jalx-1.ld: New test linker script.
* ld-mips-elf/jalx-2-main.s: New test source.
* ld-mips-elf/jalx-2-ex.s: Likewise.
* ld-mips-elf/jalx-2-printf.s: Likewise.
* ld-mips-elf/jalx-2.dd: New test output.
* ld-mips-elf/jalx-2.ld: New test linker script.
* ld-mips-elf/mips16-and-micromips.d: New test.
* ld-mips-elf/mips-elf.exp: Run the new tests
opcodes/
2011-02-25 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* micromips-opc.c: New file.
* mips-dis.c (micromips_to_32_reg_b_map): New array.
(micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): Likewise.
(micromips_ase): New variable.
(is_micromips): New function.
(set_default_mips_dis_options): Handle microMIPS ASE.
(print_insn_micromips): New function.
(is_compressed_mode_p): Likewise.
(_print_insn_mips): Handle microMIPS instructions.
* Makefile.am (CFILES): Add micromips-opc.c.
* configure.in (bfd_mips_arch): Add micromips-opc.lo.
* Makefile.in: Regenerate.
* configure: Regenerate.
* mips-dis.c (micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_n_map): New macro.
2011-07-24 14:20:15 +00:00
Richard Sandiford
bcd530a713
include/opcode/
...
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (INSN_TRAP): Rename to...
(INSN_NO_DELAY_SLOT): ... this.
(INSN_SYNC): Remove macro.
gas/
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.c (can_swap_branch_p): Adjust for the rename of
INSN_TRAP to INSN_NO_DELAY_SLOT. Remove the check for INSN_SYNC
as well as explicit checks for ERET and DERET when scheduling
branch delay slots.
opcodes/
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* mips-opc.c (NODS): New macro.
(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
(DSP_VOLA): Likewise.
(mips_builtin_opcodes): Add NODS annotation to "deret" and
"eret". Replace INSN_SYNC with NODS throughout. Use NODS in
place of TRAP for "wait", "waiti" and "yield".
* mips16-opc.c (NODS): New macro.
(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
(mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
"restore" and "save".
2011-07-24 14:04:51 +00:00
H.J. Lu
7a9068fe16
Add initial Intel K1OM support.
...
bfd/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.am (ALL_MACHINES): Add cpu-k1om.lo.
(ALL_MACHINES_CFILES): Add cpu-k1om.c.
* Makefile.in: Regenerated.
* archures.c (bfd_architecture): Add bfd_arch_k1om.
(bfd_k1om_arch): New.
(bfd_archures_list): Add &bfd_k1om_arch.
* bfd-in2.h: Regenerated.
* config.bfd (targ64_selvecs): Add bfd_elf64_k1om_vec if
bfd_elf64_x86_64_vec is supported. Add bfd_elf64_k1om_freebsd_vec
if bfd_elf64_x86_64_freebsd_vec is supported.
(targ_selvecs): Likewise.
* configure.in: Support bfd_elf64_k1om_vec and
bfd_elf64_k1om_freebsd_vec.
* configure: Regenerated.
* cpu-k1om.c: New.
* elf64-x86-64.c (elf64_k1om_elf_object_p): New.
(bfd_elf64_k1om_vec): Likewise.
(bfd_elf64_k1om_freebsd_vec): Likewise.
* targets.c (bfd_elf64_k1om_vec): New.
(bfd_elf64_k1om_freebsd_vec): Likewise.
(_bfd_target_vector): Add bfd_elf64_k1om_vec and
bfd_elf64_k1om_freebsd_vec.
binutils/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (init_dwarf_regnames): Handle EM_K1OM.
* elfedit.c (elf_machine): Support EM_K1OM.
(elf_class): Likewise.
* readelf.c (guess_is_rela): Handle EM_K1OM.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(get_section_type_name): Likewise.
(get_elf_section_flags): Likewise.
(process_section_headers): Likewise.
(get_symbol_index_type): Likewise.
(is_32bit_abs_reloc): Likewise.
(is_32bit_pcrel_reloc): Likewise.
(is_64bit_abs_reloc): Likewise.
(is_64bit_pcrel_reloc): Likewise.
(is_none_reloc): Likewise.
* doc/binutils.texi: Mention K1OM for elfedit.
binutils/testsuite/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* binutils-all/elfedit.exp: Run elfedit-4.
* binutils-all/elfedit-4.d: New.
gas/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add k1om.
(i386_align_code): Handle PROCESSOR_K1OM.
(check_cpu_arch_compatible): Check EM_K1OM.
(i386_arch): Handle Intel K1OM.
(i386_mach): Return bfd_mach_k1om for Intel K1OM.
(i386_target_format): Return ELF_TARGET_K1OM_FORMAT for Intel
K1OM.
* config/tc-i386.h (ELF_TARGET_K1OM_FORMAT): New.
(processor_type): Add PROCESSOR_K1OM.
* doc/c-i386.texi: Document k1om.
gas/testsuite/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/k1om.d: New.
* gas/i386/k1om-inval.l: Likewise.
* gas/i386/k1om-inval.s: Likewise.
* gas/i386/i386.exp: Run k1om-inval and k1om.
include/elf/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* common.h (EM_K1OM): New.
ld/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.am (ALL_64_EMULATIONS): Add eelf_k1om.o and
eelf_k1om_fbsd.o
(eelf_k1om.c): New.
(eelf_k1om_fbsd.c): Likewise.
* Makefile.in: Regenerated.
* configure.tgt (targ64_extra_emuls): Add elf_k1om if elf_x86_64
is supported. Add elf_k1om_fbsd if elf_x86_64_fbsd is supported.
(targ_extra_emuls): Likewise.
* emulparams/elf_k1om.sh: New.
* emulparams/elf_k1om_fbsd.sh: Likewise.
ld/testsuite/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* ld-x86-64/abs-k1om.d: New.
* ld-x86-64/protected2-k1om.d: Likewise.
* ld-x86-64/protected3-k1om.d: Likewise.
* ld-x86-64/x86-64.exp: Run abs-k1om, protected2-k1om and
protected3-k1om.
opcodes/
2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* configure.in: Handle bfd_k1om_arch.
* configure: Regenerated.
* disassemble.c (disassembler): Handle bfd_k1om_arch.
* i386-dis.c (print_insn): Handle bfd_mach_k1om and
bfd_mach_k1om_intel_syntax.
* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
(cpu_flags): Add CpuK1OM.
* i386-opc.h (CpuK1OM): New.
(i386_cpu_flags): Add cpuk1om.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2011-07-22 20:22:38 +00:00
Nick Clifton
1b93226d63
* arm-dis.c (print_insn_arm): Revert previous, undocumented,
...
accidental change.
2011-07-12 08:45:45 +00:00
Nick Clifton
5d73b1f18f
PR binutils/12329
...
* avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
insns using post-increment addressing.
* avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
2011-07-01 16:11:27 +00:00
H.J. Lu
182ae480cc
Update rorxS.
...
2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (vex_len_table): Update rorxS.
2011-07-01 01:34:35 +00:00
H.J. Lu
4cb0953da2
Fix rorx in BMI2.
...
gas/testsuite/
2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* gas/i386/bmi2.s: Correct rorx tests.
* gas/i386/x86-64-bmi2.s: Likewise.
* gas/i386/bmi2-intel.d: Updated.
* gas/i386/bmi2.d: Likewise.
* gas/i386/x86-64-bmi2-intel.d: Likewise.
* gas/i386/x86-64-bmi2.d: Likewise.
opcodes/
2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* i386-dis.c (vex_len_table): Correct rorxS.
* i386-opc.tbl: Correct rorx.
* i386-tbl.h: Regenerated.
2011-06-30 15:44:55 +00:00
H.J. Lu
906efcbc31
Replace "index" with "i".
...
2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
* tilegx-opc.c (find_opcode): Replace "index" with "i".
* tilepro-opc.c (find_opcode): Likewise.
2011-06-29 20:46:11 +00:00
Richard Sandiford
ceb94aa50d
gas/
...
* config/tc-mips.c (find_altered_mips16_opcode): New function.
(append_insn): Use it.
opcodes/
* mips16-opc.c (jalrc, jrc): Move earlier in file.
2011-06-29 20:42:48 +00:00
H.J. Lu
f7002f424a
Re-indent prefix_table.
...
2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
PREFIX_VEX_0F388E.
2011-06-21 17:56:46 +00:00
Andreas Schwab
563002680c
* Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
...
(MOSTLYCLEANFILES): ... here.
* Makefile.in: Regenerate.
2011-06-17 15:06:46 +00:00
Alan Modra
bcf2cf9fc5
* Makefile.in: Regenerate.
2011-06-14 05:11:52 +00:00
Nick Clifton
aa137e4d51
* Makefile.am (ALL_MACHINES): Add cpu-tilegx.lo and cpu-tilepro.lo.
...
(ALL_MACHINE_CFILES): Add cpu-tilegx.c and cpu-tilepro.c.
(BFD32_BACKENDS): Add elf32-tilegx.lo, elf32-tilepro.lo,
and elfxx-tilegx.lo.
(BFD32_BACKENDS_CFILES): Add elf32-tilegx.c elf32-tilepro.c, and
elfxx-tilegx.c.
(BFD64_BACKENDS): Add elf64-tilegx.lo.
(BFD64_BACKENDS_CFILES): Add elf64-tilegx.c.
* Makefile.in: Regenerate.
* arctures.c (bfd_architecture): Define bfd_arch_tilepro,
bfd_arch_tilegx, bfd_mach_tilepro, bfd_mach_tilegx.
(bfd_arch_info): Add bfd_tilegx_arch, bfd_tilepro_arch.
(bfd_archures_list): Add bfd_tilegx_arch, bfd_tilepro_arch.
bfd-in2.h: Regenerate.
* config.bfd: Handle tilegx-*-* and tilepro-*-*.
* configure.in: Handle bfd_elf32_tilegx_vec, bfd_elf32_tilepro_vec,
and bfd_elf64_tilegx_vec.
* configure: Regenerate.
* elf-bfd.h (enum elf_target_id): Define TILEGX_ELF_DATA and
TILEPRO_ELF_DATA.
* libbfd.h: Regenerate.
* reloc.c: Add BFD_RELOC_TILEPRO_{COPY, GLOB_DAT, JMP_SLOT,
RELATIVE, BROFF_X1, JOFFLONG_X1, JOFFLONG_X1_PLT, IMM8_X0,
IMM8_Y0, IMM8_X1, IMM8_Y1, DEST_IMM8_X1, MT_IMM15_X1, MF_IMM15_X1,
IMM16_X0, IMM16_X1, IMM16_X0_LO, IMM16_X1_LO, IMM16_X0_HI,
IMM16_X1_HI, IMM16_X0_HA, IMM16_X1_HA, IMM16_X0_PCREL,
IMM16_X1_PCREL, IMM16_X0_LO_PCREL, IMM16_X1_LO_PCREL,
IMM16_X0_HI_PCREL, IMM16_X1_HI_PCREL, IMM16_X0_HA_PCREL,
IMM16_X1_HA_PCREL, IMM16_X0_GOT, IMM16_X1_GOT, IMM16_X0_GOT_LO,
IMM16_X1_GOT_LO, IMM16_X0_GOT_HI, IMM16_X1_GOT_HI,
IMM16_X0_GOT_HA, IMM16_X1_GOT_HA, MMSTART_X0, MMEND_X0,
MMSTART_X1, MMEND_X1, SHAMT_X0, SHAMT_X1, SHAMT_Y0, SHAMT_Y1,
IMM16_X0_TLS_GD, IMM16_X1_TLS_GD, IMM16_X0_TLS_GD_LO,
IMM16_X1_TLS_GD_LO, IMM16_X0_TLS_GD_HI, IMM16_X1_TLS_GD_HI,
IMM16_X0_TLS_GD_HA, IMM16_X1_TLS_GD_HA, IMM16_X0_TLS_IE,
IMM16_X1_TLS_IE, IMM16_X0_TLS_IE_LO, IMM16_X1_TLS_IE_LO,
IMM16_X0_TLS_IE_HI, IMM16_X1_TLS_IE_HI, IMM16_X0_TLS_IE_HA,
IMM16_X1_TLS_IE_HA, TLS_DTPMOD32, TLS_DTPOFF32, TLS_TPOFF32}
Add BFD_RELOC_TILEGX_{HW0, HW1, HW2, HW3, HW0_LAST, HW1_LAST,
HW2_LAST, COPY, GLOB_DAT, JMP_SLOT, RELATIVE, BROFF_X1,
JUMPOFF_X1, JUMPOFF_X1_PLT, IMM8_X0, IMM8_Y0, IMM8_X1, IMM8_Y1,
DEST_IMM8_X1, MT_IMM14_X1, MF_IMM14_X1, MMSTART_X0, MMEND_X0,
SHAMT_X0, SHAMT_X1, SHAMT_Y0, SHAMT_Y1, IMM16_X0_HW0,
IMM16_X1_HW0, IMM16_X0_HW1, IMM16_X1_HW1, IMM16_X0_HW2,
IMM16_X1_HW2, IMM16_X0_HW3, IMM16_X1_HW3, IMM16_X0_HW0_LAST,
IMM16_X1_HW0_LAST, IMM16_X0_HW1_LAST, IMM16_X1_HW1_LAST,
IMM16_X0_HW2_LAST, IMM16_X1_HW2_LAST, IMM16_X0_HW0_PCREL,
IMM16_X1_HW0_PCREL, IMM16_X0_HW1_PCREL, IMM16_X1_HW1_PCREL,
IMM16_X0_HW2_PCREL, IMM16_X1_HW2_PCREL, IMM16_X0_HW3_PCREL,
IMM16_X1_HW3_PCREL, IMM16_X0_HW0_LAST_PCREL,
IMM16_X1_HW0_LAST_PCREL, IMM16_X0_HW1_LAST_PCREL,
IMM16_X1_HW1_LAST_PCREL, IMM16_X0_HW2_LAST_PCREL,
IMM16_X1_HW2_LAST_PCREL, IMM16_X0_HW0_GOT, IMM16_X1_HW0_GOT,
IMM16_X0_HW1_GOT, IMM16_X1_HW1_GOT, IMM16_X0_HW2_GOT,
IMM16_X1_HW2_GOT, IMM16_X0_HW3_GOT, IMM16_X1_HW3_GOT,
IMM16_X0_HW0_LAST_GOT, IMM16_X1_HW0_LAST_GOT,
IMM16_X0_HW1_LAST_GOT, IMM16_X1_HW1_LAST_GOT,
IMM16_X0_HW2_LAST_GOT, IMM16_X1_HW2_LAST_GOT, IMM16_X0_HW0_TLS_GD,
IMM16_X1_HW0_TLS_GD, IMM16_X0_HW1_TLS_GD, IMM16_X1_HW1_TLS_GD,
IMM16_X0_HW2_TLS_GD, IMM16_X1_HW2_TLS_GD, IMM16_X0_HW3_TLS_GD,
IMM16_X1_HW3_TLS_GD, IMM16_X0_HW0_LAST_TLS_GD,
IMM16_X1_HW0_LAST_TLS_GD, IMM16_X0_HW1_LAST_TLS_GD,
IMM16_X1_HW1_LAST_TLS_GD, IMM16_X0_HW2_LAST_TLS_GD,
IMM16_X1_HW2_LAST_TLS_GD, IMM16_X0_HW0_TLS_IE,
IMM16_X1_HW0_TLS_IE, IMM16_X0_HW1_TLS_IE, IMM16_X1_HW1_TLS_IE,
IMM16_X0_HW2_TLS_IE, IMM16_X1_HW2_TLS_IE, IMM16_X0_HW3_TLS_IE,
IMM16_X1_HW3_TLS_IE, IMM16_X0_HW0_LAST_TLS_IE,
IMM16_X1_HW0_LAST_TLS_IE, IMM16_X0_HW1_LAST_TLS_IE,
IMM16_X1_HW1_LAST_TLS_IE, IMM16_X0_HW2_LAST_TLS_IE,
IMM16_X1_HW2_LAST_TLS_IE, TLS_DTPMOD64, TLS_DTPOFF64, TLS_TPOFF64,
TLS_DTPMOD32, TLS_DTPOFF32, TLS_TPOFF32}
* targets.c (bfd_elf32_tilegx_vec): Declare.
(bfd_elf32_tilepro_vec): Declare.
(bfd_elf64_tilegx_vec): Declare.
(bfd_target_vector): Add bfd_elf32_tilegx_vec, bfd_elf32_tilepro_vec,
and bfd_elf64_tilegx_vec.
* cpu-tilegx.c: New file.
* cpu-tilepro.c: New file.
* elf32-tilepro.h: New file.
* elf32-tilepro.c: New file.
* elf32-tilegx.c: New file.
* elf32-tilegx.h: New file.
* elf64-tilegx.c: New file.
* elf64-tilegx.h: New file.
* elfxx-tilegx.c: New file.
* elfxx-tilegx.h: New file.
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-tilegx.c and
config/tc-tilepro.c.
(TARGET_CPU_HFILES): Add config/tc-tilegx.h and
config/tc-tilepro.h.
* Makefile.in: Regenerate.
* configure.tgt (tilepro-*-*): New.
(tilegx-*-*): Likewise.
* config/tc-tilegx.c: New file.
* config/tc-tilegx.h: Likewise.
* config/tc-tilepro.h: Likewise.
* config/tc-tilepro.c: Likewise.
* doc/Makefile.am (CPU_DOCS): Add c-tilegx.texi and
c-tilepro.texi.
* doc/Makefile.in: Regenerate.
* doc/all.texi (TILEGX): Define.
(TILEPRO): Define.
* doc/as.texinfo: Add Tile-Gx and TILEPro documentation. Include
c-tilegx.texi and c-tilepro.texi.
* doc/c-tilegx.texi: New.
* doc/c-tilepro.texi: New.
* gas/tilepro/t_constants.s: New file.
* gas/tilepro/t_constants.d: Likewise.
* gas/tilepro/t_insns.s: Likewise.
* gas/tilepro/tilepro.exp: Likewise.
* gas/tilepro/t_insns.d: Likewise.
* gas/tilegx/tilegx.exp: Likewise.
* gas/tilegx/t_insns.d: Likewise.
* gas/tilegx/t_insns.s: Likewise.
* dis-asm.h (print_insn_tilegx): Declare.
(print_insn_tilepro): Likewise.
* tilegx.h: New file.
* tilepro.h: New file.
* common.h: Add EM_TILEGX.
* tilegx.h: New file.
* tilepro.h: New file.
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32tilegx.c and
eelf32tilepro.c.
(ALL_64_EMULATION_SOURCES): Add eelf64tilegx.c.
(eelf32tilegx.c): New target.
(eelf32tilepro.c): Likewise.
(eelf64tilegx.c): Likewise.
* Makefile.in: Regenerate.
* configure.tgt: Handle tilegx-*-* and tilepro-*-*.
* emulparams/elf32tilegx.sh: New file.
* emulparams/elf64tilegx.sh: New file.
* emulparams/elf32tilepro.sh: New file.
* ld-elf/eh5.d: Don't run on tile*.
* ld-srec/srec.exp: xfail on tile*.
* ld-tilegx/external.s: New file.
* ld-tilegx/reloc.d: New file.
* ld-tilegx/reloc.s: New file.
* ld-tilegx/tilegx.exp: New file.
* ld-tilepro/external.s: New file.
* ld-tilepro/reloc.d: New file.
* ld-tilepro/reloc.s: New file.
* ld-tilepro/tilepro.exp: New file.
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
* Makefile.in: Regenerate.
* configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
* configure: Regenerate.
* disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
* po/POTFILES.in: Regenerate.
* tilegx-dis.c: New file.
* tilegx-opc.c: New file.
* tilepro-dis.c: New file.
* tilepro-opc.c: New file.
2011-06-13 15:18:54 +00:00
H.J. Lu
6c30d220f1
Support AVX Programming Reference (June, 2011).
...
gas/
2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* config/tc-i386.c (i386_error): Add invalid_vsib_address and
unsupported_vector_index_register.
(cpu_arch): Add .avx2, .bmi2, .lzcnt and .invpcid.
(check_VecOperands): New.
(match_template): Call check_VecOperands. Handle
invalid_vsib_address and unsupported_vector_index_register.
(build_modrm_byte): Support VecSIB. Check register-only source
operand when two source operands are swapped.
(i386_index_check): Allow Xmm/Ymm index registers.
* doc/c-i386.texi: Document avx2/.avx2, bmi2/.bmi2, lzcnt/.lzcnt
and invpcid./invpcid.
gas/testsuite/
2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* gas/i386/arch-10-1.l: Updated.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.s: Add LZCNT to comments.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10-lzcnt.d: New.
* gas/i386/avx-gather-intel.d: Likewise.
* gas/i386/avx-gather.d: Likewise.
* gas/i386/avx-gather.s: Likewise.
* gas/i386/avx2-intel.d: Likewise.
* gas/i386/avx2.d: Likewise.
* gas/i386/avx2.s: Likewise
* gas/i386/avx256int-intel.d: Likewise.
* gas/i386/avx256int.d: Likewise.
* gas/i386/avx256int.s: Likewise.
* gas/i386/bmi2-intel.d: Likewise.
* gas/i386/bmi2.d: Likewise.
* gas/i386/bmi2.s: Likewise.
* gas/i386/inval-invpcid.l:Likewise.
* gas/i386/inval-invpcid.s: Likewise.
* gas/i386/invpcid-intel.d: Likewise.
* gas/i386/invpcid.d: Likewise.
* gas/i386/invpcid.s: Likewise.
* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
* gas/i386/x86-64-avx-gather-intel.d: Likewise.
* gas/i386/x86-64-avx-gather.d: Likewise.
* gas/i386/x86-64-avx-gather.s: Likewise.
* gas/i386/x86-64-avx2-intel.d: Likewise.
* gas/i386/x86-64-avx2.d: Likewise.
* gas/i386/x86-64-avx2.s: Likewise.
* gas/i386/x86-64-avx256int-intel.d: Likewise.
* gas/i386/x86-64-avx256int.d: Likewise.
* gas/i386/x86-64-avx256int.s: Likewise.
* gas/i386/x86-64-bmi2-intel.d: Likewise.
* gas/i386/x86-64-bmi2.d: Likewise.
* gas/i386/x86-64-bmi2.s: Likewise.
* gas/i386/x86-64-inval-invpcid.l: Likewise.
* gas/i386/x86-64-inval-invpcid.s: Likewise.
* gas/i386/x86-64-invpcid-intel.d: Likewise.
* gas/i386/x86-64-invpcid.d: Likewise.
* gas/i386/x86-64-invpcid.s: Likewise.
opcodes/
2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2011)
* i386-dis.c (XMGatherQ): New.
* i386-dis.c (EXxmm_mb): New.
(EXxmm_mb): Likewise.
(EXxmm_mw): Likewise.
(EXxmm_md): Likewise.
(EXxmm_mq): Likewise.
(EXxmmdw): Likewise.
(EXxmmqd): Likewise.
(VexGatherQ): Likewise.
(MVexVSIBDWpX): Likewise.
(MVexVSIBQWpX): Likewise.
(xmm_mb_mode): Likewise.
(xmm_mw_mode): Likewise.
(xmm_md_mode): Likewise.
(xmm_mq_mode): Likewise.
(xmmdw_mode): Likewise.
(xmmqd_mode): Likewise.
(ymmxmm_mode): Likewise.
(vex_vsib_d_w_dq_mode): Likewise.
(vex_vsib_q_w_dq_mode): Likewise.
(MOD_VEX_0F385A_PREFIX_2): Likewise.
(MOD_VEX_0F388C_PREFIX_2): Likewise.
(MOD_VEX_0F388E_PREFIX_2): Likewise.
(PREFIX_0F3882): Likewise.
(PREFIX_VEX_0F3816): Likewise.
(PREFIX_VEX_0F3836): Likewise.
(PREFIX_VEX_0F3845): Likewise.
(PREFIX_VEX_0F3846): Likewise.
(PREFIX_VEX_0F3847): Likewise.
(PREFIX_VEX_0F3858): Likewise.
(PREFIX_VEX_0F3859): Likewise.
(PREFIX_VEX_0F385A): Likewise.
(PREFIX_VEX_0F3878): Likewise.
(PREFIX_VEX_0F3879): Likewise.
(PREFIX_VEX_0F388C): Likewise.
(PREFIX_VEX_0F388E): Likewise.
(PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
(PREFIX_VEX_0F38F5): Likewise.
(PREFIX_VEX_0F38F6): Likewise.
(PREFIX_VEX_0F3A00): Likewise.
(PREFIX_VEX_0F3A01): Likewise.
(PREFIX_VEX_0F3A02): Likewise.
(PREFIX_VEX_0F3A38): Likewise.
(PREFIX_VEX_0F3A39): Likewise.
(PREFIX_VEX_0F3A46): Likewise.
(PREFIX_VEX_0F3AF0): Likewise.
(VEX_LEN_0F3816_P_2): Likewise.
(VEX_LEN_0F3819_P_2): Likewise.
(VEX_LEN_0F3836_P_2): Likewise.
(VEX_LEN_0F385A_P_2_M_0): Likewise.
(VEX_LEN_0F38F5_P_0): Likewise.
(VEX_LEN_0F38F5_P_1): Likewise.
(VEX_LEN_0F38F5_P_3): Likewise.
(VEX_LEN_0F38F6_P_3): Likewise.
(VEX_LEN_0F38F7_P_1): Likewise.
(VEX_LEN_0F38F7_P_2): Likewise.
(VEX_LEN_0F38F7_P_3): Likewise.
(VEX_LEN_0F3A00_P_2): Likewise.
(VEX_LEN_0F3A01_P_2): Likewise.
(VEX_LEN_0F3A38_P_2): Likewise.
(VEX_LEN_0F3A39_P_2): Likewise.
(VEX_LEN_0F3A46_P_2): Likewise.
(VEX_LEN_0F3AF0_P_3): Likewise.
(VEX_W_0F3816_P_2): Likewise.
(VEX_W_0F3818_P_2): Likewise.
(VEX_W_0F3819_P_2): Likewise.
(VEX_W_0F3836_P_2): Likewise.
(VEX_W_0F3846_P_2): Likewise.
(VEX_W_0F3858_P_2): Likewise.
(VEX_W_0F3859_P_2): Likewise.
(VEX_W_0F385A_P_2_M_0): Likewise.
(VEX_W_0F3878_P_2): Likewise.
(VEX_W_0F3879_P_2): Likewise.
(VEX_W_0F3A00_P_2): Likewise.
(VEX_W_0F3A01_P_2): Likewise.
(VEX_W_0F3A02_P_2): Likewise.
(VEX_W_0F3A38_P_2): Likewise.
(VEX_W_0F3A39_P_2): Likewise.
(VEX_W_0F3A46_P_2): Likewise.
(MOD_VEX_0F3818_PREFIX_2): Removed.
(MOD_VEX_0F3819_PREFIX_2): Likewise.
(VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
(VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
(VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
(VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
(VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
(VEX_LEN_0F3A0E_P_2): Likewise.
(VEX_LEN_0F3A0F_P_2): Likewise.
(VEX_LEN_0F3A42_P_2): Likewise.
(VEX_LEN_0F3A4C_P_2): Likewise.
(VEX_W_0F3818_P_2_M_0): Likewise.
(VEX_W_0F3819_P_2_M_0): Likewise.
(prefix_table): Updated.
(three_byte_table): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(vex_w_table): Likewise.
(mod_table): Likewise.
(putop): Handle "LW".
(intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
(OP_EX): Likewise.
(OP_E_memory): Handle vex_vsib_d_w_dq_mode and
vex_vsib_q_w_dq_mode.
(OP_XMM): Handle vex_vsib_q_w_dq_mode.
(OP_VEX): Likewise.
* i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
(cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
(opcode_modifiers): Add VecSIB.
* i386-opc.h (CpuAVX2): New.
(CpuBMI2): Likewise.
(CpuLZCNT): Likewise.
(CpuINVPCID): Likewise.
(VecSIB128): Likewise.
(VecSIB256): Likewise.
(VecSIB): Likewise.
(i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
(i386_opcode_modifier): Add vecsib.
* i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2011-06-10 21:27:40 +00:00
Quentin Neill
d535accd98
Add CpuF16C to CPU_BDVER2_FLAGS.
...
opcodes/
2011-06-02 Quentin Neill <quentin.neill@amd.com>
* i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
* i386-init.h: Regenerated.
2011-06-03 20:06:20 +00:00
Nick Clifton
f8b960bc80
PR binutils/12752
...
* arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
computing address offsets.
(print_arm_address): Likewise.
(print_insn_arm): Likewise.
(print_insn_thumb16): Likewise.
(print_insn_thumb32): Likewise.
2011-06-03 10:04:03 +00:00
Nathan Sidwell
26d97720ed
gas/
...
* config/tc-arm.c (parse_address_main): Handle -0 offsets.
(encode_arm_addr_mode_2): Set default sign of zero here ...
(encode_arm_addr_mode_3): ... and here.
(encode_arm_cp_address): ... and here.
(md_apply_fix): Use default sign of zero here.
gas/testsuite/
* gas/arm/inst.d: Adjust for signed zero offsets.
* gas/arm/ldst-offset0.d: New test.
* gas/arm/ldst-offset0.s: New test.
* gas/arm/offset-1.d: New test.
* gas/arm/offset-1.s: New test.
ld/testsuite/
Adjust tests for zero offset formatting.
* ld-arm/cortex-a8-fix-bcc-plt.d: Adjust.
* ld-arm/farcall-arm-arm-pic-veneer.d: Adjust.
* ld-arm/farcall-arm-thumb.d: Adjust.
* ld-arm/farcall-group-size2.d: Adjust.
* ld-arm/farcall-group.d: Adjust.
* ld-arm/farcall-mix.d: Adjust.
* ld-arm/farcall-mix2.d: Adjust.
* ld-arm/farcall-mixed-lib-v4t.d: Adjust.
* ld-arm/farcall-mixed-lib.d: Adjust.
* ld-arm/farcall-thumb-arm-blx-pic-veneer.d: Adjust.
* ld-arm/farcall-thumb-arm-pic-veneer.d: Adjust.
* ld-arm/farcall-thumb-thumb.d: Adjust.
* ld-arm/ifunc-10.dd: Adjust.
* ld-arm/ifunc-3.dd: Adjust.
* ld-arm/ifunc-4.dd: Adjust.
* ld-arm/ifunc-5.dd: Adjust.
* ld-arm/ifunc-6.dd: Adjust.
* ld-arm/ifunc-7.dd: Adjust.
* ld-arm/ifunc-8.dd: Adjust.
* ld-arm/jump-reloc-veneers-long.d: Adjust.
* ld-arm/tls-longplt-lib.d: Adjust.
* ld-arm/tls-thumb1.d: Adjust.
opcodes/
* arm-dis.c (print_insn_coprocessor): Explicitly print #-0
as address offset.
(print_arm_address): Likewise. Elide positive #0 appropriately.
(print_insn_arm): Likewise.
2011-06-02 15:32:10 +00:00
Nick Clifton
cc643b88f1
Fix spelling mistakes.
2011-06-02 13:43:24 +00:00
Andreas Krebbel
c8fa16ed5a
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
...
* config/tc-s390.c (md_gather_operands): Fix check for floating
register pair operands.
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* opcode/s390.h: Replace S390_OPERAND_REG_EVEN with
S390_OPERAND_REG_PAIR.
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.c: Replace S390_OPERAND_REG_EVEN with
S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
* s390-opc.txt: Fix cxr instruction type.
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/esa-g5.d: Fix fp register pair operands.
* gas/s390/esa-g5.s: Likewise.
* gas/s390/zarch-z196.d: Likewise.
* gas/s390/zarch-z196.s: Likewise.
* gas/s390/zarch-z9-109.d: Likewise.
* gas/s390/zarch-z9-109.s: Likewise.
* gas/s390/zarch-z9-ec.d: Likewise.
* gas/s390/zarch-z9-ec.s: Likewise.
2011-05-24 16:13:31 +00:00
Andreas Krebbel
5e4b319cdc
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
...
* config/tc-s390.c (md_gather_operands): Emit an error for odd
numbered registers used as register pair operand.
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* opcode/s390.h: Add S390_OPCODE_REG_EVEN flag.
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.c: Add new instruction types marking register pair
operands.
* s390-opc.txt: Match instructions having register pair operands
to the new instruction types.
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/esa-g5.d: Fix register pair operands.
* gas/s390/esa-g5.s: Likewise.
* gas/s390/esa-z9-109.d: Likewise.
* gas/s390/esa-z9-109.s: Likewise.
* gas/s390/zarch-z196.d: Likewise.
* gas/s390/zarch-z196.s: Likewise.
* gas/s390/zarch-z9-109.d: Likewise.
* gas/s390/zarch-z9-109.s: Likewise.
* gas/s390/zarch-z900.d: Likewise.
* gas/s390/zarch-z900.s: Likewise.
* gas/s390/zarch-z990.d: Likewise.
* gas/s390/zarch-z990.s: Likewise.
2011-05-24 13:33:57 +00:00
Nick Clifton
fda544a25c
* v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
...
operands.
2011-05-19 11:10:59 +00:00
Quentin Neill
4cab4add34
2011-05-10 Quentin Neill <quentin.neill@amd.com>
...
gas/
* config/tc-i386.c (cpu_arch): Add bdver2 and rename
PROCESSOR_BDVER1 to PROCESSOR_BDVER.
(i386_align_code): Rename PROCESSOR_BDVER1.
(processor_type): Ditto.
* doc/c-i386.texi: Add bdver2.
opcodes/
* i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
* i386-init.h: Regenerated.
gas/testsuite/
* gas/i386/i386.exp: Add new bdver2 test cases.
* gas/i386/nops-1-bdver2.d: New.
* gas/i386/x86-64-nops-1-bdver2.d: New.
2011-05-11 22:35:20 +00:00
Nick Clifton
b4e7b88557
Updated Danish, Esperanto and French translations.
2011-04-27 10:02:27 +00:00
Alan Modra
2f7f771012
* ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
2011-04-25 23:11:21 +00:00
DJ Delorie
9887672fa6
* rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
...
* rx-decode.c: Regenerate.
2011-04-21 05:48:06 +00:00
H.J. Lu
3251b3756a
Regenerate i386-init.h.
...
2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
* i386-init.h: Regenerated.
2011-04-20 14:27:34 +00:00
Quentin Neill
b13a3ca683
* i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
...
from bdver1 flags.
2011-04-19 23:45:17 +00:00
Nick Clifton
00bbc0bdc6
* config/tc-arm.c (v7m_psrs): Revert previous delta.
...
* gas/arm/mrs-msr-thumb-v7e-m.s: Restore name of basepri_max
register.
* gas/arm/mrs-msr-thumb-v7e-m.d: Likewise.
* gas/arm/arch7.d: Likewise.
* gas/arm/arch7.s: Likewise.
* arm-dis.c: Revert previous reversion.
2011-04-19 07:44:12 +00:00
Nick Clifton
ac7f631be1
* gas/arm/arch7.s: Fix typo basepri_max should be basepri_mask.
...
* gas/arm/mrs-msr-thumb-v7e-m.s: Likewise.
* gas/arm/arch7.d: Update expected disassembly.
* gas/arm/attr-march-armv7.d: Remove Microcontroller tag.
* gas/arm/blx-bad.d: Only run for ELF based targets.
* gas/arm/mrs-msr-thumb-v6t2.d: Likewise.
* gas/arm/vldm-arm.d: Likewise.
* gas/arm/mrs-msr-thumb-v7-m.d: Likewise.
Remove qualifiers from PSR and IAPSR regsiter names.
* gas/arm/mrs-msr-thumb-v7e-m.d: Likewise.
* gas/arm/thumb2_bcond.d: Update expected disassembly to allow for
relaxing of branch insns.
* gas/arm/thumb32.d: Fix whitespace problems in disassembly.
* config/tc-arm.c (parse_psr): Use selected_cpu not cpu_variant to
detect M-profile targets.
(do_t_swi): Exclude v7 and higher variants from arm_ext_os test.
(v7m_psrs): Fix typo: basepri_max should be basepri_mask.
* arm-dis.c (psr_name): Revert previous delta.
* arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
2011-04-19 07:27:32 +00:00
Nick Clifton
7d063384af
* v850-dis.c (disassemble): Always print a closing square brace if
...
an opening square brace was printed.
2011-04-13 13:20:24 +00:00
Nick Clifton
32a946987b
PR binutils/12534
...
* arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
patterns.
(print_insn_thumb32): Handle %L.
* gas/arm/thumb32.s: Add PC relative LDRD and STRD insns.
* gas/arm/thumb32.l: Update expected output.
* gas/arm/thumb32.d: Update expected disassembly.
2011-04-12 16:01:48 +00:00
Julian Brown
d2cd120565
gas/
...
* config/tc-arm.c (parse_psr): Add LHS argument. Improve support
for *APSR bitmasks.
(operand_parse_code): Replace OP_PSR with OP_wPSR and OP_rPSR.
Remove OP_RVC_PSR.
(parse_operands): Likewise.
(do_mrs): Tweak error message for constraint.
(do_t_mrs): Update constraints for changes to APSR support.
(do_t_msr): Likewise. Don't set PSR_f flag here.
(psrs): Remove "g", "nzcvq", "nzcvqg".
(insns): Tweak entries for msr and mrs instructions.
opcodes/
* arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
(print_insn_thumb32): Add APSR bitmask support.
gas/testsuite/
* gas/arm/mrs-msr-thumb-v7-m.s: New.
* gas/arm/mrs-msr-thumb-v7-m.d: New.
* gas/arm/mrs-msr-thumb-v7-m-bad.d: New.
* gas/arm/mrs-msr-thumb-v7-m-bad.l: New.
* gas/arm/mrs-msr-thumb-v7-m-bad.s: New.
* gas/arm/mrs-msr-thumb-v7e-m.d: New.
* gas/arm/mrs-msr-thumb-v7e-m.s: New.
* gas/arm/mrs-msr-arm-v7-a-bad.d: New.
* gas/arm/mrs-msr-arm-v7-a-bad.l: New.
* gas/arm/mrs-msr-arm-v7-a-bad.s: New.
* gas/arm/mrs-msr-arm-v7-a.d: New.
* gas/arm/mrs-msr-arm-v7-a.s: New.
* gas/arm/mrs-msr-arm-v6.d: New.
* gas/arm/mrs-msr-arm-v6.s: New.
* gas/arm/mrs-msr-thumb-v6t2.d: New.
* gas/arm/mrs-msr-thumb-v6t2.s: New.
* gas/arm/arch7.d: Fix typo in disassembly for BASEPRI_MAX,
bitmasks for IAPSR etc.
* gas/arm/arch7.s: Specify bitmask for APSR writes.
* gas/arm/archv6m.s: Likewise.
* msr-imm-bad.l: Tweak expected disassembly in error message.
* msr-reg-bad.l: Likewise.
* msr-imm.d: Tweak expected disassembly.
* msr-reg.d: Likewise.
* msr-reg-thumb.d: Likewise.
* msr-imm.s: Specify bitmask on APSR writes.
* msr-reg.s: Add comment about deprecated usage.
2011-04-11 18:49:06 +00:00
Paul Brook
1fbaefec00
2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
...
opcodes/
* arm-dis.c (print_insn): init vars moved into private_data structure.
binutils/testsuite/
* binutils-all/arm/simple.s: Demo issue with objdump with
multiple input files
* binutils-all/arm/objdump.exp: added new ARM test case code
2011-04-08 11:42:19 +00:00
Mike Frysinger
67171547aa
opcodes: blackfin: ignore (M) on MAC0-only dsp mac funcs
...
If the MAC1 part of the insn is disabled, then the (M) flag is ignored.
Rather than include it in the decode, move the MM clearing to the MAC0
portion of the code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 05:27:39 +00:00
Eric B. Weddington
8cc66334fa
/bfd:
...
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* archures.c: Add AVR XMEGA architecture information.
* cpu-avr.c (arch_info_struct): Likewise.
* elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise.
(elf32_avr_object_p): Likewise.
/gas:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (struct avr_opcodes_s): Add opcode field.
(AVR_INSN): Change definition to match.
(avr_opcodes): Likewise, change to match.
(mcu_types): Add XMEGA architecture names and new XMEGA device names.
(md_show_usage): Add XMEGA architecture names.
(avr_operand): Add 'E' constraint for DES instruction of XMEGA devices.
Add support for SPM Z+ instruction.
* doc/c-avr.texi: Add documentation for XMEGA architectures and
devices.
/include/opcode:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
New instruction set flags.
(AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
/ld:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures.
(eavrxmega?.c): Likewise.
* configure.tgt (targ_extra_emuls): Likewise.
* emulparams/avrxmega1.sh: New file.
* emulparams/avrxmega2.sh: Likewise.
* emulparams/avrxmega3.sh: Likewise.
* emulparams/avrxmega4.sh: Likewise.
* emulparams/avrxmega5.sh: Likewise.
* emulparams/avrxmega6.sh: Likewise.
* emulparams/avrxmega7.sh: Likewise.
* emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation):
Add avrxmega6, avrxmega7 to list of architectures for no stubs.
/opcodes:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
post-increment to support LPM Z+ instruction. Add support for 'E'
constraint for DES instruction.
(print_insn_avr): Adjust calls to avr_operand. Rename variable.
2011-03-22 18:10:48 +00:00
Richard Sandiford
34e77a920a
include/elf/
...
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
2011-03-14 16:04:16 +00:00
Richard Sandiford
35fc36a8d6
include/elf/
...
* internal.h (elf_internal_sym): Add st_target_internal.
* arm.h (arm_st_branch_type): New enum.
(ARM_SYM_BRANCH_TYPE): New macro.
bfd/
* elf-bfd.h (elf_link_hash_entry): Add target_internal.
* elf.c (swap_out_syms): Set st_target_internal for each
Elf_Internal_Sym.
* elfcode.h (elf_swap_symbol_in): Likewise.
* elf32-i370.c (i370_elf_finish_dynamic_sections): Likewise.
* elf32-sh-symbian.c (sh_symbian_relocate_section): Likewise.
* elf64-sparc.c (elf64_sparc_output_arch_syms): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise.
* elflink.c (elf_link_output_extsym): Likewise.
(bfd_elf_final_link): Likewise.
(elf_link_add_object_symbols): Copy st_target_internal
to the hash table if we see a definition.
(_bfd_elf_copy_link_hash_symbol_type): Copy target_internal.
* elf32-arm.c (elf32_arm_stub_hash_entry): Replace st_type with
a branch_type field.
(a8_erratum_fix, a8_erratum_reloc): Likewise.
(arm_type_of_stub): Replace actual_st_type with an
actual_branch_type parameter.
(arm_build_one_stub): Use branch types rather than st_types to
determine the type of branch.
(cortex_a8_erratum_scan): Likewise.
(elf32_arm_size_stubs): Likewise.
(bfd_elf32_arm_process_before_allocation): Likewise.
(allocate_dynrelocs_for_symbol): Likewise.
(elf32_arm_finish_dynamic_sections): Likewise.
(elf32_arm_final_link_relocate): Replace sym_flags parameter with
a branch_type parameter.
(elf32_arm_relocate_section): Update call accordingly.
(elf32_arm_adjust_dynamic_symbol): Don't check STT_ARM_TFUNC.
(elf32_arm_output_map_sym): Initialize st_target_internal.
(elf32_arm_output_stub_sym): Likewise.
(elf32_arm_symbol_processing): Delete.
(elf32_arm_swap_symbol_in): Convert STT_ARM_TFUNCs into STT_FUNCs.
Use st_target_internal to record the branch type.
(elf32_arm_swap_symbol_out): Use st_target_internal to test for
Thumb functions.
(elf32_arm_is_function_type): Delete.
(elf_backend_symbol_processing): Likewise.
(elf_backend_is_function_type): Likewise.
gas/
* config/tc-arm.c (arm_adjust_symtab): Set the branch type
for Thumb symbols.
ld/
* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Check
eh->target_internal.
opcodes/
* arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
Use branch types instead.
(print_insn): Likewise.
2011-03-14 15:55:04 +00:00
Maciej W. Rozycki
0067d8fc73
opcodes/
...
* mips-opc.c (mips_builtin_opcodes): Correct register use
annotation of "alnv.ps".
gas/testsuite/
* gas/mips/alnv_ps-swap.d: New test for ALNV.PS instruction
branch swapping.
* gas/mips/alnv_ps-swap.s: Source for the new test.
* gas/mips/mips.exp: Run the new test.
2011-02-28 16:34:39 +00:00
Maciej W. Rozycki
3eebd5eb03
gas/
...
* config/tc-mips.c (macro): Handle M_PREF_AB.
include/opcode/
* mips.h (M_PREF_AB): New enum value.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
2011-02-28 16:06:51 +00:00
Maciej W. Rozycki
89c0d58cff
Swap ChangeLog entries.
2011-02-28 16:03:38 +00:00
Mike Frysinger
500cccad3b
opcodes: blackfin: drop null/nul checks in OUTS
...
Parts of the disassembler rely on the disasm info never being NULL (such
as being able to read memory to disassemble in the first place). So drop
useless null checks in the OUTS helper.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-22 20:52:31 +00:00
Mike Frysinger
f5caf9f434
opcodes: blackfin: use OUTS helper
...
We have an OUTS helper to handle outf fprintf_func logic, so conver the
few places not using it over.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-22 20:51:42 +00:00
Mike Frysinger
e5bc42655d
opcodes: blackfin: clean up saved_state
...
Mark the state static, punt unused members, unify indexable register
lookups, and abort when there is a register lookup failure. Otherwise
we return NULL and the calling code assumes a valid pointer is returned.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-20 01:26:14 +00:00
Mike Frysinger
602427c4af
opcodes: blackfin: fix style
...
Non-functional thrashing to the GNU style.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-14 17:12:05 +00:00
Mike Frysinger
298c1ec2a0
opcodes: blackfin: catch invalid loopsetup insns
...
The LoopSetup insn is only valid when the reg field is 0-7, so
don't go decoding it incorrectly when reg is 8-15.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-14 05:21:04 +00:00
Ralf Wildenhues
822ce8ee21
Remove freebsd1 from libtool.m4 macros and config.rpath.
...
/:
Import from Libtool and gnulib:
2011-01-27 Gerald Pfeifer <gerald@pfeifer.com>
Prepare for supporting FreeBSD 10.
* config.rpath: Remove handling of freebsd1* which soon would
match FreeBSD 10.0.
2011-01-20 Gerald Pfeifer <gerald@pfeifer.com> (tiny change)
Remove support for FreeBSD 1.x.
* libtool.m4 (_LT_LINKER_SHLIBS)
(_LT_SYS_DYNAMIC_LINKER): Remove handling of freebsd1* which
soon would incorrectly match FreeBSD 10.0.
bfd/:
* configure: Regenerate.
gas/:
* configure: Regenerate.
ld/:
* configure: Regenerate.
opcodes/:
* configure: Regenerate.
binutils/:
* configure: Regenerate.
gprof/:
* configure: Regenerate.
2011-02-13 21:00:14 +00:00
Mike Frysinger
13c02f06ff
opcodes: blackfin: fix decoding of ABS
...
The single cycle dual mac ABS insn was incorrectly decoding the mac1
part of the insn.
Once we fix the decode, update the gas tests to have the correct output.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-13 18:55:22 +00:00
Mike Frysinger
4db6639409
opcodes: blackfin: fix decoding of dsp mult insns
...
When assigning to a register half, the mac0 part of the mult insn
was not decoding properly. It would always show a full dreg instead
of the dreg low half.
Once we fix the disassembler, we have to update a few of the gas
tests as their previous expected output was incorrect.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-13 18:54:49 +00:00
Mike Frysinger
36f446111a
gas/opcodes: blackfin: punt BYTEOP2M insn support
...
The BYTEOP2M insn was part of the initial Blackfin designs, but never made
it into any actual silicon. So punt support for it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-13 18:53:16 +00:00
Mike Frysinger
9805c0a5b6
opcodes: blackfin: add missing space after PRNT insn
...
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-12 19:38:11 +00:00
Mike Frysinger
43a6aa65fe
opcodes: blackfin: drop "GP" register
...
There never was a "GP" register, so punt it from the decode map. It's
a hold over from a very old processor definition and never made it into
actual silicon.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-12 19:37:32 +00:00
Mike Frysinger
26bb3ddd50
gas/opcodes: blackfin: move dsp mac func defines to common header
...
The mmod field is decoded in a few places (gas/opcodes/sim), so move it to
a common place to avoid duplication.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-12 19:36:31 +00:00
Mike Frysinger
69b8ea4abd
opcodes: blackfin: constify register names
...
Constify the array itself since it need not be writable.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-11 19:03:27 +00:00
Michael Snyder
42d5f9c6ef
2011-02-09 Michael Snyder <msnyder@vmware.com>
...
* i386-dis.c (OP_J): Parenthesize expression to prevent
truncated addresses.
(print_insn): Fix indentation off-by-one.
2011-02-09 18:43:41 +00:00
Nick Clifton
4be0c94123
Updated Danish translation.
2011-02-01 13:14:40 +00:00
Alan Modra
6b069ee70d
* ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
2011-01-21 00:53:11 +00:00
H.J. Lu
e3949f17f3
Properly sign-extend byte.
...
gas/testsuite/
2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/intel.d: Updated.
* gas/i386/opcode-intel.d: Likewise.
* gas/i386/opcode-suffix.d: Likewise.
* gas/i386/opcode.d: Likewise.
opcodes/
2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (sIbT): New.
(b_T_mode): Likewise.
(dis386): Replace sIb with sIbT on "pushT".
(x86_64_table): Replace sIb with Ib on "aam" and "aad".
(OP_sI): Handle b_T_mode. Properly sign-extend byte.
2011-01-18 17:08:13 +00:00
Jan Kratochvil
752573b292
opcodes/
...
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated.
2011-01-18 14:14:46 +00:00
Quentin Neill
2a2a0f38e7
Add support for TBM instructions.
...
gas/
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS.
* doc/c-i386.texi (i386-TBM): New section.
opcodes/
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* i386-dis.c (REG_XOP_TBM_01): New.
(REG_XOP_TBM_02): New.
(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
entries, and add bextr instruction.
* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
(cpu_flags): Add CpuTBM.
* i386-opc.h (CpuTBM) New.
(i386_cpu_flags): Add bit cputbm.
* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
blcs, blsfill, blsic, t1mskc, and tzmsk.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated
gas/testsuite
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* gas/i386/tbm.s: New.
* gas/i386/tbm.d: New.
* gas/i386/tbm-intel.d: New.
* gas/i386/x86-64-tbm.s: New.
* gas/i386/x86-64-tbm.d: New.
* gas/i386/x86-64-tbm-intel.d: New.
* gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern.
* gas/i386/arch-10.s: Add a TBM instruction.
* gas/i386/arch-10-1.l: Add TBM instruction pattern.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
2011-01-17 18:40:36 +00:00
DJ Delorie
90d6ff629e
* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
2011-01-12 07:06:29 +00:00
Mingjie Xing
c95354ed13
Take unadjusted offset for loongson3a specific instructions.
2011-01-11 07:22:09 +00:00
Nick Clifton
f74656046a
* po/da.po: Updated Danish translation.
2011-01-10 13:51:10 +00:00
Nathan Sidwell
639e30d297
gas/testsuite/
...
* gas/arm/blx-bad.s: New.
* gas/arm/blx-bad.d: New.
opcodes/
* arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
2011-01-06 14:30:43 +00:00
H.J. Lu
f12dc42220
Implement BMI instructions.
2011-01-05 00:16:57 +00:00
H.J. Lu
cb21baef77
Add VexGdq.
...
2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (VexGdq): New.
(OP_VEX): Handle dq_mode.
2011-01-04 20:53:32 +00:00
H.J. Lu
4fb3aee212
Update copyright in comments to 2011.
2011-01-01 21:42:17 +00:00
H.J. Lu
0db46eb403
Update copyright to 2011.
...
binutils/
2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
* version.c (print_version): Update copyright to 2011.
gas/
2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
* gas.c (parse_args): Update copyright to 2011.
gold/
2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
* version.cc (print_version): Update copyright to 2011.
ld/
2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
* ldver.c (ldversion): Update copyright to 2011.
opcodes/
2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (process_copyright): Update copyright to 2011.
2011-01-01 20:55:48 +00:00
H.J. Lu
9e9e082043
Rotate binutils ChangeLogs.
2011-01-01 16:43:53 +00:00
Dave Anglin
3c853d9313
PR gas/11395
...
* config/tc-hppa.c (pa_ip): Revert last change. Add variable need_cond
to determine whether a 64-bit condition is needed for 'A' and 'S'
conditions. Default to 32-bit never condition for logical and unit
instructions. Add error message for missing branch on bit condition.
* hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
"bb" entries.
* hppa-dis.c (compare_cond_64_names): Change never condition to ",*".
(add_cond_64_names): Likewise.
(logical_cond_64_names): Likewise.
(unit_cond_64_names): Likewise.
2010-12-31 16:43:46 +00:00
H.J. Lu
351f65ca26
Add x86-64 ILP32 support.
...
bfd/
2010-12-30 H.J. Lu <hongjiu.lu@intel.com>
* archures.c (bfd_mach_x64_32): New.
(bfd_mach_x64_32_intel_syntax): Likewise.
* bfd-in2.h: Regenerated.
* config.bfd (targ64_selvecs): Add bfd_elf32_x86_64_vec for
i[3-7]86-*-linux-*.
(targ_selvecs): Add bfd_elf32_x86_64_vec for x86_64-*-linux-*.
* configure.in: Support bfd_elf32_x86_64_vec.
* configure: Regenerated.
* cpu-i386.c (bfd_x64_32_arch_intel_syntax): New.
(bfd_x64_32_arch): Likewise.
* elf-bfd.h (elf_append_rela): New prototype.
(elf_append_rel): Likewise.
(elf64_r_info): Likewise.
(elf32_r_info): Likewise.
(elf64_r_sym): Likewise.
(elf32_r_sym): Likewise.
* elf64-x86-64.c (ABI_64_P): New.
(elf_x86_64_info_to_howto): Replace ELF64_R_TYPE with
ELF32_R_TYPE. Replace ELF64_ST_TYPE with ELF_ST_TYPE.
(elf_x86_64_check_tls_transition):Likewise.
(elf_x86_64_check_relocs): Likewise.
(elf_x86_64_gc_mark_hook):Likewise.
(elf_x86_64_gc_sweep_hook): Likewise.
(elf_x86_64_relocate_section): Likewise.
(elf_x86_64_reloc_type_class): Likewise.
(ELF_DYNAMIC_INTERPRETER): Renamed to ...
(ELF64_DYNAMIC_INTERPRETER): This.
(ELF32_DYNAMIC_INTERPRETER): New.
(elf_x86_64_link_hash_table): Add r_info, r_sym, swap_reloca_out,
dynamic_interpreter and dynamic_interpreter_size.
(elf_x86_64_get_local_sym_hash): Replace ELF64_R_SYM with
htab->r_sym. Replace ELF64_R_INFO with htab->r_info.
(elf_x86_64_get_local_sym_hash): Likewise.
(elf_x86_64_check_tls_transition):Likewise.
(elf_x86_64_check_relocs): Likewise.
(elf_x86_64_gc_mark_hook):Likewise.
(elf_x86_64_gc_sweep_hook): Likewise.
(elf_x86_64_relocate_section): Likewise.
(elf_x86_64_finish_dynamic_symbol): Likewise.
(elf_x86_64_finish_local_dynamic_symbol): Likewise.
(elf_x86_64_link_hash_table_create): Initialize r_info, r_sym,
swap_reloca_out, dynamic_interpreter and dynamic_interpreter_size.
(elf_x86_64_check_relocs): Check ABI_64_P when requesting for
PIC.
(elf_x86_64_relocate_section): Likewise.
(elf64_x86_64_adjust_dynamic_symbol): Replace sizeof
(Elf64_External_Rela) with bed->s->sizeof_rela.
(elf64_x86_64_allocate_dynrelocs): Likewise.
(elf64_x86_64_size_dynamic_sections): Likewise.
(elf64_x86_64_finish_dynamic_symbol): Likewise.
(elf64_x86_64_append_rela): Removed.
(elf32_x86_64_elf_object_p): New.
Add bfd_elf32_x86_64_vec.
* elf64-x86-64.c (elf64_x86_64_xxx): Renamed to ...
(elf_x86_64_xxx): This.
* elflink.c (bfd_elf_final_link): Check ELF file class on error.
(elf_append_rela): New.
(elf_append_rel): Likewise.
(elf64_r_info): Likewise.
(elf32_r_info): Likewise.
(elf64_r_sym): Likewise.
(elf32_r_sym): Likewise.
* targets.c (bfd_elf32_x86_64_vec): New.
(_bfd_target_vector): Add bfd_elf32_x86_64_vec.
gas/
2010-12-30 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (x86_elf_abi): New.
(i386_mach): Return bfd_mach_x64_32 for ILP32.
(OPTION_N32): Likewise.
(md_longopts): Add "n32" for ELF.
(md_parse_option): Handle OPTION_N32.
(md_show_usage): Add --n32.
(i386_target_format): Update and check x86_elf_abi.
* config/tc-i386.h (ELF_TARGET_FORMAT32): New.
* doc/as.texinfo: Document --n32.
* doc/c-i386.texi: Likewise.
gas/testsuite/
2010-12-30 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/ilp32/lns/ilp32.exp: New.
* gas/i386/ilp32/lns/lns-common-1.d: Likewise.
* gas/i386/ilp32/lns/lns-duplicate.d: Likewise.
* gas/i386/ilp32/cfi/cfi-common-1.d: New.
* gas/i386/ilp32/cfi/cfi-common-2.d: Likewise.
* gas/i386/ilp32/cfi/cfi-common-3.d: Likewise.
* gas/i386/ilp32/cfi/cfi-common-4.d: Likewise.
* gas/i386/ilp32/cfi/cfi-common-5.d: Likewise.
* gas/i386/ilp32/cfi/cfi-common-6.d: Likewise.
* gas/i386/ilp32/cfi/cfi-common-7.d: Likewise.
* gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
* gas/i386/ilp32/cfi/ilp32.exp: Likewise.
* gas/i386/ilp32/elf/ehopt0.d: Likewise.
* gas/i386/ilp32/elf/equ-reloc.d: Likewise.
* gas/i386/ilp32/elf/file.d: Likewise.
* gas/i386/ilp32/elf/group0a.d: Likewise.
* gas/i386/ilp32/elf/group0b.d: Likewise.
* gas/i386/ilp32/elf/group1a.d: Likewise.
* gas/i386/ilp32/elf/group1b.d: Likewise.
* gas/i386/ilp32/elf/ifunc-1.d: Likewise.
* gas/i386/ilp32/elf/ilp32.exp: Likewise.
* gas/i386/ilp32/elf/redef.d: Likewise.
* gas/i386/ilp32/elf/section0.d: Likewise.
* gas/i386/ilp32/elf/section1.d: Likewise.
* gas/i386/ilp32/elf/section3.d: Likewise.
* gas/i386/ilp32/elf/section4.d: Likewise.
* gas/i386/ilp32/elf/section6.d: Likewise.
* gas/i386/ilp32/elf/section7.d: Likewise.
* gas/i386/ilp32/elf/struct.d: Likewise.
* gas/i386/ilp32/elf/symtab.d: Likewise.
* gas/i386/ilp32/elf/symver.d: Likewise.
* gas/i386/ilp32/ilp32.exp: New.
* gas/i386/ilp32/immed64.d: Likewise.
* gas/i386/ilp32/mixed-mode-reloc64.d: Likewise.
* gas/i386/ilp32/reloc64.d: Likewise.
* gas/i386/ilp32/rex.d: Likewise.
* gas/i386/ilp32/rexw.d: Likewise.
* gas/i386/ilp32/svme64.d: Likewise.
* gas/i386/ilp32/x86-64-addr32.d: Likewise.
* gas/i386/ilp32/x86-64-addr32-intel.d: Likewise.
* gas/i386/ilp32/x86-64-aes.d: Likewise.
* gas/i386/ilp32/x86-64-aes-intel.d: Likewise.
* gas/i386/ilp32/x86-64-amdfam10.d: Likewise.
* gas/i386/ilp32/x86-64-arch-1.d: Likewise.
* gas/i386/ilp32/x86-64-arch-2.d: Likewise.
* gas/i386/ilp32/x86-64-avx.d: Likewise.
* gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
* gas/i386/ilp32/x86-64-avx-swap.d: Likewise.
* gas/i386/ilp32/x86-64-avx-swap-intel.d: Likewise.
* gas/i386/ilp32/x86-64-branch.d: Likewise.
* gas/i386/ilp32/x86-64-cbw.d: Likewise.
* gas/i386/ilp32/x86-64-cbw-intel.d: Likewise.
* gas/i386/ilp32/x86-64-clmul.d: Likewise.
* gas/i386/ilp32/x86-64-clmul-intel.d: Likewise.
* gas/i386/ilp32/x86-64-crc32.d: Likewise.
* gas/i386/ilp32/x86-64-crc32-intel.d: Likewise.
* gas/i386/ilp32/x86-64-crx.d: Likewise.
* gas/i386/ilp32/x86-64-crx-suffix.d: Likewise.
* gas/i386/ilp32/x86-64.d: Likewise.
* gas/i386/ilp32/x86-64-disp.d: Likewise.
* gas/i386/ilp32/x86-64-disp-intel.d: Likewise.
* gas/i386/ilp32/x86-64-drx.d: Likewise.
* gas/i386/ilp32/x86-64-drx-suffix.d: Likewise.
* gas/i386/ilp32/x86-64-ept.d: Likewise.
* gas/i386/ilp32/x86-64-ept-intel.d: Likewise.
* gas/i386/ilp32/x86-64-fma4.d: Likewise.
* gas/i386/ilp32/x86-64-fma.d: Likewise.
* gas/i386/ilp32/x86-64-fma-intel.d: Likewise.
* gas/i386/ilp32/x86-64-gidt.d: Likewise.
* gas/i386/ilp32/x86-64-ifunc.d: Likewise.
* gas/i386/ilp32/x86-64-intel64.d: Likewise.
* gas/i386/ilp32/x86-64-io.d: Likewise.
* gas/i386/ilp32/x86-64-io-intel.d: Likewise.
* gas/i386/ilp32/x86-64-io-suffix.d: Likewise.
* gas/i386/ilp32/x86-64-localpic.d: Likewise.
* gas/i386/ilp32/x86-64-mem.d: Likewise.
* gas/i386/ilp32/x86-64-mem-intel.d: Likewise.
* gas/i386/ilp32/x86-64-movbe.d: Likewise.
* gas/i386/ilp32/x86-64-movbe-intel.d: Likewise.
* gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise.
* gas/i386/ilp32/x86-64-nops-1.d: Likewise.
* gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise.
* gas/i386/ilp32/x86-64-nops-1-nocona.d: Likewise.
* gas/i386/ilp32/x86-64-nops-1-pentium.d: Likewise.
* gas/i386/ilp32/x86-64-nops-2.d: Likewise.
* gas/i386/ilp32/x86-64-nops-3.d: Likewise.
* gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise.
* gas/i386/ilp32/x86-64-nops-4.d: Likewise.
* gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise.
* gas/i386/ilp32/x86-64-nops-5.d: Likewise.
* gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise.
* gas/i386/ilp32/x86-64-nops.d: Likewise.
* gas/i386/ilp32/x86-64-opcode.d: Likewise.
* gas/i386/ilp32/x86-64-opcode-inval.d: Likewise.
* gas/i386/ilp32/x86-64-opcode-inval-intel.d: Likewise.
* gas/i386/ilp32/x86-64-opts.d: Likewise.
* gas/i386/ilp32/x86-64-opts-intel.d: Likewise.
* gas/i386/ilp32/x86-64-pcrel.d: Likewise.
* gas/i386/ilp32/x86-64-reg.d: Likewise.
* gas/i386/ilp32/x86-64-reg-intel.d: Likewise.
* gas/i386/ilp32/x86-64-rep.d: Likewise.
* gas/i386/ilp32/x86-64-rep-suffix.d: Likewise.
* gas/i386/ilp32/x86-64-rip.d: Likewise.
* gas/i386/ilp32/x86-64-rip-intel.d: Likewise.
* gas/i386/ilp32/x86-64-sib.d: Likewise.
* gas/i386/ilp32/x86-64-sib-intel.d: Likewise.
* gas/i386/ilp32/x86-64-simd.d: Likewise.
* gas/i386/ilp32/x86-64-simd-intel.d: Likewise.
* gas/i386/ilp32/x86-64-simd-suffix.d: Likewise.
* gas/i386/ilp32/x86-64-sse2avx.d: Likewise.
* gas/i386/ilp32/x86-64-sse2avx-opts.d: Likewise.
* gas/i386/ilp32/x86-64-sse2avx-opts-intel.d: Likewise.
* gas/i386/ilp32/x86-64-sse3.d: Likewise.
* gas/i386/ilp32/x86-64-sse4_1.d: Likewise.
* gas/i386/ilp32/x86-64-sse4_1-intel.d: Likewise.
* gas/i386/ilp32/x86-64-sse4_2.d: Likewise.
* gas/i386/ilp32/x86-64-sse4_2-intel.d: Likewise.
* gas/i386/ilp32/x86-64-sse-check.d: Likewise.
* gas/i386/ilp32/x86-64-sse-check-none.d: Likewise.
* gas/i386/ilp32/x86-64-sse-check-warn.d: Likewise.
* gas/i386/ilp32/x86-64-sse-noavx.d: Likewise.
* gas/i386/ilp32/x86-64-ssse3.d: Likewise.
* gas/i386/ilp32/x86-64-stack.d: Likewise.
* gas/i386/ilp32/x86-64-stack-intel.d: Likewise.
* gas/i386/ilp32/x86-64-stack-suffix.d: Likewise.
* gas/i386/ilp32/x86-64-unwind.d: Likewise.
* gas/i386/ilp32/x86-64-vmx.d: Likewise.
* gas/i386/ilp32/x86-64-xsave.d: Likewise.
* gas/i386/ilp32/x86-64-xsave-intel.d: Likewise.
ld/
2010-12-30 H.J. Lu <hongjiu.lu@intel.com>
* emulparams/elf32_x86_64.sh: New.
* configure.tgt (targ64_extra_emuls): Add elf32_x86_64 for
i[3-7]86-*-linux-*.
(targ_extra_libpath): Likewise.
(targ_extra_emuls): Add elf32_x86_64 for x86_64-*-linux-*.
(targ_extra_libpath): Likewise.
* Makefile.am (ALL_64_EMULATION_SOURCES): Add eelf32_x86_64.c.
(eelf32_x86_64.c): New.
* Makefile.in: Regenerated.
opcodes/
2010-12-30 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (print_insn): Support bfd_mach_x64_32 and
bfd_mach_x64_32_intel_syntax.
2010-12-31 00:33:36 +00:00
Richard Sandiford
9867540240
include/opcode/
...
2010-12-14 Mingjie Xing <mingjie.xing@gmail.com>
* mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
(OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
(INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
opcodes/
2010-12-14 Mingjie Xing <mingjie.xing@gmail.com>
* mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define.
(mips_builtin_opcodes): Add loongson3a specific instructions.
* mips-dis.c (print_insn_args): Handle the new arguments +a|b|c|z|Z.
gas/
2010-12-14 Mingjie Xing <mingjie.xing@gmail.com>
* config/tc-mips.c (insn_uses_reg): Handle the new flags
INSN2_READ_FPR_Z, INSN2_READ_GPR_D and INSN2_READ_GPR_Z.
(append_insn): Handle delay-slot filling for the new flags.
(validate_mips_insn): Handle the new arguments +a|b|c|z|Z.
(mips_ip): Handle the new arguments +a|b|c|z|Z.
gas/testsuite/
2010-12-14 Mingjie Xing <mingjie.xing@gmail.com>
* gas/mips/loongson-3a-2.s, gas/mips/loongson-3a-2.d,
gas/mips/loongson-3a-3.s, gas/mips/loongson-3a-3.d: New tests.
* gas/mips/mips.exp: Run them.
2010-12-18 11:14:14 +00:00
Richard Sandiford
a471ec3a5c
opcodes/
...
2010-12-03 Mingming Sun <mingm.sun@gmail.com>
* mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
fixed point instructions.
gas/testsuite/
2010-12-03 Mingming Sun <mingm.sun@gmail.com>
* gas/mips/loongson-3a.s, gas/mips/loongson-3a.d: New test.
* gas/mips/mips.exp: Run it.
2010-12-11 10:48:55 +00:00
Mike Frysinger
8b9a522f57
bfd/binutils/gas/gprof/ld/libiberty/opcodes: add .gitignore
...
This seems to cover a few random targets as well as --enable-targets=all.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-12-09 09:03:18 +00:00
Alan Modra
1de34e0afe
Update translations
2010-11-25 06:08:52 +00:00
Nick Clifton
fd50354116
bfd/
...
* archures.c (bfd_mach_mips_loongson_3a): Defined.
* bfd-in2.h (bfd_mach_mips_loongson_3a): Defined.
* cpu-mips.c (I_loongson_3a): New add.
(arch_info_struct): Add loongson_3a.
* elfxx-mips.c (_bfd_elf_mips_mach): Add loongson_3a.
(mips_set_isa_flags): Add loongson_3a.
(mips_mach_extensions): Add loongson_3a in MIPS64 extensions.
binutils/
* readelf.c (get_machine_flags): Add loongson-3a.
gas/
* config/tc-mips.c (mips_cpu_info_table): Add loongson3a in MIPS 64.
* doc/c-mips.texi (MIPS cpu): Add loongson3a.
include/
* elf/mips.h (E_MIPS_MACH_LS3A): Defined.
* opcode/mips.h (INSN_LOONGSON_3A): Defined.
(CPU_LOONGSON_3A): Defined.
(OPCODE_IS_MEMBER): Add LOONGSON_3A.
opcodes/
* mips-dis.c (mips_arch_choices): Add loongson3a.
* mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
(mips_builtin_opcodes): Modify some instructions' membership from
IL2F to IL2F|IL3A, since these instructions are supported by Loongson_3A.
2010-11-11 10:23:39 +00:00
Nick Clifton
8e295ce05a
Updated translations.
2010-11-10 14:39:10 +00:00
Tristan Gingold
2ee0aedfb8
bfd/
...
2010-11-05 Tristan Gingold <gingold@adacore.com>
* po/bfd.pot: Regenerate
binutils/
2010-11-05 Tristan Gingold <gingold@adacore.com>
* po/binutils.pot: Regenerate
gas/
2010-11-05 Tristan Gingold <gingold@adacore.com>
* po/gas.pot: Regenerate
* po/POTFILES.in: Regenerate
gprof/
2010-11-05 Tristan Gingold <gingold@adacore.com>
* po/gprof.pot: Regenerate
ld/
2010-11-05 Tristan Gingold <gingold@adacore.com>
* po/ld.pot: Regenerate
* po/POTFILES.in: Regenerate
opcodes/
2010-11-05 Tristan Gingold <gingold@adacore.com>
* po/opcodes.pot: Regenerate
2010-11-05 10:25:11 +00:00
Maciej W. Rozycki
af47889861
* mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".
2010-10-28 13:49:51 +00:00
Andreas Krebbel
be7a250d1a
2010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
...
* config/tc-s390.c (md_begin): Only add to hash table if cpu and
mode mask fit.
2010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
2010-10-28 07:37:45 +00:00
Chao-ying Fu
d958d1a369
2010-10-25 Chao-ying Fu <fu@mips.com>
...
* mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
2010-10-25 18:09:10 +00:00
Nathan Sidwell
c0621d88b0
bfd/
...
* elf32-tic6x.c: Add attribution.
gas/
* config/tc-tic6x.c: Add attribution.
opcodes/
* tic6x-dis.c: Add attribution.
2010-10-25 15:33:54 +00:00
Alan Modra
a43817dfc9
* Makefile.am (CLEANFILES): Add stamp-lm32. Sort.
...
* Makefile.in: Regenerate.
2010-10-21 23:50:57 +00:00
Maciej W. Rozycki
704897fbef
opcodes/
...
* mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
macros before their corresponding MIPS III hardware instructions.
gas/
* config/tc-mips.c (macro)[M_LD_OB, M_SD_OB]: Handle 64-bit ABIs.
gas/testsuite/
* gas/mips/lineno.s: Convert to o32.
* gas/mips/lineno.d: Adjust patterns accordingly. Force the o32
ABI.
2010-10-18 00:15:35 +00:00
H.J. Lu
da98bb4c74
Add CpuNop to CPU_GENERIC64_FLAGS.
...
gas/testsuite/
2010-10-16 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run x86-64-nops-1-g64.
* gas/i386/x86-64-nops-1.d: Remove -mtune=generic64.
* gas/i386/x86-64-nops-1-g64.d: New.
opcodes/
2010-10-16 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
* i386-init.h: Regenerated.
2010-10-16 21:53:16 +00:00
Mike Frysinger
e1791cb8b5
gas: blackfin: fix encoding of BYTEOP2M insn
...
The BYTEOP2M parser incorrectly calls BYTEOP2P to generate the opcode.
Once we've fixed that, it's easy to see that the disassembler also likes
to decode this insn incorrectly. So fix that and then add some tests.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-10-15 20:44:46 +00:00
H.J. Lu
553d0a7447
Remove CheckRegSize from movq.
...
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Remove CheckRegSize from movq.
* i386-tbl.h: Regenerated.
2010-10-14 23:16:19 +00:00
H.J. Lu
cfc08d490e
Remove CheckRegSize from instructions with 0, 1 or fixed operands.
...
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Remove CheckRegSize from instructions with
0, 1 or fixed operands.
* i386-tbl.h: Regenerated.
2010-10-14 21:37:30 +00:00
H.J. Lu
56ffb74112
Add CheckRegSize to instructions which require register size check.
...
gas/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_template): Check checkregsize
instead of w for register size check.
gas/testsuite/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run inval-reg.
* gas/i386/inval-reg.l: New.
* gas/i386/inval-reg.s: Likewise.
opcodes/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add CheckRegSize.
* i386-opc.h (CheckRegSize): New.
(i386_opcode_modifier): Add checkregsize.
* i386-opc.tbl: Add CheckRegSize to instructions which
require register size check.
* i386-tbl.h: Regenerated.
2010-10-14 18:45:10 +00:00
Andreas Schwab
1a2dab1fbb
binutils/:
...
* binutils-all/m68k/objdump.exp: Add fnop test.
* binutils-all/m68k/fnop.s: New file.
opcodes/:
* m68k-opc.c (m68k_opcodes): Move fnop before fbf.
2010-10-11 22:18:42 +00:00
Andreas Krebbel
a3ec2691d0
2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
...
* s390-opc.c: Make the instruction masks for the load/store on
condition instructions to cover the condition code mask as well.
* s390-opc.txt: lgoc -> locg and stgoc -> stocg.
2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/zarch-z196.d: Adjust the load/store on condition
instructions.
* gas/s390/zarch-z196.s: Likewise.
2010-10-11 11:56:53 +00:00
Jan Kratochvil
d92fa646e7
opcodes/
...
* Makefile.am (libopcodes_a_SOURCES): New as empty.
* Makefile.in: Regenerate.
2010-10-11 06:10:35 +00:00
Alan Modra
4469d2be4b
cgen/
...
* utils-cgen.scm (gen-attr-accessors): Rename bool attribute to bool_.
* cpu/mep.opc (mep_cgen_insn_supported): Ditto.
include/opcode/
* cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
(CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
opcodes/
* fr30-desc.h: Regenerate.
* frv-desc.h: Regenerate.
* ip2k-desc.h: Regenerate.
* iq2000-desc.h: Regenerate.
* lm32-desc.h: Regenerate.
* m32c-desc.h: Regenerate.
* m32r-desc.h: Regenerate.
* mep-desc.h: Regenerate.
* mep-opc.c: Regenerate.
* mt-desc.h: Regenerate.
* openrisc-desc.h: Regenerate.
* xc16x-desc.h: Regenerate.
* xstormy16-desc.h: Regenerate.
2010-10-09 06:50:23 +00:00
Alan Modra
9ccb8af972
Fix build with -DDEBUG=7
2010-10-08 14:00:50 +00:00
Bernd Schmidt
5d4c71e127
gas/
...
* config/tc-tic6x.c (tic6x_try_encode): Correct encoding of fstg field
in SPKERNEL instructions.
opcodes/
* tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
in SPKERNEL instructions.
gas/testsuite/
* gas/tic6x/insns-c674x-sploop.d: Add two more sploop/spkernel tests.
* gas/tic6x/insns-c674x-sploop.s: Likewise.
2010-10-07 11:28:49 +00:00
