* arch-defs.h: Deleted.
* mloop.in: Renamed from mainloop.in.
* sem.c: Renamed from semantics.c.
* Makefile.in: Update.
* sem-ops.h: Deleted.
* mem-ops.h: Deleted.
start-sanitize-cygnus
Add cgen support for generating files.
end-sanitize-cygnus
(arch): Renamed from CPU.
* decode.c: Redone.
* decode.h: Redone.
* extract.c: Redone.
* model.c: Redone.
* sem-switch.c: Redone.
* sem.c: Renamed from semantics.c, and redone.
* m32r-sim.h (PROFILE_COUNT_FILLNOPS): Update.
(GETTWI,SETTWI,BRANCH_NEW_PC): Define.
* m32r.c (WANT_CPU,WANT_CPU_M32R): Define.
(m32r_{fetch,store}_register): New functions.
(model_mark_{get,set}_h_gr): Prefix with m32r_.
(m32r_model_mark_{busy,unbusy}_reg): Prefix with m32r_.
(h_cr_{get,set}): Prefix with m32r_.
(do_trap): Fetch state from current_cpu, not current_state.
Call sim_engine_halt instead of engine_halt.
* sim-if.c (alloc_cpu): New function.
(free_state): New function.
(sim_open): Call sim_state_alloc, and malloc space for selected cpu
type. Call sim_analyze_program.
(sim_create_inferior): Handle selected cpu type when setting PC.
start-sanitize-m32rx
(sim_resume): Handle m32rx.
end-sanitize-m32rx
(sim_stop_reason): Deleted.
(print_m32r_misc_cpu): Update.
start-sanitize-m32rx
(sim_{fetch,store}_register): Handle m32rx.
end-sanitize-m32rx
(sim_{read,write}): Deleted.
(sim_engine_illegal_insn): New function.
* sim-main.h: Don't include arch-defs.h,sim-core.h,sim-events.h.
Include arch.h,cpuall.h. Include cpu.h,decode.h if m32r.
start-sanitize-m32rx
Include cpux.h,decodex.h if m32rx.
end-sanitize-m32rx
(_sim_cpu): Include member appropriate cpu_data member for the cpu.
(M32R_MISC_PROFILE): Renamed from M32R_PROFILE.
(sim_state): Delete members core,events,halt_jmp_buf.
Change `cpu' member to be a pointer to the cpu's struct, rather than
record inside the state struct.
* tconfig.in (WITH_DEVICES): Define here.
(WITH_FAST,WITH_SEM_SWITCH_{FULL,FAST}): Define for the cpu.
* cgen.sh: New file.
* cgen-scache.h: Deleted.
* cgen-scache.c: Only compile contents if WITH_SCACHE.
(scache_init): Use runtime computed size of SCACHE.
(scache_flush): Likewise.
* cgen-mem.h (GETIMEMU[QHSD]I): Declare.
([GS]ETT{QI,UQI,HI,UHI,SI,USI,DI,UDI}): Declare.
* cgen-sim.h: Scache support moved here.
(PC): Redo definition.
(ARGBUF,SCACHE,PARALLEL_EXEC): Provide forward decls.
(DECODE): Add parallel execution support.
Only include semantic label members if using switch.
(SWITCH,CASE,BREAK,DEFAULT,ENDSWITCH): Portable computed goto support.
(CGEN_CPU): Delete members exec_state, halt_sigrc, halt_jmp_buf.
(IADDR,CIA,SEM_ARG,EX_FN_NAME,SEM_FN_NAME,RECORD_IADDR,SEM_ARGBUF,
SEM_NEXT_PC,SEM_BRANCH_VIA_{CACHE,ADDR},SEM_NEW_PC_ADDR): Moved here
from cgen-types.h.
(engine_{stop,run,resume,halt,signal}): Delete decls.
* cgen-types.h (CGEN_{XCAT3,CAT3}): Delete.
(argbuf,scache): Delete forward decls.
(STATE): Delete decl.
* cgen-utils.c: Don't include decode.h, mem-ops.h, sem-ops.h.
Include cgen-mem.h, cgen-ops.h.
(engine_halt,engine_signal): Delete.
({ex,exc,sem,semc}_illegal): Delete.
(sim_disassemble_insn): Result of extract fn is in bits.
* genmloop.sh: Rewrite.
For sim/mips, enable multi-sim support when mips64vr5400-elf is target.
For sim/igen, allow specification of a default machine (will need
more work later).
* simops.c (OP_4201): For "rac", sign extend 56 bit value before
it is shifted.
* d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using
SIGNED64 macro.
