* d10v_sim.h (SEXT56): Define.
* simops.c (OP_4201): For "rac", sign extend 56 bit value before it is shifted. * d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using SIGNED64 macro.
This commit is contained in:
Andrew Cagney
parent
d4b2cc56c0
commit
aa49c64f3e
9 changed files with 230 additions and 55 deletions
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@ -1,3 +1,13 @@
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Wed Dec 3 17:27:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* d10v_sim.h (SEXT56): Define.
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* simops.c (OP_4201): For "rac", sign extend 56 bit value before
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it is shifted.
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* d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using
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SIGNED64 macro.
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Tue Dec 2 15:38:34 1997 Fred Fish <fnf@cygnus.com>
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* interp.c (sim_resume): Call do_2_short with LEFT_FIRST or
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@ -1,3 +1,4 @@
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#include "config.h"
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#include <stdio.h>
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#include <ctype.h>
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#include <limits.h>
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@ -18,43 +19,14 @@
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extern int d10v_debug;
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#if UCHAR_MAX == 255
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typedef unsigned char uint8;
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typedef signed char int8;
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#else
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#error "Char is not an 8-bit type"
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#endif
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#if SHRT_MAX == 32767
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typedef unsigned short uint16;
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typedef signed short int16;
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#else
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#error "Short is not a 16-bit type"
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#endif
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#if INT_MAX == 2147483647
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typedef unsigned int uint32;
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typedef signed int int32;
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#elif LONG_MAX == 2147483647
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typedef unsigned long uint32;
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typedef signed long int32;
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#else
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#error "Neither int nor long is a 32-bit type"
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#endif
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#if LONG_MAX > 2147483647
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typedef unsigned long uint64;
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typedef signed long int64;
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#elif __GNUC__
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typedef unsigned long long uint64;
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typedef signed long long int64;
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#else
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#error "Can't find an appropriate 64-bit type"
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#endif
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#include "sim-types.h"
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typedef unsigned8 uint8;
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typedef unsigned16 uint16;
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typedef signed16 int16;
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typedef unsigned32 uint32;
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typedef signed32 int32;
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typedef unsigned64 uint64;
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typedef signed64 int64;
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/* FIXME: D10V defines */
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typedef uint16 reg_t;
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@ -62,6 +34,7 @@ typedef uint16 reg_t;
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struct simops
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{
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long opcode;
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int is_long;
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long mask;
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int format;
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int cycles;
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@ -118,7 +91,8 @@ struct _state
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uint8 F1;
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uint8 C;
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uint8 exe;
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int exception;
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int exception;
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int pc_changed;
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/* everything below this line is not reset by sim_create_inferior() */
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uint8 *imem;
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uint8 *dmem;
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@ -132,7 +106,7 @@ extern struct simops Simops[];
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extern asection *text;
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extern bfd_vma text_start;
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extern bfd_vma text_end;
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extern bfd *exec_bfd;
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extern bfd *prog_bfd;
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#define PC (State.cregs[2])
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#define PSW (State.cregs[0])
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@ -160,23 +134,27 @@ extern bfd *exec_bfd;
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#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
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/* sign-extend a 32-bit number */
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#define SEXT32(x) ((((x)&0xffffffffLL)^(~0x7fffffffLL))+0x80000000LL)
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#define SEXT32(x) ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000))
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/* sign extend a 40 bit number */
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#define SEXT40(x) ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL)
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#define SEXT40(x) ((((x)&SIGNED64(0xffffffffff))^(~SIGNED64(0x7fffffffff)))+SIGNED64(0x8000000000))
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/* sign extend a 44 bit number */
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#define SEXT44(x) ((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL)
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#define SEXT44(x) ((((x)&SIGNED64(0xfffffffffff))^(~SIGNED64(0x7ffffffffff)))+SIGNED64(0x80000000000))
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/* sign extend a 56 bit number */
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#define SEXT56(x) ((((x)&SIGNED64(0xffffffffffffff))^(~SIGNED64(0x7fffffffffffff)))+SIGNED64(0x80000000000000))
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/* sign extend a 60 bit number */
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#define SEXT60(x) ((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL)
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#define SEXT60(x) ((((x)&SIGNED64(0xfffffffffffffff))^(~SIGNED64(0x7ffffffffffffff)))+SIGNED64(0x800000000000000))
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#define MAX32 0x7fffffffLL
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#define MIN32 0xff80000000LL
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#define MASK32 0xffffffffLL
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#define MASK40 0xffffffffffLL
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#define MAX32 SIGNED64(0x7fffffff)
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#define MIN32 SIGNED64(0xff80000000)
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#define MASK32 SIGNED64(0xffffffff)
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#define MASK40 SIGNED64(0xffffffffff)
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#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
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/* The alignment of MOD_E in the following macro depends upon "i" always being a power of 2. */
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#define INC_ADDR(x,i) x = ((State.MD && x == (MOD_E & ~((i)-1))) ? MOD_S : (x)+(i))
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extern uint8 *dmem_addr PARAMS ((uint32));
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extern bfd_vma decode_pc PARAMS ((void));
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@ -213,3 +191,5 @@ extern void write_longlong PARAMS ((uint8 *addr, int64 data));
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#define SET_IMAP0(x) SW(0xff00,x)
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#define SET_IMAP1(x) SW(0xff02,x)
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#define SET_DMAP(x) SW(0xff04,x)
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#define JMP(x) { PC = (x); State.pc_changed = 1; }
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@ -1912,18 +1912,20 @@ OP_5201 ()
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}
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State.F1 = State.F0;
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tmp = SEXT56 ((State.a[0] << 16) | (State.a[1] & 0xffff));
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if (shift >=0)
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tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
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tmp <<= shift;
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else
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tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
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tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
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if (tmp > MAX32)
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tmp >>= -shift;
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tmp += 0x8000;
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tmp >>= 16; /* look at bits 0:43 */
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if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
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{
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State.regs[OP[0]] = 0x7fff;
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State.regs[OP[0]+1] = 0xffff;
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State.F0 = 1;
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}
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else if (tmp < MIN32)
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else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
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{
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State.regs[OP[0]] = 0x8000;
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State.regs[OP[0]+1] = 0;
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@ -2429,8 +2431,10 @@ OP_0 ()
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uint16 tmp;
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trace_input ("sub", OP_REG, OP_REG, OP_VOID);
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/* see ../common/sim-alu.h for a more extensive discussion on how to
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compute the carry/overflow bits. */
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tmp = State.regs[OP[0]] - State.regs[OP[1]];
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State.C = (tmp > State.regs[OP[0]]);
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State.C = ((uint16) State.regs[OP[0]] >= (uint16) State.regs[OP[1]]);
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State.regs[OP[0]] = tmp;
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trace_output (OP_REG);
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}
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@ -12,6 +12,7 @@ loop.s
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t-macros.i
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t-mac.s
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t-msbu.s
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t-rac.s
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t-rachi.s
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t-rep.s
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t-mulxu.s
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@ -1,6 +1,15 @@
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Wed Dec 3 16:35:24 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* t-rac.s: New files.
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* t-macros.i: Add macros for checking psw and 2w quantities.
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* Makefile.in (TESTS): Update.
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Tue Dec 2 11:01:36 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s: New files.
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* t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s, t-sub.s: New
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files.
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* Makefile.in: Update.
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@ -44,9 +44,11 @@ TESTS = \
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t-mvtac.ok \
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t-msbu.ok \
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t-mulxu.ok \
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t-rac.ok \
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t-rachi.ok \
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t-rep.ok \
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t-sub2w.ok \
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t-sub.ok \
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t-subi.ok \
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#
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127
sim/testsuite/d10v-elf/t-macros.i
Normal file
127
sim/testsuite/d10v-elf/t-macros.i
Normal file
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@ -0,0 +1,127 @@
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.macro start
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.text
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.align 2
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.globl _start
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_start:
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.endm
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.macro exit47
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ldi r6, 1
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ldi r2, 47
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trap 15
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.endm
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.macro exit0
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ldi r6, 1
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ldi r2, 0
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trap 15
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.endm
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.macro load reg val
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ldi \reg, #\val
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.endm
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.macro load2w reg hi lo
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ld2w \reg, @(1f,r0)
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.data
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.align 2
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1: .short \hi
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.short \lo
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.text
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.endm
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.macro check exit reg val
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cmpeqi \reg, #\val
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brf0t 1f
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0: ldi r6, 1
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ldi r2, \exit
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trap 15
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1:
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.endm
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.macro check2w2 exit reg hi lo
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st2w \reg, @(1f,r0)
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ld r2, @(1f, r0)
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cmpeqi r2, #\hi
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brf0f 0f
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ld r2, @(1f + 2, r0)
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cmpeqi r2, #\lo
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brf0f 0f
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bra 2f
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0: ldi r6, 1
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ldi r2, \exit
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trap 15
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.data
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.align 2
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1: .long 0
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.text
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2:
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.endm
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.macro loadacc2 acc guard hi lo
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ldi r2, #\lo
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mvtaclo r2, \acc
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ldi r2, #\hi
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mvtachi r2, \acc
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ldi r2, #\guard
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mvtacg r2, \acc
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.endm
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.macro checkacc2 exit acc guard hi lo
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ldi r2, #\guard
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mvfacg r3, \acc
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cmpeq r2, r3
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brf0f 0f
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ldi r2, #\hi
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mvfachi r3, \acc
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cmpeq r2, r3
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brf0f 0f
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ldi r2, #\lo
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mvfaclo r3, \acc
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cmpeq r2, r3
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brf0f 0f
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bra 4f
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0: ldi r6, 1
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ldi r2, \exit
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trap 15
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4:
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.endm
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.macro loadpsw2 val
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ldi r2, #\val
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mvtc r2, cr0
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.endm
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.macro checkpsw2 exit val
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mvfc r2, cr0
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cmpeqi r2, #\val
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brf0t 1f
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ldi r6, 1
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ldi r2, \exit
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trap 15
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1:
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.endm
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.macro hello
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;; 4:write (1, string, strlen (string))
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ldi r6, 4
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ldi r2, 1
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ldi r3, 1f
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ldi r4, 2f-1f-1
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trap 15
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.section .rodata
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1: .string "Hello World!\n"
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2: .align 2
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.text
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.endm
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16
sim/testsuite/d10v-elf/t-rac.s
Normal file
16
sim/testsuite/d10v-elf/t-rac.s
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.include "t-macros.i"
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start
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;; clear FX
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loadpsw2 0x8004
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loadacc2 a0 0x80 0x0000 0x0000
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loadacc2 a1 0x00 0x0000 0x5000
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load r10 0x0123
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load r11 0x4567
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test_rac1:
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RAC r10, a0, #-2
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checkpsw2 1 0x8008
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check2w2 2 r10 0x8000 0x0000
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exit0
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26
sim/testsuite/d10v-elf/t-rep.s
Normal file
26
sim/testsuite/d10v-elf/t-rep.s
Normal file
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.include "t-macros.i"
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start
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# Check that the instruction @REP_E is executed when it
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# is reached using a branch instruction
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ldi r2, 1
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test_rep_1:
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rep r2, end_rep_1
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nop || nop
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nop || nop
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nop || nop
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nop || nop
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ldi r3, 46
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bra end_rep_1
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ldi r3, 42
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end_rep_1:
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addi r3, 1
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check 1 r3 47
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exit0
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