Commit graph

514 commits

Author SHA1 Message Date
Ian Lance Taylor
03514bc871 Thu Feb 13 20:41:22 1997 Philippe De Muyter <phdm@info.ucl.ac.be>
* m68k-opc.c (m68k_opcodes): Add swbeg pseudo-instruction.
1997-02-14 01:43:14 +00:00
Jeff Law
9bd0068fc8 * mn10200-opc.c (IMM16_PCREL): This is a signed operand.
(IMM24_PCREL): Likewise.
Fixes bugs exposed by disassembler testsuite.
1997-02-13 23:31:53 +00:00
Ian Lance Taylor
6617b927da * mips-dis.c (print_mips16_insn_arg): Use memaddr - 2 as the base
address for an extended PC relative instruction that is not a
	branch.
1997-02-13 18:29:25 +00:00
Ian Lance Taylor
d1c52e5b5c Wed Feb 12 12:27:40 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* m68k-dis.c (print_insn_m68k): Set bytes_per_chunk and
	bytes_per_line.
1997-02-12 17:28:14 +00:00
Fred Fish
e2773136e0 * tic80-opc.c (tic80_operands): Fix typo '+' -> '|'.
(tic80_opcodes): Sort entries so that long immediate forms
	come after short immediate forms, making it easier for
	assembler to select the right one for a given operand.
1997-02-11 23:48:15 +00:00
Ian Lance Taylor
2ea116f49b * mips-dis.c (_print_insn_mips): Set bytes_per_chunk and
display_endian.
	(print_insn_mips16): Likewise.
1997-02-11 20:46:14 +00:00
Gavin Romig-Koch
276c2d7dc8 Add r5900 1997-02-11 13:26:34 +00:00
Fred Fish
c37555c141 * tic80-opc.c (tic80_symbol_to_value): Changed to accept
a symbol class that restricts translation to just that
	class (general register, condition code, etc).
1997-02-10 17:16:28 +00:00
Fred Fish
cceb79baa8 * tic80-opc.c (tic80_operands): Add REG_0_E, REG_22_E,
and REG_DEST_E for register operands that have to be
	an even numbered register.  Add REG_FPA for operands that
	are one of the floating point accumulator registers.
	Add TIC80_OPERAND_MASK to flags for ENDMASK operand.
	(tic80_opcodes): Change entries that need even numbered
	register operands to use the new operand table entries.
	Add "or" entries that are identical to "or.tt" entries.
1997-02-07 00:38:44 +00:00
Ian Lance Taylor
0d52464ce4 * mips16-opc.c: Add new cases of exit instruction for
disassembler.
	* mips-dis.c (print_mips16_insn_arg): Display floating point
	registers in operands of exit instruction.  Print `$' before
	register names in operands of entry and exit instructions.
1997-02-05 16:14:26 +00:00
Fred Fish
6cb5b585c5 * tic80-opc.c (tic80_predefined_symbols): Table of name/value
pairs for all predefined symbols recognized by the assembler.
	Also used by the disassembling routines.
	(tic80_symbol_to_value): New function.
	(tic80_value_to_symbol): New function.
	* tic80-dis.c (print_operand_control_register,
 	print_operand_condition_code, print_operand_bitnum):
	Remove private tables and use tic80_value_to_symbol function.
1997-01-30 21:16:46 +00:00
Martin Hunt
f28d34be74 Thu Jan 30 11:30:45 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-dis.c (print_operand): Change address printing
	to correctly handle PC wrapping.  Fixes PR11490.
1997-01-30 19:33:11 +00:00
Jeff Law
c9f649022e * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative
branchs relaxable.
1997-01-29 16:40:15 +00:00
Ian Lance Taylor
20d4301801 * mips-dis.c (print_insn_mips16): Set insn_info information.
(print_mips16_insn_arg): Likewise.
1997-01-28 21:49:18 +00:00
Ian Lance Taylor
c4f19df2ef * mips-dis.c (print_insn_mips16): Better handling of an extend
opcode followed by an instruction which can not be extended.
1997-01-28 20:58:28 +00:00
J.T. Conklin
071ad7f0e0 * m68k-opc.c (m68k_opcodes): Changed operand specifier for the
coldfire moveb instruction to not allow an address register as
destination.  Although the documentation does not indicate that
this is invalid, experiments uncovered unexpected behavior.
Added a comment explaining the situation.  Thanks to Andreas
Schwab for pointing this out to me.
1997-01-24 20:14:26 +00:00
Fred Fish
1eb54bb463 * tic80-opc.c (tic80_opcodes): Expand comment to note that the
entries are presorted so that entries with the same mnemonic are
	adjacent to each other in the table.  Sort the entries for each
	instruction so that this is true.
1997-01-23 03:17:45 +00:00
Ian Lance Taylor
84be8dcf9e Mon Jan 20 12:48:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* m68k-dis.c: Include <libiberty.h>.
	(print_insn_m68k): Sort the opcode table on the most significant
	nibble of the opcode.
1997-01-20 17:50:34 +00:00
Fred Fish
68c7761c42 * tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd",
"vsub", "vst", "xnor", and "xor" instructions.
      (V_a1): Renamed from V_a, msb of accumulator reg number.
      (V_a0): Add macro, lsb of accumulator reg number.
1997-01-19 22:24:21 +00:00
Fred Fish
8fdffbc4b3 * tic80-dis.c (print_insn_tic80): Broke excessively long
function up into several smaller ones and arranged for
        the instruction printing function to be callable recursively
        to print vector instructions that have both a load and a
        math instruction packed into a single opcode.
        * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode
        to explain why it comes after the other vector opcodes.
1997-01-19 18:33:10 +00:00
J.T. Conklin
c49bbc27db fix operand mask in the "moveml" entries for the coldfire. 1997-01-18 00:37:30 +00:00
J.T. Conklin
a3d4e445d2 From the coldfire branch:
* m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
	move insns to handle immediate operands.

From Andreas Schwab:

        * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil".
1997-01-18 00:27:23 +00:00
Fred Fish
c977d8fb7b * tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V):
New macros for building vector instruction opcodes.
	(tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and
	FMT_LI, which were unused.  The field is now a flags field.
	Remove some opcodes that are possible, but illegal, such
	as long immediate instructions with doubles for immediate
	values.  Add "vadd" and "vld" instructions.
1997-01-17 04:00:56 +00:00
Fred Fish
5fdeceb477 * tic80-opc.c (tic80_operands): Reorder some table entries to make
the order more logical.  Move the shift alias instructions ("rotl",
	"shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be
 	interspersed with the regular sr.x and sl.x instructions.  Add
	and test new instruction opcodes for "sl", "sli", "sr", "sri", "st",
 	"sub", "subu", "swcr", and "trap".
1997-01-16 02:10:17 +00:00
Fred Fish
003df61759 * tic80-dis.c (print_insn_tic80): Print floating point operands
as floats.
      * tic80-opc.c (SPFI): Add single precision floating point
      immediate operand type.
      (ROTATE): Add rotate operand type for shifts.
      (ENDMASK): Add for shifts.
      (n): Macro for the 'n' bit.
      (i): Macro for the 'i' bit.
      (PD): Macro for the 'PD' field.
      (P2): Macro for the 'P2' field.
      (P1): Macro for the 'P1' field.
      (tic80_operands): Add entries for "exts", "extu", "fadd",
      "fcmp", and "fdiv".
1997-01-13 23:05:49 +00:00
Jeff Law
1b8a127fe7 Fix copyright. 1997-01-06 22:14:13 +00:00
Jeff Law
09171e3fe6 * mn10200-dis.c (disassemble): Mask off unwanted bits after
adding in current address for pc-relative operands.
Fixes disassembly of backwards 24bit pc-relative addressese.
1997-01-06 22:13:39 +00:00
Fred Fish
50965d0ec2 * tic80-dis.c (R_SCALED): Add macro to test for ":s" modifier bit.
(print_insn_tic80): If R_SCALED then print ":s" modifier for operand.
	* tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names
	changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
	(SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI,
	REG_BASE_M_SI, REG_BASE_M_LI respectively.
	(REG_SCALED, LSI_SCALED): New operand types.
	(E): New macro for 'E' bit at bit 27.
	(tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap
	opcodes, including the various size flavors (b,h,w,d) for
	the direct load and store instructions.
1997-01-06 18:04:38 +00:00
Fred Fish
937fe72232 * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit
in an instruction.
	* tic80-dis.c (print_insn_tic80): Change comma and paren handling.
  	Use M_SI and M_LI macros to check for ":m" modifier for GPR operands.
	* tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands.
	(F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New	bit-twiddlers.
	(MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode
	masks with "MASK_* & ~M_*" to get the M bit reset.
	(tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef.
1997-01-05 19:29:42 +00:00
Fred Fish
1f8c8c60a1 * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE
correctly.  Add support for printing TIC80_OPERAND_BITNUM and
	TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic
	form.
	* tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM,
	CC, SICR, and LICR table entries.
	(tic80_opcodes): Add and test "nop", "br", "bbo", "bbz",
	"bcnd", and "brcr" opcodes.
1997-01-05 02:10:14 +00:00
Fred Fish
872dc6f0bc * ppc-opc.c (powerpc_operands): Make comment match the
actual fields (no shift field).
	* sparc-opc.c (sparc_opcodes): Document why this cannot be "const".

	* tic80-dis.c (print_insn_tic80): Replace abort stub with a
	partial implementation, work in progress.
	* tic80-opc.c (tic80_operands): Begin construction operands table.
	(tic80_opcodes): Continue populating opcodes table and start
	filling in the operand indices.
	(tic80_num_opcodes): Add this.
1997-01-04 01:39:30 +00:00
Ian Lance Taylor
a3ecb49f4b * m68k-opc.c: Add #B case for moveq. 1997-01-03 17:14:30 +00:00
Jeff Law
bc83032148 * mn10300-dis.c (disassemble): Make sure all variables are initialized
before they are used.
Fixes various weird disassembly problems.
1997-01-02 19:21:36 +00:00
Jeff Law
160cca6457 * v850-opc.c (v850_opcodes): Put curly-braces around operands
for "breakpoint" instruction.
Fixes random assembler failures for hp-x-v850 toolchain.
1996-12-31 21:20:00 +00:00
Ian Lance Taylor
1a4752c664 * Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE.
(dep): Use ALL_CFLAGS rather than CFLAGS.
1996-12-31 20:38:45 +00:00
Michael Meissner
0068e79cc5 Set V850_OPERAND_ADJUST_SHORT_MEMORY flag on sst.{h,w}/sld.{h,w} instructions 1996-12-31 20:11:39 +00:00
Ken Raeburn
f204f75257 End tic80 sanitization regions with "end-sanitize-tic80", not
with "start-sanitize-tic80".
1996-12-31 17:51:22 +00:00
Fred Fish
39620b712c * Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency.
(tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in.
1996-12-31 00:09:59 +00:00
Ian Lance Taylor
ea6c562019 * mips16-opc.c: Add "abs". 1996-12-30 16:38:24 +00:00
Fred Fish
a79d0193ec * Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o.
* disassemble.c (ARCH_tic80): Define if ARCH_all is defined.
	(disassembler): Add bfd_arch_tic80 support to set disassemble
 	to print_insn_tic80.
	* tic80-dis.c (print_insn_tic80): Add stub.
1996-12-29 18:01:29 +00:00
Fred Fish
6357e7f68e (Laying groundwork (that will be incrementally fleshed out) for TIc80 support)
* configure.in (arch in $selarchs): Add bfd_tic80_arch entry.
	* configure: Regenerate with autoconf.
	* tic80-dis.c: Add file.
	* tic80-opc.c: Add file.
1996-12-28 05:36:52 +00:00
Martin Hunt
b5baebe405 Fri Dec 20 14:30:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (pre_defined_registers):  Add cr[0-15], dpc, dpsw, link.
1996-12-20 22:32:16 +00:00
Jeff Law
e098bae8e7 * mn10200-opc.c (mn10200_operands): Add SIMM16N.
(mn10200_opcodes): Use it for some logicals and btst insns.
        Add "break" and "trap" instructions.
1996-12-18 17:12:16 +00:00
Jeff Law
374cb3020b * mn10300-opc.c (mn10300_opcodes): Add "break" instruction.
For gdb.
1996-12-16 22:28:24 +00:00
Jeff Law
d21f1eae7d * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)". 1996-12-16 20:05:07 +00:00
Ian Lance Taylor
39e5bea281 * mips-dis.c (print_mips16_insn_arg): The base address of a PC
relative load or add now depends upon whether the instruction is
	in a delay slot.
1996-12-15 03:37:08 +00:00
Jeff Law
c6b62ad1d7 * mn10200-dis.c: Finish writing disassembler.
* mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn".
        Fix mask for "jmp (an)".
mn10200 disassembler works!
1996-12-12 08:09:27 +00:00
Jeff Law
77955104ba * mn10300-dis.c (disassemble, print_insn_mn10300): Corrently
handle endianness issues for mn10300.
1996-12-11 17:34:15 +00:00
Jeff Law
532700fc31 * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)".
Yoshihiro Adachi sez the manual was wrong for this insn.
1996-12-11 16:29:02 +00:00
Jeff Law
7bfc95d917 * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2
instruction.  Fix opcode field for "movb (imm24),dn".
Stuff found by the testsuite.
1996-12-10 20:34:14 +00:00