gas/
2015-03-10 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (mapping_state): Set minimum alignment for
code sections.
gas/testsuite
2015-03-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/codealign.d: Add test for code section alignment.
* gas/aarch64/codealign.s: New file.
bfd/
PR gas/17843
* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Expect
R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
to be used with MOVK rather than MOVZ.
gas/
PR gas/17843
* config/tc-aarch64.c (process_movw_reloc_info): Allow
R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
for MOVK.
gas/testsuite/
PR gas/17843
* gas/aarch64/tls.s, gas/aarch64/tls.d: Add test for
R_AARCH64_TLSLE_MOVW_TPREL_G0/R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
sequence.
ld/testsuite/
PR gas/17843
* ld-aarch64/tlsle.s, ld-aarch64/tlsle.d: New test.
* ld-aarch64/aarch64-elf.exp: Run it.
gas/
* write.c (SUB_SEGMENT_ALIGN): Don't pad non-code sections at
end to their alignment.
gas/testsuite/
* gas/sparc/pcrel.d: Update for changed padding in data sections.
* gas/sparc/pcrel64.d: Likewise.
ld/testsuite/
* ld-sparc/gotop32.rd: Update for changed padding in data sections.
* ld-sparc/gotop32.td: Likewise.
* ld-sparc/gotop64.rd: Likewise.
* ld-sparc/gotop64.td: Likewise.
* ld-tilegx/external.s: Align .data.
* ld-tilepro/external.s: Likewise.
Add support to objdump for dumping the .avr.prop section in a structured
way.
binutils/ChangeLog:
* od-elf32_avr.c: Add elf32-avr.h include.
(OPT_AVRPROP): Define.
(options[]): Add 'avr-prop' entry.
(elf32_avr_help): Add avr-prop help text.
(elf32_avr_dump_avr_prop): New function.
(elf32_avr_dump): Add check for avr-prop.
bfd/ChangeLog:
* elf32-avr.h (struct avr_property_header): New strucure.
(avr_elf32_load_property_records): Declare.
(avr_elf32_property_record_name): Declare.
* elf32-avr.c: Add bfd_stdint.h include.
(retrieve_local_syms): New function.
(get_elf_r_symndx_section): New function.
(get_elf_r_symndx_offset): New function.
(internal_reloc_compare): New function.
(struct avr_find_section_data): New structure.
(avr_is_section_for_address): New function.
(avr_find_section_for_address): New function.
(avr_elf32_load_records_from_section): New function.
(avr_elf32_load_property_records): New function.
(avr_elf32_property_record_name): New function.
gas/testsuite/ChangeLog:
* gas/avr/avr-prop-1.d: New file.
* gas/avr/avr-prop-1.s: New file.
bfd * elf32-v850.c (v850_set_note): New function. Creates a Renesas
style note entry.
(v850_elf_make_note_section): New function. Creates a note
section.
(v850_elf_create_sections): New function. Create a note section
if one is not already present.
(v850_elf_set_note): New function. Adds a note to a bfd.
(v850_elf_copy_private_bfd_data): New function. Copies V850
notes.
(v850_elf_merge_notes): New function. Merges V850 notes.
(print_v850_note): New function. Displays a V850 note.
(v850_elf_print_notes): New function. Displays all notes attached
to a bfd.
(v850_elf_merge_private_bfd_data): Call v850_elf_merge_notes.
(v850_elf_print_private_bfd_data): Call v850_elf_print_notes.
(v850_elf_fake_sections): Set the type of the V850 note section.
* bfd-in.h (v850_elf_create_sections): Add prototype.
(v850_elf_set_note): Add prototype.
* bfd-in2.h: Regenerate.
binutils* readelf.c (get_machine_flags): Remove deprecated V850 machine
flags.
(get_v850_section_type_name): New function. Handles V850 special
sections.
(get_section_type_name): Add support for V850.
(get_v850_elf_note_type): New function. Returns the name of a
V850 note.
(print_v850_note): New function. Prints a V850 note.
(process_v850_notes): New function. Prints V850 notes.
(process_note_sections): Add support for V850.
binutils/testsute
* binutils-all/objcopy.exp: Skip the strip-10 test for the V850.
gas * config/tc-v850.c (soft_float): New variable.
(v850_data_8): New variable.
(md_show_usage): Add -msoft-float/-mhard-float.
(md_parse_option): Likewise.
(md_begin): Set the default value of soft_float.
(v850_md_end): New function. Creates a note section.
* config/tc-v850.h (md_end): Define.
* doc/c-v850.texi: Document -msoft-float/-mhard-float.
gas/testsuite
* gas/elf/elf.exp: Add special version of the section2 test for
the V850.
* gas/elf/section2.e-v850: New file.
include/elf
* v850.h (EF_RH850_SIMD): Delete deprecated flag.
(EF_RH850_CACHE): Likewise.
(EF_RH850_MMU): Likewise.
(EF_RH850_DATA_ALIGN8): Likewise.
(SHT_RENESAS_IOP): Fix typo in name.
(SHT_RENESAS_INFO): Define.
(V850_NOTE_SECNAME): Define.
(SIZEOF_V850_NOTE): Define.
(V850_NOTE_NAME): Define.
(enum v850_notes): New enum.
(NUM_V850_NOTES): Define.
ld/ChangeLog
2015-02-24 Nick Clifton <nickc@redhat.com>
* Makefile.am (ev850.c): Add dependency upon
$(srcdir)/emultempl/v850elf.em.
(ev850_rh850.c): Likewise.
* Makefile.in: Regenerate.
* emultempl/v850elf.em: New file.
* emulparams/v850.sh (EXTRA_EM_FILE): Define.
* emulparams/v850_rh850.sh (EXTRA_EM_FILE): Define.
* scripttempl/v850.sc: Add .note.renesas section.
* scripttempl/v850_rh850.sc: Likewise.
ld/testsuite
* ld-elf/extract-symbol-1sec.d: Expect to fail on the V850.
Tests that bfd_perform_reloc doesn't freak over a NONE reloc at end
of section.
gas/
* read.c (s_reloc): Match BFD_RELOC_NONE, BFD_RELOC{8,16,32,64}.
* write.c (get_frag_for_reloc): Allow match just past end of frag.
gas/testsuite/
* gas/all/none.s,
* gas/all/none.d: New test.
* gas/all/gas.exp: Run it.
- 32 128 bit vector registers (overlapping with the existing 16 64 bit
floating point registers)
- vector double instructions
- vector integer instructions
- scalar vector instructions (allowing to have more floating point
registers for scalar operations)
- vector string instructions
gas/ChangeLog:
* config/tc-s390.c (struct pd_reg): Remove.
(pre_defined_registers): Remove.
(REG_NAME_CNT): Remove.
(reg_name_search): Calculate the register number instead of doing
a lookup.
(register_name, tc_s390_regname_to_dw2regnum): Adopt to the new
reg_name_search signature.
(s390_parse_cpu): Support the new arch string z13.
(s390_insert_operand): Support for vector registers with the extra
field for the fifth bit of each vector register operand.
(md_gather_operand): Adjust to the new handling of optional
parameters.
* doc/as.texinfo: Document the z13 cpu string.
gas/testsuite/ChangeLog:
* gas/s390/esa-g5.d: Add a variant without the optional operand.
* gas/s390/esa-g5.s: Likewise.
* gas/s390/esa-z9-109.d: Likewise.
* gas/s390/esa-z9-109.s: Likewise.
* gas/s390/zarch-z9-109.d: Likewise.
* gas/s390/zarch-z9-109.s: Likewise.
* gas/s390/zarch-z10.d: For variants with a zero optional argument
it is not dumped by objdump anymore.
* gas/s390/zarch-zEC12.d: Likewise.
* gas/s390/zarch-z13.d: New file.
* gas/s390/zarch-z13.s: New file.
* gas/s390/s390.exp: Run the test for the z13 files.
include/opcode/ChangeLog:
* s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
ld/testsuite/ChangeLog:
* ld-s390/tlsbin.dd: The nopr register operand is optional and not
printed if 0 anymore.
opcodes/ChangeLog:
* s390-dis.c (s390_extract_operand): Support vector register
operands.
(s390_print_insn_with_opcode): Support new operands types and add
new handling of optional operands.
* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
and include opcode/s390.h instead.
(struct op_struct): New field `flags'.
(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
(dumpTable): Dump flags.
(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
string.
* s390-opc.c: Add new operands types, instruction formats, and
instruction masks.
(s390_opformats): Add new formats for .insn.
* s390-opc.txt: Add new instructions.
When runtime patching code (like e.g. done by the Linux kernel) there
may be cases where the set of stack frame alterations differs between
unpatched and patched code. Consequently the corresponding unwind data
needs patching too. Locating the right places within an FDE, however,
is rather cumbersome without a way to insert labels in the resulting
section. Hence this patch introduces a new directive, .cfi_label. Note
that with the way CFI data gets emitted currently (at the end of the
assembly process) this can't support local FB- and dollar-labels.
gas/
2015-01-12 Jan Beulich <jbeulich@suse.com>
* gas/dw2gencfi.c (cfi_add_label, dot_cfi_label): New.
(cfi_pseudo_table): Add "cfi_label".
(output_cfi_insn): Handle CFI_label.
(select_cie_for_fde): Als terminate CIE when encountering
CFI_label.
* dw2gencfi.h (cfi_add_label): Declare.
(struct cfi_insn_data): New member "sym_name".
(CFI_label): New.
* read.c (read_symbol_name): Drop "static".
* read.h (read_symbol_name): Declare.
gas/testsuite/
2015-01-12 Jan Beulich <jbeulich@suse.com>
gas/cfi/cfi-label.d, gas/cfi/cfi-label.s: New.
gas/cfi/cfi.exp: Run new tests.
These two, other than VQSHLU, didn't have their immediates properly range
checked so far.
(Re-sending unchanged from the original v2 due to never having got an
answer to https://sourceware.org/ml/binutils/2013-04/msg00121.html.)
gas/
2015-01-12 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_neon_shl_imm): Check immediate range.
(do_neon_qshl_imm): Likewise.
gas/testsuite/
2015-01-12 Jan Beulich <jbeulich@suse.com>
* gas/arm/neon-addressing-bad.s: Add test for invalid VSHL,
VQSHL, and VQSHLU immediates.
* gas/arm/neon-addressing-bad.l: Update accordingly.
When fixups are converted to a difference type within md_apply_fix, we
previously left the contents of VALP (the value that was initially
computed within write.c:fixup_segment) unchanged. This is harmless,
except that this value is used within write.c:fixup_segment once we
return from md_apply_fix to perform an overflow check.
In some cases, the value computed in write.c:fixup_segment is so wrong
that an overflow error can be triggered. These errors are incorrect.
This patch avoids the overflow errors by adjusting the value in
write.c:fixup_segment using the VALP pointer in md_apply_fix.
A test for this issue is included.
gas/ChangeLog:
* config/tc-avr.c (md_apply_fix): Update the contents of VALP for
diff fixups.
gas/testsuite/ChangeLog:
* gas/avr/large-debug-line-table.d: New file.
* gas/avr/large-debug-line-table.s: New file.
Have the assembler prepare for linker relaxation by default. This
means that users will be able to make use of linker relaxation without
having to adjust the assembler flags, this can make life easier when
compiling libraries.
Having this on by default in the assembler should make no difference to
the assembler code produced, however, some of the debug information will
be slightly less compressed.
A few tests needed to be updated as a result of this change as they
relied on linker relaxation support being off by default.
I've tightened up the definition of which sections can be relaxed on AVR
as part of this commit, the assembler used to think that all
non-debugging sections could be relaxed, when in reality only code
sections can be relaxed for AVR. The previous definition was not
dangerous, just over cautious. The new tighter definition allows an
extra test (gas/testsuite/gas/all/forward.d) to continue to pass.
gas/ChangeLog:
* config/tc-avr.c (struct avr_opt_s): Change link_relax to
no_link_relax, extend comment.
(enum options): Add new OPTION_NO_LINK_RELAX.
(md_longopts): Add entry for -mno-link-relax.
(md_parse_option): Handle OPTION_NO_LINK_RELAX, and update
OPTION_LINK_RELAX.
(md_begin): Initialise linkrelax from no_link_relax.
(md_show_usage): Include -mno-link-relax option.
(relaxable_section): Only allocatable code sections can be
relaxed.
* config/tc-avr.h (TC_LINKRELAX_FIXUP): Define.
gas/testsuite/ChangeLog:
* gas/all/gas.exp: Test will not pass on AVR due to linker
relaxation support.
* gas/avr/noreloc_withoutrelax.d: Add -mno-link-relax option.
* gas/avr/link-relax-elf-flag-clear.d: Likewise.
ld/testsuite/ChangeLog:
* ld/testsuite/ld-avr/relax-elf-flags-02.d: Add -mno-link-relax
option.
* ld/testsuite/ld-avr/relax-elf-flags-03.d: Likewise.
* ld/testsuite/ld-avr/relax-elf-flags-04.d: Likewise.
* ld/testsuite/ld-avr/relax-elf-flags-05.d: Likewise.
* ld/testsuite/ld-avr/relax-elf-flags-06.d: Likewise.
The AVR target uses a bit in the elf header flags to indicate if the
object was assembled ready for linker relaxation. Previously this flag
was always set, even when the object was not assembled ready for linker
relaxation.
This patch moves setting of the flag into the assembler, and sets it
only when the assembler is preparing the file for linker relaxation.
bfd/ChangeLog:
* elf32-avr.c (bfd_elf_avr_final_write_processing): Don't set
EF_AVR_LINKRELAX_PREPARED unconditionally.
gas/ChangeLog:
* config/tc-avr.c: Add include for elf/avr.h.
(avr_elf_final_processing): New function.
* config/tc-avr.h (elf_tc_final_processing): Define.
(avr_elf_final_processing): Declare
gas/testsuite/ChangeLog:
* gas/avr/link-relax-elf-flag-clear.d: New file.
* gas/avr/link-relax-elf-flag-set.d: New file.
* gas/avr/link-relax-elf-flag.s: New file.
gas/
* config/tc-mips.c (md_apply_fix): Apply alignment check
to the symbol and offset rather than *valP for
BFD_RELOC_MIPS_18_PCREL_S3. Also update the error message
for BFD_RELOC_MIPS_19_PCREL_S2.
gas/testsuite/
* gas/mips/r6-64.s: Remove .align directives from LDPC
instructions and add further tests for LDPC.
* gas/mips/r6-64-n32.d: remove the NOPs from LDPC expected
output and update for new tests.
* gas/mips/r6-64-n64.d: Likewise.
* gas/mips/ldpc-unalign.l: New file.
* gas/mips/ldpc-unalign.s: Likewise.
* gas/mips/mips.exp: Run ldpc-unalign test.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add JALRC alias for JIALC.
Remove the operand from NAL.
gas/testsuite/
* gas/mips/r6.s: Test JALRC and NAL
* gas/mips/r6-n32.d: Add expected output for JALRC and NAL.
* gas/mips/r6-n64.d: Likewise.
* gas/mips/r6.d: Likewise.
On further reading of ISA manual it appears gas should have been
treating mftb and mftbu as extended mnemonics for mfspr, for ISA 2.03
and later.
opcodes/
* ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
power4 and later.
gas/testsuite/
* gas/ppc/a2.d: Update for mftb change.
* gas/ppc/476.d: Likewise.
For conditional branches that need more than one trampoline to reach its
target assembler couldn't always find suitable trampoline because
post-loop condition check was placed inside the loop, resulting in
premature loop termination. Move check outside the loop.
This fixes the following build errors seen when assembling huge files
produced by gcc:
Error: jump target out of range; no usable trampoline found
Error: operand 1 of 'j' has out of range value '307307'
2014-11-25 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (search_trampolines): Move post-loop
condition check outside the search loop.
gas/testsuite/
* gas/xtensa/trampoline.d: Add expected output for branches.
* gas/xtensa/trampoline.s: Add test case for branches.
gas/
2014-11-21 Terry Guo <terry.guo@arm.com>
* config/tc-arm.c (md_assemble): Do not consider relaxation.
(md_convert_frag): Test and set target arch attribute accordingly.
(aeabi_set_attribute_string): Turn it into a global function.
* config/tc-arm.h (md_post_relax_hook): Enable it for ARM target.
(aeabi_set_public_attributes): Declare it.
gas/testsuite/
2014-11-21 Terry Guo <terry.guo@arm.com>
* gas/arm/attr-arch-assumption.d: New file.
* gas/arm/attr-arch-assumption.s: Likewise.
ld/testsuite/
2014-11-21 Terry Guo <terry.guo@arm.com>
* ld-arm/tls-longplt-lib.s: Require ARMv6T2.
* ld-arm/tls-longplt.s: Likewise.
* ld-arm/tls-longplt-lib.d: Updated.
* ld-arm/tls-longplt.d: Likewise.
* config/tc-aarch64.c (warn_unpredictable_ldst): Check that transfer
registers are in the GP register set. Adjust warnings. Use correct
field member for address register.
* testsuite/gas/aarch64/diagnostic.l: Update.
Structions with R_X86_64_GOTTPOFF relocation must be encoded with REX
prefix even if it isn't required by destination register. Otherwise
linker can't safely perform IE -> LE optimization.
bfd/
PR ld/17482
* elf64-x86-64.c (elf_x86_64_relocate_section): Update comments
for IE->LE transition.
gas/
PR ld/17482
* config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix
for structions with R_X86_64_GOTTPOFF relocation for x32 if needed.
gas/testsuite/
PR ld/17482
* gas/i386/ilp32/x32-tls.d: New file.
* gas/i386/ilp32/x32-tls.s: Likewise.
ld/testsuite/
PR ld/17482
* ld-x86-64/tlsie4.dd: Updated.
bfd/
* elfxx-mips.c (update_mips_abiflags_isa): Add E_MIPS_ARCH_32R6
and E_MIPS_ARCH_64R6 support.
ld/testsuite/
* ld-mips-elf/abiflags-strip10-ph.d: New file.
* ld-mips-elf/mips-eld.exp: Run the new test.
gas/
* config/tc-mips.c (mips_elf_final_processing): Add INSN_ISA32R6
and INSN_ISA64R6 support.
gas/testsuite/
* gas/mips/elf_arch_mips32r6.d: New file.
* gas/mips/elf_arch_mips64r6.d: New file.
* gas/mips/mips.exp: Run the new tests.
binutils:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* readelf.c (print_mips_isa_ext): Print the value of Octeon3.
gas:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
(mips_cpu_info_table): Octeon3 enables virt ase.
* doc/c-mips.texi: Document octeon3 as an acceptable value for
-march=.
gas/testsuite:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* gas/mips/mips.exp: Add support for Octeon3 architecture.
Also add in support for running Octeon3 tests.
* gas/mips/octeon3.d: New test.
* gas/mips/octeon3.s: New test source.
opcodes:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* mips-dis.c (mips_arch_choices): Add octeon3.
* mips-opc.c (IOCT): Include INSN_OCTEON3.
(IOCT2): Likewise.
(IOCT3): New define.
(IVIRT): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
IVIRT instructions.
Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
operand for IOCT3.
bfd:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* archures.c: Add octeon3 for mips target.
* bfd-in2.h: Regenerate.
* bfd/cpu-mips.c: Define I_mipsocteon3.
nfo_struct): Add octeon3 support.
* bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for
octeon3.
(mips_set_isa_flags): Add support for octeon3.
(bfd_mips_isa_ext): Add bfd_mach_mips_octeon3.
(mips_mach_extensions): Make bfd_mach_mips_octeon3 an
extension of bfd_mach_mips_octeon2.
(print_mips_isa_ext): Print the value of Octeon3.
This makes sure `HAVE_CODE_COMPRESSION' evaluates correctly when the
`.insn' directive is used at the beginning of a source file before any
instructions have been produced and that ELF file header's MIPS16 and
microMIPS ASE flags are set correctly in the case where no instructions
have been produced other than with the said directive.
gas/
* config/tc-mips.c (s_insn): Set file options.
gas/testsuite/
* gas/mips/insn-opts.d: New test.
* gas/mips/insn-opts.s: New test source.
* gas/mips/mips.exp: Run the new test.
The construct being added to the cond.s test case otherwise triggered
both the "missing closing ..." and the "stray ..." (twice) warnings in
_find_end_of_line(). As that code fragments suggests, this is needed to
support (include) files that can be used for both assembler .include
and compiler #include directives.
The write.c change is to make gas report an error if reg_section
symbols should leak in future. The tc-i386.c change is the real fix.
Note that the error isn't the most helpful, "redefined symbol cannot
be used on reloc", but I'm not inclined to improve what is really an
internal gas error. reg_section symbols shouldn't leak..
gas/
PR 17493
* write.c (adjust_reloc_syms): Don't allow symbols in reg_section
to be reduced to reg_section section symbol.
* gas/config/tc-i386.c (i386_finalize_immediate): Reject all
reg_section immediates.
gas/testsuite/
* gas/i386/inval-equ-2.l: Adjust.
Hash lookup is silly when we can attach the line table info directly
to sections instead. Worse, hash lookup fails when we have multiple
sections with the same name.
gas/
* dwarf2dbg.c (all_segs_hash): Delete.
(get_line_subseg): Delete last_seg, last_subseg, last_line_subseg.
Retrieve line_seg for section via seg_info.
* subsegs.h (segment_info_typet): Add dwarf2_line_seg.
gas/testsuite/
* gas/elf/group2.d, * gas/elf/group2.s: New test.
* gas/elf/elf.exp: Run it.
bfd/
* aoutx.h (NAME (aout, machine_type)): Add mips32r6 and mips64r6.
* archures.c (bfd_architecture): Likewise.
* bfd-in2.h (bfd_architecture): Likewise.
(bfd_reloc_code_real): Add relocs BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
BFD_RELOC_MIPS_19_PCREL_S2.
* cpu-mips.c (arch_info_struct): Add mips32r6 and mips64r6.
* elf32-mips.c: Define relocs R_MIPS_PC21_S2, R_MIPS_PC26_S2
R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
* elf64-mips.c: Define REL, and RELA relocations R_MIPS_PC21_S2,
R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16
and R_MIPS_PCLO16.
(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
* elfn32-mips.c: Likewise.
* elfxx-mips.c (MIPSR6_P): New define.
(mipsr6_exec_plt_entry): New array.
(hi16_reloc_p): Add support for R_MIPS_PCHI16.
(lo16_reloc_p): Add support for R_MIPS_PCLO16.
(aligned_pcrel_reloc_p): New function.
(mips_elf_relocation_needs_la25_stub): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(mips_elf_calculate_relocation): Add support for relocs:
R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2,
R_MIPS_PCHI16 and R_MIPS_PCLO16.
(_bfd_elf_mips_mach): Add support for mips32r6 and mips64r6.
(mips_elf_add_lo16_rel_addend): Add support for R_MIPS_PCHI16.
(_bfd_mips_elf_check_relocs): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(_bfd_mips_elf_relocate_section): Add a check for unaligned
pc relative relocs.
(_bfd_mips_elf_finish_dynamic_symbol): Add support for MIPS r6
plt entry.
(mips_set_isa_flags): Add support for mips32r6 and mips64r6.
(_bfd_mips_elf_print_private_bfd_data): Likewise.
(mips_32bit_flags_p): Add support for mips32r6.
* libbfd.h (bfd_reloc_code_real_names): Add entries for
BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2,
BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2.
* reloc.c: Document relocs BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
BFD_RELOC_MIPS_19_PCREL_S2.
binutils/
* readelf.c (get_machine_flags): Add support for mips32r6 and
mips64r6.
elfcpp/
* mips.h (E_MIPS_ARCH_32R6, E_MIPS_ARCH_64R6): New enum constants.
gas/
* config/tc-mips.c (mips_nan2008): New static global.
(mips_flag_nan2008): Removed.
(LL_SC_FMT): New define.
(COP12_FMT): Updated.
(ISA_IS_R6): New define.
(ISA_HAS_64BIT_REGS): Add mips64r6.
(ISA_HAS_DROR): Likewise.
(ISA_HAS_64BIT_FPRS): Add mips32r6 and mips64r6.
(ISA_HAS_ROR): Likewise.
(ISA_HAS_ODD_SINGLE_FPR): Likewise.
(ISA_HAS_MXHC1): Likewise.
(hilo_interlocks): Likewise.
(md_longopts): Likewise.
(ISA_HAS_LEGACY_NAN): New define.
(options): Add OPTION_MIPS32R6 and OPTION_MIPS64R6.
(mips_ase): Add field rem_rev.
(mips_ases): Updated to add which ISA an ASE was removed in.
(mips_isa_rev): Add support for mips32r6 and mips64r6.
(mips_check_isa_supports_ase): Add support to check if an ASE
has been removed in the specified MIPS ISA revision.
(validate_mips_insn): Skip '-' character.
(macro_build): Likewise.
(mips_check_options): Prevent R6 working with fp32, mips16,
micromips, or branch relaxation.
(file_mips_check_options): Set R6 floating point registers to
64 bit. Also deal with the nan2008 option.
(limited_pcrel_reloc_p): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(operand_reg_mask): Add support for OP_SAME_RS_RT, OP_CHECK_PREV
and OP_NON_ZERO_REG.
(match_check_prev_operand): New static function.
(match_same_rs_rt_operand): New static function.
(match_non_zero_reg_operand): New static function.
(match_operand): Added entries for: OP_SAME_RS_RT, OP_CHECK_PREV
and OP_NON_ZERO_REG.
(insns_between): Added case to deal with forbidden slots.
(append_insn): Added support for relocs: BFD_RELOC_MIPS_21_PCREL_S2
and BFD_RELOC_MIPS_26_PCREL_S2.
(match_insn): Add support for operands -A, -B, +' and +". Also
skip '-' character.
(mips_percent_op): Add entries for %pcrel_hi and %pcrel_lo.
(md_parse_option): Add support for mips32r6 and mips64r6. Also
update the nan option handling.
(md_pcrel_from): Add cases for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2.
(mips_force_relocation): Prevent forced relaxation for MIPS r6.
(md_apply_fix): Add support for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(s_mipsset): Add support for mips32r6 and mips64r6.
(s_nan): Update to support the new nan2008 framework.
(tc_gen_reloc): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
BFD_RELOC_LO16_PCREL.
(mips_elf_final_processing): Updated to use the mips_nan2008.
(mips_cpu_info_table): Add entries for mips32r6 and mips64r6.
(macro): Enable ldc2, sdc2, ll, lld, swc2, sc, scd, cache, pref
macros for R6.
(mips_fix_adjustable): Make PC relative R6 relocations relative
to the symbol and not the section.
* configure.ac: Add support for mips32r6 and mips64r6.
* configure: Regenerate.
* doc/c-mips.texi: Document the -mips32r6 and -mips64r6 command line
options.
* doc/as.texinfo: Likewise.
gas/testsuite/
* gas/mips/24k-triple-stores-1.s: If testing for r6 prevent
non-supported instructions from being tested.
* gas/mips/24k-triple-stores-2.s: Likewise.
* gas/mips/24k-triple-stores-3.s: Likewise.
* gas/mips/24k-triple-stores-6.s: Likewise.
* gas/mips/beq.s: Likewise.
* gas/mips/eva.s: Likewise.
* gas/mips/ld-zero-3.s: Likewise.
* gas/mips/mips32-cp2.s: Likewise.
* gas/mips/mips32.s: Likewise.
* gas/mips/mips4.s: Likewise.
* gas/mips/add.s: Don't test the add instructions if r6, and
add padding.
* gas/mips/add.d: Check for a triple dot not a nop at the end of the
disassembly output.
* gas/mips/micromips@add.d: Likewise.
* gas/mips/mipsr6@24k-branch-delay-1.d: New file.
* gas/mips/mipsr6@24k-triple-stores-1.d: New file.
* gas/mips/mipsr6@24k-triple-stores-2-llsc.d: New file.
* gas/mips/mipsr6@24k-triple-stores-2.d: New file.
* gas/mips/mipsr6@24k-triple-stores-3.d: New file.
* gas/mips/mipsr6@24k-triple-stores-6.d: New file.
* gas/mips/mipsr6@add.d: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.s: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.s: New file.
* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.l: New file.
* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.s: New file.
* gas/mips/mipsr6@beq.d: New file.
* gas/mips/mipsr6@bge.d: New file.
* gas/mips/mipsr6@bgeu.d: New file.
* gas/mips/mipsr6@blt.d: New file.
* gas/mips/mipsr6@bltu.d: New file.
* gas/mips/mipsr6@branch-misc-1.d: New file.
* gas/mips/mipsr6@branch-misc-2-64.d: New file.
* gas/mips/mipsr6@branch-misc-2pic-64.d: New file.
* gas/mips/mipsr6@branch-misc-4-64.d: New file.
* gas/mips/mipsr6@cache.d: New file.
* gas/mips/mipsr6@eva.d: New file.
* gas/mips/mipsr6@jal-svr4pic-noreorder.d: New file.
* gas/mips/mipsr6@jal-svr4pic.d: New file.
* gas/mips/mipsr6@ld-zero-2.d: New file.
* gas/mips/mipsr6@ld-zero-3.d: New file.
* gas/mips/mipsr6@loc-swap-dis.d: New file.
* gas/mips/mipsr6@mips32-cp2.d: New file.
* gas/mips/mipsr6@mips32-imm.d: New file.
* gas/mips/mipsr6@mips32.d: New file.
* gas/mips/mipsr6@mips32r2.d: New file.
* gas/mips/mipsr6@mips4-fp.d: New file.
* gas/mips/mipsr6@mips4-fp.l: New file.
* gas/mips/mipsr6@mips4-fp.s: New file.
* gas/mips/mipsr6@mips4.d: New file.
* gas/mips/mipsr6@mips5-fp.d: New file.
* gas/mips/mipsr6@mips5-fp.l: New file.
* gas/mips/mipsr6@mips5-fp.s: New file.
* gas/mips/mipsr6@mips64.d: New file.
* gas/mips/mipsr6@msa-branch.d: New file.
* gas/mips/mipsr6@msa.d: New file.
* gas/mips/mipsr6@pref.d: New file.
* gas/mips/mipsr6@relax-swap3.d: New file.
* gas/mips/r6-64-n32.d: New file.
* gas/mips/r6-64-n64.d: New file.
* gas/mips/r6-64-removed.l: New file.
* gas/mips/r6-64-removed.s: New file.
* gas/mips/r6-64.s: New file.
* gas/mips/r6-attr-none-double.d: New file.
* gas/mips/r6-n32.d: New file.
* gas/mips/r6-n64.d: New file.
* gas/mips/r6-removed.l: New file.
* gas/mips/r6-removed.s: New file.
* gas/mips/r6.d: New file.
* gas/mips/r6.s: New file.
* gas/mips/mipsr6@mips32-dsp.d: New file.
* gas/mips/mipsr6@mips32-dspr2.d: New file.
* gas/mips/mipsr6@mips32r2-ill.l: New file.
* gas/mips/mipsr6@mips32r2-ill.s: New file.
* gas/mips/cache.s: Add r6 instruction varients.
* gas/mips/mips.exp: Add support for the mips32r6 and mips64r6
architectures. Also prevent non r6 supported tests from running.
Finally, add in support for running the new r6 tests.
(run_dump_test_arch): Add support for mipsr6 tests.
(run_list_test_arch): Add support for using files of the
form arch@testname.l .
include/elf/
* mips.h: Add relocs: R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
(E_MIPS_ARCH_32R6): New define.
(E_MIPS_ARCH_64R6): New define.
include/opcode/
* mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
+I, +O, +R, +:, +\, +", +;
(mips_check_prev_operand): New struct.
(INSN2_FORBIDDEN_SLOT): New define.
(INSN_ISA32R6): New define.
(INSN_ISA64R6): New define.
(INSN_UPTO32R6): New define.
(INSN_UPTO64R6): New define.
(mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
(ISA_MIPS32R6): New define.
(ISA_MIPS64R6): New define.
(CPU_MIPS32R6): New define.
(CPU_MIPS64R6): New define.
(cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
ld/
* ldmain.c (get_emulation): Add support for -mips32r6 and -mips64r6.
opcodes/
* mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
mips64r6.
(parse_mips_dis_option): Allow MSA and virtualization support for
mips64r6.
(mips_print_arg_state): Add fields dest_regno and seen_dest.
(mips_seen_register): New function.
(print_insn_arg): Refactored code to use mips_seen_register
function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
the register rather than aborting.
(print_insn_args): Add length argument. Add code to correctly
calculate the instruction address for pc relative instructions.
(validate_insn_args): New static function.
(print_insn_mips): Prevent jalx disassembling for r6. Use
validate_insn_args.
(print_insn_micromips): Use validate_insn_args.
all the arguments are valid.
* mips-formats.h (PREV_CHECK): New define.
* mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
-t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
(RD_pc): New define.
(FS): New define.
(I37): New define.
(I69): New define.
(mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
MIPS R6 instructions from MIPS R2 instructions.
gas/
* config/tc-arm.c (aeabi_set_public_attributes): Update intended_arch based
on the info we got during parsing.
(arm_handle_align): Make sure the p2align expanding logic under thumb
unchanged.
gas/testsuite/
* gas/arm/blx-bl-convert.d: New testcase.
* gas/arm/blx-bl-convert.l: Warning expectation.
* gas/arm/blx-bl-convert.s: Source file.
2014-08-21 Nathan Sidwell <nathan@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
opcodes/
* arm-dis.c (print_arm_address): Negate the GPR-relative offset
returned if the U bit is set.
2014-08-21 Paul Brook <paul@codesourcery.com>
gas/testsuite/
* gas/arm/arch7a-mp.d: Adjust according to `print_arm_address'
offset fix.
* gas/arm/arch7r-mp.d: Likewise.
The variables used to track insn state should be pushed down into the
private_data structure to avoid pollution across calls.
This also happens to fix the output when hitting comments/invalid insns
which needs to tweak a gas test.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
If the user gives us an unaligned PC, then dump an error as such.
Otherwise if you try to disassemble at an odd address, the output
will look weird (it'll read one byte earlier).
This can be seen in one of the gas tests where data is in the middle
of .text, so move the data to .data like it should be in the first place.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
gas/
* read.c (assign_symbol): Don't force "set" symbols local for PE.
gas/testsuite/
* gas/pe/set.s, * gas/pe/set.d: New test.
* gas/pe/pe.exp: Run it.
At some point the arm-elf output became the same as arm-eabi. Remove
the special handling of arm-elf.
gas/testsuite/ChangeLog:
2014-07-10 Will Newton <will.newton@linaro.org>
* gas/elf/elf.exp: Remove special handling of arm-elf for
section2 test.
* gas/elf/section2.e-armeabi: Rename to...
* gas/elf/section2.e-arm: ...here.
* gas/elf/section2.e-armelf: Remove file.
With this change all gas and most ld tests pass when configured for
arm-linux. It doesn't look like these configurations have been
tested in a long time but this attempts to stem the bit-rot slightly.
gas/testsuite/ChangeLog:
2014-07-10 Will Newton <will.newton@linaro.org>
* gas/arm/bl-local-2.d: Only enable the test on EABI and
NaCl configurations.
* gas/arm/bl-local-v4t.d: Likewise.
* gas/arm/blx-local.d: Likewise.
* gas/arm/branch-reloc.d: Likewise.
ld/testsuite/ChangeLog:
2014-07-10 Will Newton <will.newton@linaro.org>
* ld-arm/arm-elf.exp (armelftests_nonacl): Move Cortex-A8 fix
tests, IFUNC tests and other EABI requiring tests to...
(armeabitests_nonacl): ...here.
* ld-arm/arm-app-abs32.d: Loosen regex for architecture type
to allow test to pass on configurations without an attributes
section.
* ld-arm/arm-app.d: Likewise.
* ld-arm/arm-lib-plt32.d: Likewise.
* ld-arm/arm-lib.d: Likewise.
* ld-arm/arm-static-app.d: Likewise.
* ld-arm/armthumb-lib.d: Likewise.
* ld-arm/cortex-a8-far.d: Likewise.
* ld-arm/farcall-mixed-app.d: Likewise.
* ld-arm/farcall-mixed-lib-v4t.d: Likewise.
* ld-arm/farcall-mixed-lib.d: Likewise.
* ld-arm/mixed-app-v5.d: Likewise.
* ld-arm/mixed-app.d: Likewise.
* ld-arm/mixed-lib.d: Likewise.
* ld-arm/tls-app.d: Likewise.
* ld-arm/tls-descrelax-be32.d: Likewise.
* ld-arm/tls-descrelax.d: Likewise.
* ld-arm/tls-descseq.d: Likewise.
* ld-arm/tls-gdesc-got.d: Likewise.
* ld-arm/tls-gdesc.d: Likewise.
* ld-arm/tls-gdierelax.d: Likewise.
* ld-arm/tls-gdierelax2.d: Likewise.
* ld-arm/tls-gdlerelax.d: Likewise.
* ld-arm/tls-lib-loc.d: Likewise.
* ld-arm/tls-lib.d: Likewise.
* ld-arm/tls-thumb1.d: Likewise.
* config/tc-arm.c (literal_pool): New field "alignment".
(find_or_make_literal_pool): Initialize "alignment" to 2.
(s_ltorg): Align the pool using value of "alignment"
(parse_big_immediate): New parameter "in_exp". Return
parsed expression if "in_exp" is not null.
(parse_address_main): Invoke "parse_big_immediate" for
constant parameter.
(add_to_lit_pool): Add one parameter 'nbytes'.
Split 8 byte entry into two 4 byte entry.
Add padding to align 8 byte entry to 8 byte boundary.
(encode_arm_cp_address): Generate literal pool entry if possible.
(move_or_literal_pool): Generate entry for vldr case.
(enum lit_type): New enum type.
(do_ldst): Use new enum type.
(do_ldstv4): Likewise.
(do_t_ldst): Likewise.
(neon_write_immbits): Support Thumb-2 mode.
* gas/arm/ldconst.s: Add test cases for symbol literal.
* gas/arm/ldconst.d: Likewise.
* gas/arm/vldconst.s: Add test cases for vldr.
* gas/arm/thumb2_vpool.s: Likewise.
* gas/arm/vldconst.d: New pattern for little-endian.
* gas/arm/thumb2_vpool.d: Likewise.
* gas/arm/vldconst_be.d: New pattern for big-endian.
* gas/arm/thumb2_vpool_be.d: Likewise.
Add sp increment and decrement to ARMv8 IT block deprecate
pattern.
gas/
* config/tc-arm.c (depr_it_insns): New check for inc/dec sp.
gas/testsuite/
* gas/arm/armv8-a-it-bad.s: New check for inc/dec sp.
* gas/arm/armv8-a-it-bad.l: Likewise.
a syntax error is detected in an optional operand.
* config/tc-aarch64.c (END_OF_INSN): New macro.
(parse_operands): Handle operand given and be in wrong
format when operand is optional.
* gas/aarch64/diagnostic.s: New test patterns.
* gas/aarch64/diagnostic.l: Likewise.
This is to fix unitialised memory access when printing listings.
Many targets don't initialise parts of insn frags or data frags that
have fixups, relying on md_apply_fix to finalise the frag. Which is
fine normally, but means we need to run write_object_file after
errors, for listings. Otherwise MALLOC_PERTURB_=1 causes errors like:
x86_64-linux +FAIL: i386 mpx-inval-1
x86_64-linux +FAIL: i386 inval-equ-1
x86_64-linux +FAIL: i386 x86-64-mpx-inval-1
Running write_object_file after errors requires some tweaking to the
testsuite, since we then get extra errors reported from md_apply_fix.
gas/
* write.h (subsegs_finish): Delete declaration.
* write.c (subsegs_finish): Make static.
(write_object_file): Call subsegs_finish from here. Don't print
warning and error count here..
* as.c (main): ..do so here instead. Remove dead code for "no
object file generated". Split out count strings to better support
internationalisation. Don't call subsegs_finish. Tidy setting of
"keep_it". Run write_object_file even after errors.
(keep_it): Make static.
* config/obj-elf.c (elf_frob_symbol): Remove assert.
(elf_frob_file_before_adjust): Likewise.
gas/testsuite/
* gas/elf/bad-group.s: Use %function.
* gas/elf/bad-group.err: Expect correct line number. Allow
other errors.
* gas/elf/bad-size.err: Allow other errors. Match expected
error somewhat more rigorously.
* gas/i386/reloc32.l: Allow other errors.
* gas/i386/mpx-inval-1.l: Match applied relocs.
* gas/i386/x86-64-mpx-inval-1.l: Likewise, and nop padding.
* gas/i386/x86-64-mpx-inval-2.l: Match nop padding, and allow
other errors.
* gas/macros/dot.s: Use .balign.
* gas/macros/dot.l: Update alignment output.
* gas/symver/symver6.l: Allow other errors.
MALLOC_PERTURB_=1 results in "FAIL: VAX ELF relocations", due to object
file being emitted with uninitialised fields. Since these fields had
RELA relocs the field value won't be used at final link time, so the
problem is only seen in relocatable object files.
This rewrite of md_apply_fix clears all fields with relocs, whereas
before some fields had non-zero values.
gas/
* config/tc-vax.c (md_apply_fix): Rewrite.
(tc_gen_reloc, vax_cons, vax_cons_fix_new): Style: Use NO_RELOC
define rather than the equivalent BFD_RELOC_NONE.
gas/testsuite/
* gas/vax/elf-rel.d: Update.
gas/
* config/tc-cris.c (md_create_long_jump): Follow "short" jump
with a nop rather than leaving uninitialised.
gas/testsuite/
* gas/cris/rd-bkw4v32.d: Update.
* config/tc-msp430.c (OPTION_WARN_INTR_NOPS): Use y instead of z.
(OPTION_NO_WARN_INTR_NOPS): Use Y instead of Z.
* doc/c-msp430.texi: Update command line option description.
* gas/msp430/bad.d: Use -my not -mz.
gas/
* config/tc-mips.c (file_mips_opts_checked): New static global.
(s_module): New static function.
(file_ase): Remove.
(mips_pseudo_table): Add .module handler.
(mips_set_ase): Add opts argument and use instead of mips_opts.
(md_assemble): Use file_mips_check_options.
(md_parse_option): Update to use file_mips_opts instead of mips_opts.
(mips_set_architecture): Delete function. Moved to...
(mips_after_parse_args): Here. All logic now applies to
file_mips_opts first and then copies the final state to mips_opts.
Move error checking and defaults inference to mips_check_options and
file_mips_check_options.
(mips_check_options): New static function. Common option checking for
command line, .module and .set. Use .module values in error messages
instead of refering to command line options.
(file_mips_check_options): New static function. A wrapper for
mips_check_options with file_mips_opts. Updates BFD arch based on
final options.
(s_mipsset): Split into s_mipsset and parse_code_option. Settings
supported by both .set and .module are moved to parse_code_option.
Warnings and errors are kept in s_mipsset because when
parse_code_option is used with s_module the warnings are deferred
until code is generated. Any setting supporting 'default' value is
kept in s_mipsset as it is not applicable to s_module. Inferred
settings are also kept in s_mipsset as s_module does not infer any
settings. Use mips_check_options.
(parse_code_option): New static function derived from s_mipsset.
(s_module): New static function that implements .module. Allows file
level settings to be changed until code is generated.
(s_cpload, s_cpsetup, s_cplocal): Use file_mips_check_options.
(s_cprestore, s_cpreturn, s_cpadd, mips_address_bytes): Likewise.
(mips_elf_final_processing): Update file_ase to file_mips_opts.ase.
(md_mips_end): Use file_mips_check_options.
* doc/c-mips.texi: Document .module.
gas/testsuite
* gas/mips/mips.exp: Add new tests. Use 64-bit ABI for relax-bc1any.
Fix micromips arch definition to use mips64r2 consistently.
* gas/mips/module-defer-warn1.s: New.
* gas/mips/module-defer-warn1.d: New.
* gas/mips/module-defer-warn2.s: New.
* gas/mips/module-defer-warn2.l: New.
* gas/mips/module-override.d: New.
* gas/mips/module-override.s: New.
* gas/mips/mips-gp32-fp64.l: Update expected output.
* gas/mips/mips-gp64-fp32-pic.l: Update expected output.
* gas/mips/mips-gp64-fp32.l: Update expected output.
* config/tc-msp430.c (CHECK_RELOC_MSP430): Add OP parameter.
Generate BFD_RELOC_MSP430_ABS_HI16 if vshift is 1.
(msp430_srcoperand): Store vshift value in operand.
* msp430.h (struct msp430_operand_s): Add vshift field.
* gas/elf/struct.d: Expect extra output from some toolchains.
* gas/symver/symver0.d: Likewise.
* gas/symver/symver1.d: Likewise.
This patch firstly adds support for mips32r3 mips32r5, mips64r3
and mips64r5. Secondly it adds support for the eretnc instruction.
ChangeLog:
bfd/
* aoutx.h (NAME (aout, machine_type)): Add mips32r3, mips64r3,
mips32r5 and mips64r5.
* archures.c (bfd_architecture): Likewise.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (arch_info_struct): Likewise.
* elfxx-mips.c (mips_set_isa_flags): Likewise.
gas/
* tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3
and mips64r5.
(ISA_HAS_64BIT_FPRS): Likewise.
(ISA_HAS_ROR): Likewise.
(ISA_HAS_ODD_SINGLE_FPR): Likewise.
(ISA_HAS_MXHC1): Likewise.
(hilo_interlocks): Likewise.
(md_longopts): Likewise.
(ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5.
(ISA_HAS_DROR): Likewise.
(options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and
OPTION_MIPS64R5.
(mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
(md_parse_option): Likewise.
(s_mipsset): Likewise.
(mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3
and mips64r5. Also change p5600 entry to be mips32r5.
* configure.in: Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
* configure: Regenerate.
* doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and
-mips64r5 command line options.
* doc/as.texinfo: Likewise.
gas/testsuite/
* gas/mips/mips.exp: Add MIPS32r5 tests. Also add the mips32r3,
mips32r5, mips64r3 and mips64r5 isas to the testsuite.
* gas/mips/r5.s: New test.
* gas/mips/r5.d: Likewise.
include/opcode/
* mips.h (INSN_ISA_MASK): Updated.
(INSN_ISA32R3): New define.
(INSN_ISA32R5): New define.
(INSN_ISA64R3): New define.
(INSN_ISA64R5): New define.
(INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
(mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
mips64r5.
(INSN_UPTO32R3): New define.
(INSN_UPTO32R5): New define.
(INSN_UPTO64R3): New define.
(INSN_UPTO64R5): New define.
(ISA_MIPS32R3): New define.
(ISA_MIPS32R5): New define.
(ISA_MIPS64R3): New define.
(ISA_MIPS64R5): New define.
(CPU_MIPS32R3): New define.
(CPU_MIPS32R5): New define.
(CPU_MIPS64R3): New define.
(CPU_MIPS64R5): New define.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
(I34): New define.
(I36): New define.
(I66): New define.
(I68): New define.
* mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
mips64r5.
(parse_mips_dis_option): Update MSA and virtualization support to
allow mips64r3 and mips64r5.
This patch updates multiple opcode prefix processing:
1. Always print prefix together with bad opcode.
2. Since the last seen segment register prefix is active, we only print
the active segment register in the memory operand.
3. The 0xf2 and 0xf3 prefixes take precedence over the 0x66 prefix as the
opcode prefix. Also the last of the 0xf2 and 0xf3 prefixes wins.
4. Ignore invalid 0xf2/0xf3 prefixes if they aren't mandatory.
gas/testsuite/
PR binutils/16893
* gas/i386/katmai.d: Expect "gs" as prefix.
* gas/i386/long-1.s: Replace movapd with movss.
* gas/i386/x86-64-long-1.s: Likewise.
* gas/i386/long-1-intel.d: Updated.
* gas/i386/long-1.d: Likewise.
* gas/i386/x86-64-long-1-intel.d: Likewise.
* gas/i386/x86-64-long-1.d: Likewise.
* gas/i386/prefix.s: Add tests for multiple 0x66, 0x67, 0xf0,
0xf2 and 0xf3 prefixes.
* gas/i386/prefix.d: Updated.
opcodes/
PR binutils/16893
* i386-dis.c (twobyte_has_mandatory_prefix): New variable.
(end_codep): Likewise.
(mandatory_prefix): Likewise.
(active_seg_prefix): Likewise.
(ckprefix): Set active_seg_prefix to the active segment register
prefix.
(seg_prefix): Removed.
(get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
for prefix index. Ignore the index if it is invalid and the
mandatory prefix isn't required.
(print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
in used_prefixes here. Don't print unused prefixes. Check
active_seg_prefix for the active segment register prefix.
Restore the DFLAG bit in sizeflag if the data size prefix is
unused. Check the unused mandatory PREFIX_XXX prefixes
(append_seg): Only print the segment register which gets used.
(OP_E_memory): Check active_seg_prefix for the segment register
prefix.
(OP_OFF): Likewise.
(OP_OFF64): Likewise.
(OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
* gas/i386/opcode-intel.d: Undo the last change.
* gas/i386/opcode-suffix.d: Likewise.
* gas/i386/opcode.d: Likewise.
* gas/i386/opcode.s: Likewise.
* gas/i386/prefix.s: Add test for fwait with prefix.
* gas/i386/prefix.d: Updated.
0x9b (fwait) is both an instruction and an opcode prefix. When 0x9b is
treated as an instruction, we need to handle any prefixes before it.
This patch handles it properly.
gas/testsuite/
PR binutils/16891
* gas/i386/opcode.s: Add test for fwait with prefix.
* gas/i386/opcode-intel.d: Updated.
* gas/i386/opcode-suffix.d: Likewise.
* gas/i386/opcode.d: Likewise.
opcodes/
PR binutils/16891
* i386-dis.c (print_insn): Handle prefixes before fwait.
Fix various places where endianness needed to be taken into account
in the gas testsuite for ARM.
gas/testsuite/ChangeLog:
2014-04-23 Will Newton <will.newton@linaro.org>
* gas/arm/backslash-at.d: Fix dump output regexps for
armeb-linux-eabi configuration.
* gas/arm/got_prel.d: Likewise.
* gas/arm/inst-po.d: Likewise.
* gas/arm/unwind.d: Likewise.
If there is a a trailing align statement in a code section we may
output data padding with a data mapping followed by a code alignment
with a code mapping. The literal pool may then be output with a code
mapping symbol which will cause it to be endian swapped in a big-endian
configuration. When outputting a literal pool make sure that a data
mapping symbol is output in all cases.
gas/ChangeLog:
2014-04-23 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (s_ltorg): Call make_mapping_symbol
directly instead of mapping_state.
gas/testsuite/ChangeLog:
2014-04-23 Will Newton <will.newton@linaro.org>
* gas/arm/mapmisc.d: Check literal pool mapping with
a trailing .align statement.
* gas/arm/mapmisc.s: Likewise.
ChangeLog:
binutils/
* doc/binutils.texi: Document the disassemble MIPS XPA instructions
command line option.
gas/
* config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA.
(md_longopts): Add xpa and no-xpa command line options.
(mips_ases): Add MIPS XPA ASE.
(mips_cpu_info_table): Update p5600 entry to allow the XPA ASE.
* doc/as.texinfo: Document the MIPS XPA command line options.
* doc/c-mips.texi: Document the MIPS XPA command line options,
and assembler directives.
gas/testsuite/
* gas/mips/mips.exp: Add xpa tests.
* gas/mips/xpa.s: New test.
* gas/mips/xpa.d: Likewise.
include/
* opcode/mips.h (ASE_XPA): New define.
opcodes/
* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
to allow the MIPS XPA ASE.
(parse_mips_dis_option): Process the -Mxpa option.
* mips-opc.c (XPA): New define.
(mips_builtin_opcodes): Add MIPS XPA instructions and move the
locations of the ctc0 and cfc0 instructions.
Linking object files produced by partial linking with link-time
relaxation enabled sometimes fails with the following error message:
dangerous relocation: call8: misaligned call target: (.text.unlikely+0x63)
This happens because no basic block with an XTENSA_PROP_ALIGN flag in the
property table is generated for the first basic block, even if the
.align directive is present.
It was believed that the first frag alignment could be derived from the
section alignment, but this was not implemented for the partial linking
case: after partial linking first frag of a section may become not
first, but no additional alignment frag is inserted before it.
Basic block for such frag may be merged with previous basic block into
extended basic block during relaxation pass losing its alignment
restrictions.
Fix this by always recording alignment for the first section frag.
2014-04-22 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (xtensa_handle_align): record alignment for the
first section frag.
gas/testsuite/
* gas/xtensa/all.exp: Add test for the first section frag alignment.
* gas/xtensa/first_frag_align.d: First section frag alignment expected
dump.
* gas/xtensa/first_frag_align.s: First section frag alignment test
source.
(enum options): add OPTION_RMW_ISA for -mrmw option.
(struct option md_longopts): Add mrmw option.
(md_show_usage): add -mrmw option description.
(md_parse_option): Update isa details if -mrmw option specified.
* doc/c-avr.texi: Add doc for new option -mrmw.
* gas/avr/avr.exp: Run new tests.
* gas/avr/rmw.d: Add test for additional ISA support.
* gas/avr/rmw.s: Ditto.
(enum options): add OPTION_RMW_ISA for -mrmw option.
(struct option md_longopts): Add mrmw option.
(md_show_usage): add -mrmw option description.
(md_parse_option): Update isa details if -mrmw option specified.
* doc/c-avr.texi: Add doc for new option -mrmw.
* gas/avr/avr.exp: Run new tests.
* gas/avr/rmw.d: Add test for additional ISA support.
* gas/avr/rmw.s: Ditto.
For gathers with indices larger than elements (e. g.)
vpgatherqd ymm6{k1}, ZMMWORD PTR [ebp+zmm7*8-123]
We currently treat memory size as a size of index register, while it is
actually should be size of destination register:
vpgatherqd ymm6{k1}, YMMWORD PTR [ebp+zmm7*8-123]
This patch fixes it.
opcodes/
* i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
vscatterqps.
* i386-tbl.h: Regenerate.
gas/testsuite/
* gas/i386/avx512pf-intel.d: Change memory size for vgatherpf0qps,
vgatherpf1qps, vscatterpf0qps, vscatterpf1qps.
* gas/i386/avx512pf.s: Ditto.
* gas/i386/x86-64-avx512pf-intel.d: Ditto.
* gas/i386/x86-64-avx512pf.s: Ditto.
* gas/i386/avx512f-intel.d: Change memory size for vgatherqps,
vpgatherqd, vpscatterqd, vscatterqps.
* gas/i386/avx512f.s: Ditto.
* gas/i386/x86-64-avx512f-intel.d: Ditto.
* gas/i386/x86-64-avx512f.s: Ditto.
and %hstick_enable to the Sparc assembler.
* config/tc-sparc.c (hpriv_reg_table): Added entries for
%hstick_offset and %hstick_enable.
* doc/c-sparc.texi (Sparc-Regs): Document the %hstick_offset and
%hstick_enable hyperprivileged registers.
* sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
%hstick_enable added.
* gas/sparc/rdhpr.s: Test rd %hstick_offset and %hstick_enable.
* gas/sparc/rdhpr.d: Likewise.
* gas/sparc/wrhpr.s: Test wr %hstick_offset and %hstick_enable.
* gas/sparc/wrhpr.d: Likewise.
* config/tc-arm.c (codecomposer_syntax): New flag that states whether the
CCS syntax compatibility mode is on or off.
(asmfunc_states): New enum to represent the asmfunc directive state.
(asmfunc_state): New variable holding the asmfunc directive state.
(comment_chars): Rename to arm_comment_chars.
(line_separator_chars): Rename to arm_line_separator_chars.
(s_ccs_ref): New function that handles the .ref directive.
(asmfunc_debug): New function.
(s_ccs_asmfunc): New function that handles the .asmfunc directive.
(s_ccs_endasmfunc): New function that handles the .endasmfunc directive.
(s_ccs_def): New function that handles the .def directive.
(tc_start_label_without_colon): New function.
(md_pseudo_table): Added new CCS directives.
(arm_ccs_mode): New function that handles the -mccs command line option.
(arm_long_opts): Added new -mccs command line option.
* config/tc-arm.h (LABELS_WITHOUT_COLONS): New macro.
(TC_START_LABEL_WITHOUT_COLON): New macro.
(tc_start_label_without_colon): Added extern function declaration.
(tc_comment_chars): Define.
(tc_line_separator_chars): Define.
* app.c (do_scrub_begin): Use tc_line_separator_chars, if defined.
* read.c (read_begin): Likewise.
* doc/as.texinfo: Add documentation for the -mccs command line
option.
* doc/c-arm.texi: Likewise.
* doc/internals.texi: Document tc_line_separator_chars.
* NEWS: Mention the new feature.
* gas/arm/ccs.s: New test case.
* gas/arm/ccs.d: New expected disassembly.
* rx-decode.opc (bwl): Allow for bogus instructions with a size
field of 3.
(sbwl, ubwl, SCALE): Likewise.
* rx-decode.c: Regenerate.
* gas/rx/mov.d: Update expected disassembly.
bfd/
* peicode.h (pe_ILF_object_p): Adjust, as the version number
has been read.
(pe_bfd_object_p): Also read version number to detect ILF.
* pe-x86_64.c (COFF_WITH_PE_BIGOBJ): Define.
(x86_64pe_bigobj_vec): Define
* coffcode.h (bfd_coff_backend_data): Add _bfd_coff_max_nscns field.
(bfd_coff_max_nscns): New macro.
(coff_compute_section_file_positions): Use unsigned int for
target_index. Compare with bfd_coff_max_nscns.
(bfd_coff_std_swap_table, ticoff0_swap_table, ticoff1_swap_table):
Set a value for _bfd_coff_max_nscns.
(header_bigobj_classid): New constant.
(coff_bigobj_swap_filehdr_in, coff_bigobj_swap_filehdr_out)
(coff_bigobj_swap_sym_in, coff_bigobj_swap_sym_out)
(coff_bigobj_swap_aux_in, coff_bigobj_swap_aux_out): New
functions.
(bigobj_swap_table): New table.
* libcoff.h: Regenerate.
* coff-sh.c (bfd_coff_small_swap_table): Likewise.
* coff-alpha.c (alpha_ecoff_backend_data): Add value for
_bfd_coff_max_nscns.
* coff-mips.c (mips_ecoff_backend_data): Likewise.
* coff-rs6000.c (bfd_xcoff_backend_data)
(bfd_pmac_xcoff_backend_data): Likewise.
* coff64-rs6000.c (bfd_xcoff_backend_data)
(bfd_xcoff_aix5_backend_data): Likewise.
* targets.c (x86_64pe_bigobj_vec): Declare.
* configure.in (x86_64pe_bigobj_vec): New vector.
* configure: Regenerate.
* config.bfd: Add bigobj object format for Windows targets.
gas/
* config/tc-i386.c (use_big_obj): Declare.
(OPTION_MBIG_OBJ): Define.
(md_longopts): Add -mbig-obj option.
(md_parse_option): Handle it.
(md_show_usage): Display help for this option.
(i386_target_format): Use bigobj for x86-64 if -mbig-obj.
* doc/c-i386.texi: Document the option.
gas/testsuite/
* gas/pe/big-obj.d, gas/pe/big-obj.s: Add test.
* gas/pe/pe.exp: Add test.
include/coff/
* pe.h (struct external_ANON_OBJECT_HEADER_BIGOBJ): Declare.
(FILHSZ_BIGOBJ): Define.
(struct external_SYMBOL_EX): Declare.
(SYMENT_BIGOBJ, SYMESZ_BIGOBJ): Define.
(union external_AUX_SYMBOL_EX): Declare.
(AUXENT_BIGOBJ, AUXESZ_BIGOBJ): Define.
* internal.h (struct internal_filehdr): Change type
of f_nscns.
that if multiple bignum values are encountered only the most recent is valid.
If such expressions are cached, eg to be emitted into a literal pool later on
in the assembly, then only one expression - the last - will be correct. This
patch fixes the problem for the AArch64 target by caching each bignum value
locally.
PR gas/16688
* config/tc-aarch64.c (literal_expression): New structure.
(literal_pool): Replace exp array with literal_expression array.
(add_to_lit_pool): When adding a bignum cache the big value.
(s_ltorg): When emitting a bignum initialise the global bignum
array from the cached value.
* gas/aarch64/litpool.s: New test case.
* gas/aarch64/litpool.d: Expected disassembly.
generate warning messages about an instruction that changes the interrupt
state not being followed by a NOP instruction.
* config/msp430/msp430.c: Replace known mcu array with known
msp430 ISA mcu name array.
Accept any name for -mmcu option.
Add -mz option to warn about missing NOP following an interrupt
status change.
(check_for_nop): New.
(msp430_operands): Emit a warning, if requested, when an interrupt
changing instruction is not followed by a NOP.
* doc/c-msp430.c: Document -mz option.
* gas/msp430/bad.d: Add -mz option.
* gas/msp430/bad.s: Add more cases where warnings should be
generated.
* gas/msp430/bad.l: Add expected warning messages.
SHF_INFO_LINK bit set, which shows up in readelf section dumps. This
has broken a couple of IA64 testcases in the gas testsuite, which are
fixed by this patch.
PR binutils/16317
* gas/ia64/group-2.d: Expect I attribute with RELA sections.
* gas/ia64/xdata.d: Likewise.
The direct rounding floating-point VCVT instructions introduced in
ARMv8 encode the s32.f64 variant incorrectly. The op bit should be
set to 1 for all signed conversions.
gas/ChangeLog:
2014-01-17 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (do_vfp_nsyn_cvt_fpv8): Set OP to 1
for the s32.f64 flavours of VCVT.
gas/testsuite/ChangeLog:
2014-01-17 Will Newton <will.newton@linaro.org>
* gas/arm/armv8-a+fp.d: Correct encoding of vcvta.s32.f64.
