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[AArch64] Fix mis-detection of unpredictable load/store operations with FP regs.

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* config/tc-aarch64.c (warn_unpredictable_ldst): Check that transfer
	registers are in the GP register set.  Adjust warnings.  Use correct
	field member for address register.
	* testsuite/gas/aarch64/diagnostic.l: Update.
This commit is contained in:
Richard Earnshaw 2014-11-20 15:28:52 +00:00
parent 0cfb071748
commit 5c47e52589
3 changed files with 25 additions and 11 deletions
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7
gas/ChangeLog
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@ -1,3 +1,10 @@
2014-11-20 Richard Earnshaw <rearnsha@arm.com>
* config/tc-aarch64.c (warn_unpredictable_ldst): Check that transfer
registers are in the GP register set. Adjust warnings. Use correct
field member for address register.
* testsuite/gas/aarch64/diagnostic.l: Update.
2014-11-19 Ryan Mansfield <rmansfield@qnx.com>
* config/tc-aarch64.c (md_assemble): Call warn_unpredictable_ldst.

19
gas/config/tc-aarch64.c
View file

@ -5490,7 +5490,7 @@ programmer_friendly_fixup (aarch64_instruction *instr)
return TRUE;
}
/* Check for loads and stores that will cause unpredictable behavior */
/* Check for loads and stores that will cause unpredictable behavior. */
static void
warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
@ -5504,17 +5504,24 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
case ldst_imm9:
case ldst_unscaled:
case ldst_unpriv:
if (opnds[0].reg.regno == opnds[1].reg.regno
/* Loading/storing the base register is unpredictable if writeback. */
if ((aarch64_get_operand_class (opnds[0].type)
== AARCH64_OPND_CLASS_INT_REG)
&& opnds[0].reg.regno == opnds[1].addr.base_regno
&& opnds[1].addr.writeback)
as_warn (_("unpredictable register after writeback -- `%s'"), str);
as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
break;
case ldstpair_off:
case ldstnapair_offs:
case ldstpair_indexed:
if ((opnds[0].reg.regno == opnds[2].reg.regno
|| opnds[1].reg.regno == opnds[2].reg.regno)
/* Loading/storing the base register is unpredictable if writeback. */
if ((aarch64_get_operand_class (opnds[0].type)
== AARCH64_OPND_CLASS_INT_REG)
&& (opnds[0].reg.regno == opnds[2].addr.base_regno
|| opnds[1].reg.regno == opnds[2].addr.base_regno)
&& opnds[2].addr.writeback)
as_warn (_("unpredictable register after writeback -- `%s'"), str);
as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
/* Load operations must load different registers. */
if ((opcode->opcode & (1 << 22))
&& opnds[0].reg.regno == opnds[1].reg.regno)
as_warn (_("unpredictable load of register pair -- `%s'"), str);

10
gas/testsuite/gas/aarch64/diagnostic.l
View file

@ -109,8 +109,8 @@
[^:]*:116: Warning: unpredictable load of register pair -- `ldp d0,d0,\[sp\]'
[^:]*:117: Warning: unpredictable load of register pair -- `ldp x0,x0,\[sp\],#16'
[^:]*:118: Warning: unpredictable load of register pair -- `ldnp x0,x0,\[sp\]'
[^:]*:121: Warning: unpredictable register after writeback -- `ldr x0,\[x0,#8\]!'
[^:]*:122: Warning: unpredictable register after writeback -- `str x0,\[x0,#8\]!'
[^:]*:123: Warning: unpredictable register after writeback -- `str x1,\[x1\],#8'
[^:]*:124: Warning: unpredictable register after writeback -- `stp x0,x1,\[x0,#16\]!'
[^:]*:125: Warning: unpredictable register after writeback -- `ldp x0,x1,\[x1\],#16'
[^:]*:121: Warning: unpredictable transfer with writeback -- `ldr x0,\[x0,#8\]!'
[^:]*:122: Warning: unpredictable transfer with writeback -- `str x0,\[x0,#8\]!'
[^:]*:123: Warning: unpredictable transfer with writeback -- `str x1,\[x1\],#8'
[^:]*:124: Warning: unpredictable transfer with writeback -- `stp x0,x1,\[x0,#16\]!'
[^:]*:125: Warning: unpredictable transfer with writeback -- `ldp x0,x1,\[x1\],#16'