Commit graph

58 commits

Author SHA1 Message Date
Marcus Shawcroft
1ada945d05 [AArch64] Add support for :tlsdesc: and TLSDESC_LD_PREL19 2015-02-26 22:59:23 +00:00
Marcus Shawcroft
389b8029b6 [AArch64] Add support for :tlsdesc: and TLSDESC_ADR_PREL21 2015-02-26 22:59:16 +00:00
Marcus Shawcroft
3c12b05436 Add ADR :tlsgd: directive and TLSGD_ADR_PREL21 support. 2015-02-26 22:23:09 +00:00
Marcus Shawcroft
043bf05a3d Adding support for TLSIE_LD_GOTTREL_PREL19. 2015-02-26 22:23:09 +00:00
Marcus Shawcroft
74ad790c76 Adding ld_literal_type.
Extend the address modifier parsing to distinguish between the
modifers used in LDR literal and LDR register offset address modes.

The current parser incorrectly accepts the :got: modifier on a
register offset instruction resulting in silent corruption of the
output binary.
2015-02-26 22:23:09 +00:00
Marcus Shawcroft
6f4a313ba4 Adding adr_type and prevent adr :got:
The current implementation of the :got: assembler modifier does not
distinguish the ADR and ADRP instruction.  The :got: modifier does not
make sense on and ADR instruction and should be error'd rather than
the current behavior of applying an inappropriate relocation to the
output and scrambling the underlying instruction silently.
2015-02-26 22:23:09 +00:00
Marcus Shawcroft
1db365dcdf Remove dead code. 2015-02-26 22:23:08 +00:00
Jiong Wang
aa31c464df [AArch64] Fix code formatting in the cpu-table
2015-02-11  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_cpus): Fix code formatting.
2015-02-11 14:35:27 +00:00
Jiong Wang
2abdd192f1 [AArch64] Add support for Cortex-A72
2015-02-04  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_cpus): Add support for Cortex-A72.
	* doc/c-aarch64.texi (-mcpu=): Add "cortex-a72".
2015-02-04 19:17:12 +00:00
Alan Modra
b90efa5b79 ChangeLog rotatation and copyright year update 2015-01-02 00:53:45 +10:30
Richard Earnshaw
5c47e52589 [AArch64] Fix mis-detection of unpredictable load/store operations with FP regs.
* config/tc-aarch64.c (warn_unpredictable_ldst): Check that transfer
	registers are in the GP register set.  Adjust warnings.  Use correct
	field member for address register.
	* testsuite/gas/aarch64/diagnostic.l: Update.
2014-11-20 15:28:52 +00:00
Jiong Wang
54a28c4ce5 [AArch64] Warn on load pair to same register
2014-11-19  Ryan Mansfield  <rmansfield@qnx.com>

    * config/tc-aarch64.c (md_assemble): Call warn_unpredictable_ldst.
    (warn_unpredictable_ldst): New.

  2014-11-19  Ryan Mansfield <rmansfield@qnx.com>

    * gas/aarch64/diagnostic.s: Add new warnings test patterns.
    * gas/aarch64/diagnostic.l: Update expected diagnostic output.
2014-11-19 09:35:23 +00:00
Jan Beulich
ae527cd876 aarch64: allow adding/removing just feature flags via .arch_extension
Rather than requiring to always also set/change the base architecture,
allow just en-/disabling of architecture extensions, matching what ARM
has.
2014-11-18 14:08:28 +01:00
Philipp Tomsich
0a9ce86daf [AArch64] Add xgene2. 2014-11-18 11:24:14 +00:00
Philipp Tomsich
070cb95614 [AArch64] Add xgene1.
The name xgene1 superceeds xgene-1.  We retain support for the
original xgene-1 for compatibility but drop it from documentation.
2014-11-18 11:19:05 +00:00
Marcus Shawcroft
02c1355124 [AArch64] Enable CRC feature in GAS for cortex-a53 and cortex-a57. 2014-11-14 12:52:17 +00:00
Marcus Shawcroft
09bc6c7224 [AArch64] Remove example processors from GAS. 2014-11-13 16:42:23 +00:00
Dr Philipp Tomsich
f803aa8ead Remove the artificial limit on code alignment through the use of the
fixed part of a fragment for output generation only, which required
MAX_MEM_FOR_RS_ALIGN_CODE to be large enough to hold the maximum pad.

	* config/tc-aarch64.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define to 7.
	* config/tc-aarch64.c (aarch64_handle_align): Rewrite to handle
	large alignments with a constant fragment size of
	MAX_MEM_FOR_RS_ALIGN_CODE.
2014-10-30 10:53:09 +00:00
Andrew Pinski
55fbd9927b [AARCH64] Add thunderx support to gas
This patch adds -mcpu=thunderx support to gas.

OK? Tested with no regressions.

ChangeLog:
	* config/tc-aarch64.c (aarch64_cpus):
	Add thunderx.
	* doc/c-aarch64.texi: Document that thunderx
	is a valid processor name.
2014-10-21 10:51:01 -07:00
Jan Beulich
28f013d5cb aarch64: move bogus assertion
Asserting "idx" to be non-negative when subsequent code handles this
case is bogus. In fact the assertion triggers e.g. when mistakenly
using the arm32 comment character @ following an instruction.

While doing this I also noticed that despite there being local
variables "detail" and "idx", not all places where they could be used
did actually make use of them, so this is being adjusted at once.

Finally, for the code to be slightly more robust, also change
comparisons against -1 to such checking for a (non-)negative value.
2014-10-21 09:53:25 +02:00
Jiong Wang
df7b4545b2 [PATCH/AArch64] Generic support for all system registers using mrs and msr
2014-09-03  Jiong Wang  <jiong.wang@arm.com>

  opcode/
    * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
    * aarch64-dis-2.c: Update auto-generated file.

  gas/
    * config/tc-aarch64.c (parse_sys_reg): Remove the restriction on op0 field.

  gas/testsuite/
    * gas/aarch64/illegal.s: Update testcase.
    * gas/aarch64/illegal.d: Likewise.
    * gas/aarch64/sysreg-1.s: Likewise.
    * gas/aarch64/sysreg-1.d: Likewise.
2014-09-03 14:53:53 +01:00
Jiong Wang
ee804238f0 [PATCH/AArch64] Implement LSE feature
2014-09-03  Jiong Wang  <jiong.wang@arm.com>

  gas/
	* config/tc-aarch64.c (parse_operands): Recognize PAIRREG.
	(aarch64_features): Add entry for lse extension.

  include/opcode/
	* aarch64.h (AARCH64_FEATURE_LSE): New feature added.
	(aarch64_opnd): Add AARCH64_OPND_PAIRREG.
	(aarch64_insn_class): Add lse_atomic.
	(F_LSE_SZ): New field added.
	(opcode_has_special_coder): Recognize F_LSE_SZ.

  opcode/
	* aarch64-tbl.h (QL_R4NIL): New qualifiers.
	(aarch64_feature_lse): New feature added.
	(LSE): New Added.
	(aarch64_opcode_table): New LSE instructions added.  Improve
	descriptions for ldarb/ldarh/ldar.
	(aarch64_opcode_table): Describe PAIRREG.
	* aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
	* aarch64-opc.c (fields): Add entry for F_LSE_SZ.
	(aarch64_print_operand): Recognize PAIRREG.
	(operand_general_constraint_met_p): Check reg pair constraints for CASP
	instructions.
	* aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
	(do_special_decoding): Recognize F_LSE_SZ.
	* aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.

  gas/testsuite/
	* gas/aarch64/lse-atomic.d: New.
	* gas/aarch64/lse-atomic.s: Likewise.
	* gas/aarch64/illegal-lse.d: Likewise.
	* gas/aarch64/illegal-lse.l: Likewise.
	* gas/aarch64/illegal-lse.s: Likewise.
	* gas/aarch64/diagnostic.s: Check processor feature detect for lse
	instruction.
	* gas/aarch64/diagnostic.l: Likewise.
2014-09-03 14:53:53 +01:00
Richard Henderson
a2cac51cb0 aarch64: Fix CFA encoding of vector registers
* config/tc-aarch64.c (tc_aarch64_regname_to_dw2regnum): Fix
	register number for vector register types.
2014-08-22 14:41:43 -07:00
Alan Modra
e57e6ddc2e Prepare gas for 64-bit obstacks
Use size_t in a few places involved with obstacks, and don't include
obstack.h in files that don't use obstacks.

gas/
	* config/bfin-parse.y: Don't include obstack.h.
	* config/obj-aout.c: Likewise.
	* config/obj-coff.c: Likewise.
	* config/obj-som.c: Likewise.
	* config/tc-bfin.c: Likewise.
	* config/tc-i960.c: Likewise.
	* config/tc-rl78.c: Likewise.
	* config/tc-rx.c: Likewise.
	* config/tc-tic4x.c: Likewise.
	* expr.c: Likewise.
	* listing.c: Likewise.
	* config/obj-elf.c (elf_file_symbol): Make name_length a size_t.
	* config/tc-aarch64.c (symbol_locate): Likewise.
	* config/tc-arm.c (symbol_locate): Likewise.
	* config/tc-mmix.c (mmix_handle_mmixal): Make len_0 a size_t.
	* config/tc-score.c (s3_build_score_ops_hsh): Make len a size_t.
	(s3_build_dependency_insn_hsh): Likewise.
	* config/tc-score7.c (s7_build_score_ops_hsh): Likewise.
	(s7_build_dependency_insn_hsh): Likewise.
	* frags.c (frag_grow): Make parameter a size_t, and use size_t locals.
	(frag_new): Make parameter a size_t.
	(frag_var_init): Make max_chars and var parameters size_t.
	(frag_var, frag_variant): Likewise.
	(frag_room): Return a size_t.
	(frag_align_pattern): Make n_fill parameter a size_t.
	* frags.h: Update function prototypes.
	* symbols.c (save_symbol_name): Make name_length a size_t.
2014-07-26 21:00:50 +09:30
Nick Clifton
b97e87cc01 Fixes a problem exposed by the aarcg64/illegal.s test case - where the assembler was
generating too many error messages.

	* config/tc-aarch64.c (md_apply_fix): Ignore unused relocs.
2014-06-16 17:40:02 +01:00
Jiong Wang
f4c51f600e This fixes the aarch64 assembler so that it will generate error messages when
a syntax error is detected in an optional operand.

  * config/tc-aarch64.c (END_OF_INSN): New macro.
  (parse_operands): Handle operand given and be in wrong
  format when operand is optional.

  * gas/aarch64/diagnostic.s: New test patterns.
  * gas/aarch64/diagnostic.l: Likewise.
2014-06-16 17:22:19 +01:00
Yufeng Zhang
a52e6fd34a Enable verbose error messages by default for AArch64 gas.
gas/

	* config/tc-aarch64.c (aarch64_opts): Add new option
	"mno-verbose-error".
	(verbose_error_p): Initialize to 1.
	* doc/c-aarch64.texi (AArch64 Options): Document -mverbose-error
	and -mno-verbose-error.

gas/testsuite/

	* gas/aarch64/illegal.d: Pass -mno-verbose-error.
	* gas/aarch64/verbose-error.s: Add more verbose message testcases.
	* gas/aarch64/verbose-error.l: Ditto.
2014-03-18 17:41:43 +00:00
Nick Clifton
55d9b4c146 The value of a bignum expression is held in a single global array. This means
that if multiple bignum values are encountered only the most recent is valid.
If such expressions are cached, eg to be emitted into a literal pool later on
in the assembly, then only one expression - the last - will be correct.  This
patch fixes the problem for the AArch64 target by caching each bignum value
locally.

	PR gas/16688
	* config/tc-aarch64.c (literal_expression): New structure.
	(literal_pool): Replace exp array with literal_expression array.
	(add_to_lit_pool): When adding a bignum cache the big value.
	(s_ltorg): When emitting a bignum initialise the global bignum
	array from the cached value.

	* gas/aarch64/litpool.s: New test case.
	* gas/aarch64/litpool.d: Expected disassembly.
2014-03-12 15:50:49 +00:00
Alan Modra
4b95cf5c0c Update copyright years 2014-03-05 22:16:15 +10:30
Philipp Tomsich
9877c63c84 [AArch64] Add GAS recognition for "xgene-1"
* config/tc-aarch64.c (aarch64_cpus): Add entry for "xgene-1"

This adds support for the AppliedMicro X-Gene 1 processor to the
assembler.
2014-01-07 12:27:24 +00:00
Yufeng Zhang
3f06bfce70 gas/
* config/tc-aarch64.c (md_assemble): Defer the feature checking until
	do_encode () succeeds.

gas/testsuite/

	* gas/aarch64/rm-simd-ext.d: New file.
	* gas/aarch64/rm-simd-ext.l: Likewise.
	* gas/aarch64/rm-simd-ext.s: Likewise.
2013-12-18 19:15:57 +00:00
Yufeng Zhang
9a73e520da Revert "Do not issue error messages when parsing a PSTATE register".
This reverts commit 03e621be97.
2013-11-20 11:22:53 +00:00
Nick Clifton
03e621be97 * config/tc-aarch64.c (parse_sys_reg): Do not issue error messages
for deprecated system registers when parsing pstate fields.
2013-11-19 17:40:31 +00:00
Yufeng Zhang
18cf6de400 gas/
* config/tc-aarch64.c (parse_sys_reg): Support
	S2_<op1>_<Cn>_<Cm>_<op2>.

gas/testsuite/

	* gas/testsuite/sysreg.s: Add test.
	* gas/testsuite/sysreg.d: Update.
2013-11-18 11:42:42 +00:00
Yufeng Zhang
a203d9b72f Revert "Add support for AArch64 trace unit registers."
This reverts commit 75468c93c1.
2013-11-18 11:42:41 +00:00
Yufeng Zhang
75468c93c1 gas/
* config/tc-aarch64.c (set_other_error): New function.
	(parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set
	the variable to which it points with 'o'.
	(parse_operands): Update; check for write to read-only system
	registers or read from write-only ones.

gas/testsuite/

	* gas/aarch64/diagnostic.s: Add tests.
	* gas/aarch64/diagnostic.l: Update.
	* gas/aarch64/tracereg-illegal.d: New file.
	* gas/aarch64/tracereg-illegal.l: Ditto.
	* gas/aarch64/tracereg-illegal.s: Ditto.
	* gas/aarch64/tracereg.d: Ditto.
	* gas/aarch64/tracereg.s: Ditto.

include/opcode

	* aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
	(aarch64_sys_reg_writeonly_p): Ditto.

opcodes/

	* aarch64-opc.c (CPENT): New define.
	(F_READONLY, F_WRITEONLY): Likewise.
	(aarch64_sys_regs): Add trace unit registers.
	(aarch64_sys_reg_readonly_p): New function.
	(aarch64_sys_reg_writeonly_p): Ditto.
2013-11-15 23:40:34 +00:00
Yufeng Zhang
49eec19300 gas/
* config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg;
	call aarch64_sys_reg_deprecated_p and warn about the deprecated
	system registers.

gas/testsuite/

	* gas/aarch64/deprecated.d: New file.
	* gas/aarch64/deprecated.l: New file.
	* gas/aarch64/deprecated.s: New file.
	* gas/aarch64/sysreg-1.s: Add tests.
	* gas/aarch64/sysreg-1.d: Add tests.

include/opcode/

	* aarch64.h (aarch64_sys_reg): New typedef.
	(aarch64_sys_regs): Change to define with the new type.
	(aarch64_sys_reg_deprecated_p): Declare.

opcodes/

	* aarch64-opc.c (F_DEPRECATED): New macro.
	(aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
	F_DEPRECATED.
	(aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
	AARCH64_OPND_SYSREG.
2013-11-05 20:54:22 +00:00
Yufeng Zhang
68a6428382 gas/
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1.

gas/testsuite/

	* gas/aarch64/alias.s: Add tests.
	* gas/aarch64/alias.d: Update.
	* gas/aarch64/no-aliases.d: Update.
	* gas/aarch64/diagnostic.s: Add tests.
	* gas/aarch64/diagnostic.l: Update.
	* gas/aarch64/illegal.s: Add tests.
	* gas/aarch64/illegal.l: Update.

include/opcode/

	* aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
	(enum aarch64_opnd): Add AARCH64_OPND_COND1.

opcodes/

	* aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
	(convert_from_csel): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Handle
	AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
	(aarch64_print_operand): Handle AARCH64_OPND_COND1.
	* aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
	COND for cinc, cset, cinv, csetm and cneg.
	(AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
	* aarch64-asm-2.c: Re-generated.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.
2013-11-05 20:50:18 +00:00
Will Newton
8db49cc2de config/tc-aarch64.c: Avoid trying to parse a vector mov as immediate.
Parsing a vector mov instruction currently leads to a phantom undefined
symbol being added to the symbol table. e.g.:

       .text
       mov     x0, v0.D[0]

Produces an undefined symbol called "v0.D".

gas/ChangeLog:

2013-11-05  Will Newton  <will.newton@linaro.org>

	PR gas/16103
	* config/tc-aarch64.c (parse_operands): Avoid trying to
	parse a vector register as an immediate.

gas/testsuite/ChangeLog:

2013-11-05  Will Newton  <will.newton@linaro.org>

	* gas/aarch64/advsimd-mov-bad.d: New file.
	* gas/aarch64/advsimd-mov-bad.s: Likewise.
2013-11-05 14:28:30 +00:00
Yufeng Zhang
69091a2cc4 [AArch64, ILP32] Retire -milp32 and -mlp64; use -mabi=ilp32 and -mabi=lp64.
gas/

	* config/tc-aarch64.c (enum aarch64_abi_type): New enumeration tag.
	(AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators.
	(aarch64_abi): New variable.
	(ilp32_p): Change to be a macro.
	(aarch64_opts): Remove the support for option -milp32 and -mlp64.
	(struct aarch64_option_abi_value_table): New struct.
	(aarch64_abis): New table.
	(aarch64_parse_abi): New function.
	(aarch64_long_opts): Add entry for -mabi=.
	* doc/as.texinfo (Target AArch64 options): Document -mabi.
	* doc/c-aarch64.texi: Likewise.

gas/testsuite/

	* gas/aarch64/ilp32-basic.d (#as): Update to use -mabi=ilp32
2013-07-19 16:25:54 +00:00
Marcus Shawcroft
4aa2c5e2cb [PATCH, COMMITTED] [AArch64] Replace the :got_prel19: address modifier with :got: 2013-07-03 17:26:36 +00:00
Marcus Shawcroft
2c0a3565e5 [AArch64] Tidy up switch statement in GAS. 2013-07-03 17:25:17 +00:00
Yufeng Zhang
a6bb11b2df [AArch64, ILP32] 3/6 Support for ELF32 relocs and refactor reloc handling
bfd/

	* bfd-in2.h: Re-generated.
	* elfnn-aarch64.c (HOWTO64, HOWTO32): New define.
	(IS_AARCH64_TLS_RELOC): Change to be based on the
	bfd reloc enumerators.
	(IS_AARCH64_TLSDESC_RELOC): Likewise.
	(PG, PG_OFFSET): Cast literal to bfd_vma.
	(elf64_aarch64_howto_table): Removed.
	(elf64_aarch64_howto_dynrelocs): Removed.
	(elf64_aarch64_tls_howto_table): Removed.
	(elf64_aarch64_tlsdesc_howto_table): Removed.
	(elfNN_aarch64_howto_table): New table to host all howto entires..
	(R_AARCH64_*): Replaced by AARCH64_R (*) and AARCH64_R_STR (*).
	(elfNN_aarch64_bfd_reloc_from_howto): New function.
	(elfNN_aarch64_bfd_reloc_from_type): Ditto.
	(struct elf_aarch64_reloc_map): New.
	(elf_aarch64_reloc_map): New table.
	(elfNN_aarch64_howto_from_bfd_reloc): New function.
	(elfNN_aarch64_howto_from_type): Update to look up the new table
	elfNN_aarch64_howto_table.
	(struct elf64_aarch64_reloc_map): Remove.
	(elf64_aarch64_reloc_map): Remove.
	(elfNN_aarch64_reloc_type_lookup): Change to call
	elfNN_aarch64_howto_from_bfd_reloc.
	(elfNN_aarch64_reloc_name_lookup): Change to look up the new table
	elfNN_aarch64_howto_table.
	(aarch64_resolve_relocation): Refactor to switch on the bfd
	reloc enumerators.
	(bfd_elf_aarch64_put_addend): Likewise.
	(elfNN_aarch64_final_link_relocate): Likewise.
	(aarch64_tls_transition_without_check): Likewise.
	(aarch64_reloc_got_type): Likewise.
	(aarch64_can_relax_tls): Likewise.
	(aarch64_tls_transition): Likewise.
	(elfNN_aarch64_tls_relax): Likewise.
	(elfNN_aarch64_final_link_relocate): Likewise.
	(elfNN_aarch64_relocate_section): Likewise.
	(elfNN_aarch64_gc_sweep_hook): Likewise.
	(elfNN_aarch64_check_relocs): Likewise.
	(aarch64_tls_transition): Change to return a bfd reloc enumerator.
	* libbfd.h: Re-generated.
	* reloc.c: Re-order the AArch64 bfd reloc enumerators.
	(BFD_RELOC_AARCH64_RELOC_START)
	(BFD_RELOC_AARCH64_RELOC_END)
	(BFD_RELOC_AARCH64_LD_GOT_LO12_NC)
	(BFD_RELOC_AARCH64_LD32_GOT_LO12_NC)
	(BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC)
	(BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC)
	(BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC)
	(BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC)
	(BFD_RELOC_AARCH64_IRELATIVE): New relocs.

gas/

	* config/tc-aarch64.c (reloc_table): Replace
	BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with
	BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to
	BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and
	BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC.
	(md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
	BFD_RELOC_AARCH64_LD32_GOT_LO12_NC,
	BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
	BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC,
	BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and
	BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC.
	(aarch64_force_relocation): Likewise.

gas/testsuite/

	* gas/aarch64/ilp32-basic.d: New file.
	* gas/aarch64/ilp32-basic.s: New file.

include/elf/

	* aarch64.h: Add ELF32 reloc codes and remove fake ELF64 ones.
	(R_AARCH64_IRELATIVE): New reloc.
2013-06-26 10:47:06 +00:00
Yufeng Zhang
cec5225bd8 [AArch64, ILP32] 2/6 Parametrize elfnn-aarch64.c and add basic support in ld
and gas.

bfd/

	* Makefile.am (BFD64_BACKENDS): Add elf32-aarch64.lo.
	(BUILD_CFILES): Add elf32-aarch64.c.
	(elf32-aarch64.c): New rule for generating from elfnn-aarch64.c.
	* Makefile.in: Re-generated.
	* archures.c (bfd_mach_aarch64_ilp32): New define.
	* bfd-in.h (bfd_elf32_aarch64_init_maps): New declaration.
	(bfd_elf32_aarch64_set_options): Ditto.
	(elf32_aarch64_setup_section_lists): Ditto.
	(elf32_aarch64_next_input_section): Ditto.
	(elf32_aarch64_size_stubs): Ditto.
	(elf32_aarch64_build_stubs): Ditto.
	* bfd-in2.h: Re-generated.
	* config.bfd (aarch64-*-elf): Add bfd_elf32_littleaarch64_vec
	and bfd_elf32_bigaarch64_vec.
	(aarch64-*-linux*): Likewise.
	(aarch64_be-*-elf): Likewise.
	(aarch64_be-*-linux*): Likewise.
	* configure.in (bfd_elf32_bigaarch64_vec)
	(bfd_elf32_littleaarch64_vec): New.
	* configure: Re-generated.
	* cpu-aarch64.c (compatible): Don't allow mixing ilp32 objects with
	lp64 ones.
	(bfd_aarch64_arch_ilp32): New.
	(bfd_aarch64_arch): Link to bfd_aarch64_arch_ilp32.
	* elfnn-aarch64.c (ARCH_SIZE): New define.
	(AARCH64_R, AARCH64_R_STR, LOG_FILE_ALIGN): New defines.
	(GOT_ENTRY_SIZE): Re-define as (ARCH_SIZE / 8).
	(elf64_aarch64_*): Rename to elfNN_aarch64_*.
	(ELF64_R_*): Rename to ELFNN_R_*.
	Plus other paramaterization.
	* targets.c (bfd_elf32_bigaarch64_vec, bfd_elf32_littleaarch64_vec):
	New declarations.
	(_bfd_target_vector): Add bfd_elf32_bigaarch64_vec and
	bfd_elf32_littleaarch64_vec.

gas/

	* config/tc-aarch64.c (ilp32_p): New static variable.
	(elf64_aarch64_target_format): Return the target according to the
	value of 'ilp32_p'.
	(md_begin): Determine 'mach' according to the value of 'ilp32_p'.
	(aarch64_opts): Add support for options '-milp32' and '-mlp64'.
	(aarch64_dwarf2_addr_size): New function.
	* config/tc-aarch64.h (aarch64_dwarf2_addr_size): New declaration.
	(DWARF2_ADDR_SIZE): New define.

ld/

	* Makefile.am (ALL_64_EMULATION_SOURCES): Add eaarch64elf32.c.
	(eaarch64elf32.c): New dependency and rule.
	* Makefile.in: Re-generated.
	* configure.tgt (aarch64-*-elf): Add aarch64elf32.
	(aarch64_be-*-elf, aarch64_be-*-linux*, aarch64-*-linux*): Likewise.
	* emulparams/aarch64elf32.sh: New file.
2013-06-26 10:41:42 +00:00
Yufeng Zhang
418009c200 Correct the relocation names for R_AARCH64_TLSDESC_LD_PREL19 and R_AARCH64_TLSDESC_ADR_PAGE21. 2013-05-28 16:39:51 +00:00
Marcus Shawcroft
89d2a2a39e [AArch64] Range check only resolved relocations.
2013-05-28  Marcus Shawcroft  <marcus.shawcroft@arm.com>

        * config/tc-aarch64.c (md_apply_fix): Move value range checking
        inside fx_done condition.

2013-05-28  Marcus Shawcroft  <marcus.shawcroft@arm.com>

        * gas/aarch64/adr_1.d: New file.
        * gas/aarch64/adr_1.s: New file.
        * gas/aarch64/b_1.d: New file.
        * gas/aarch64/b_1.s: New file.
        * gas/aarch64/beq_1.d: New file.
        * gas/aarch64/beq_1.s: New file.
        * gas/aarch64/ldr_1.d: New file.
        * gas/aarch64/ldr_1.s: New file.
        * gas/aarch64/tbz_1.d: New file.
        * gas/aarch64/tbz_1.s: New file.
2013-05-28 09:43:42 +00:00
Yufeng Zhang
62b0d0d5f3 Add to the AArch64 GAS the missing support for hexadecimal-format
floating-point literal in the FMOV instruction.

gas/

	* config/tc-aarch64.c (aarch64_imm_float_p): Rename 'e' to 'pattern';
	add comment.
	(aarch64_double_precision_fmovable): New function.
	(parse_aarch64_imm_float): Add parameter 'dp_p'; call the new
	function; handle hexadecimal representation of IEEE754 encoding.
	(parse_operands): Update the call to parse_aarch64_imm_float.

gas/testsuite/

	* gas/aarch64/diagnostic.s: Add test.
	* gas/aarch64/diagnostic.l: Update.
	* gas/aarch64/illegal.s: Add test.
	* gas/aarch64/illegal.l: Update.
	* gas/aarch64/fpmov.s: New file.
	* gas/aarch64/fpmov.d: New file.
2013-03-05 16:31:44 +00:00
Yufeng Zhang
e60bb1dd35 include/opcode/
* aarch64.h (AARCH64_FEATURE_CRC): New macro.

opcodes/

	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	(aarch64_feature_crc): New static.
	(CRC): New macro.
	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.

gas/

	* config/tc-aarch64.c (aarch64_features): Add the 'crc' option.

gas/testsuite/

	* gas/aarch64/crc32.s: New test.
	* gas/aarch64/crc32.d: Ditto.
2013-02-28 19:18:40 +00:00
Yufeng Zhang
aeebdd9b12 gas/
* config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn
	for system registers.

gas/testsuite/

	* gas/aarch64/illegal.l: Delete the error message for
	msr S3_1_C13_C15_1,x7.
	* gas/aarch64/sysreg.s: Add new tests.
	* gas/aarch64/sysreg.d: Update.
2013-02-28 18:51:05 +00:00
Yufeng Zhang
a1ccaec952 opcodes/
* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	fields to NULL.
	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.

gas/

	* config/tc-aarch64.c (md_begin): Change to check if 'name' is
	NULL.

gas/testsuite/

	* gas/aarch64/system.s: Add tests.
	* gas/aarch64/system.d: Update.
2013-02-14 18:12:51 +00:00