Commit graph

2318 commits

Author SHA1 Message Date
Jose E. Marchesi
3807431192 Support for the sparc %pmcdper privileged register.
opcodes/ChangeLog:

2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-dis.c (print_insn_sparc): Handle the privileged register
	%pmcdper.

gas/ChangeLog:

2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (priv_reg_table): New privileged register
	%pmcdper.

gas/testsuite/ChangeLog:

2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* gas/sparc/wrpr.s: Test writing to the privileged %pmcdper
	register.
	* gas/sparc/wrpr.d: ...and the expected result.
	* gas/sparc/rdpr.s: Test reading from the privileged %pmcdper
	register.
	* gas/sparc/rdpr.d: ...and the expected result.
2015-08-25 17:16:34 +02:00
Jan Stancek
5f40e14d76 Fix the partial disassembly of a broken three byte instruction at the end of a function.
opcodes	* i386-dis.c (print_insn): Fix decoding of three byte operands.

tests	* gas/i386/intel.s: Add test of disassembly of a potential
	three byte instuction at the end of a function.
	* gas/i386/intel.d: Update expected disassembly.
2015-08-24 14:50:15 +01:00
Alexander Fomin
ab4e4ed5da PR binutils/18257: Properly decode x86/Intel mask instructions.
opcodes/

	PR binutils/18257
	* i386-dis.c: Use MOD_TABLE for most of mask instructions.
	(MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1, MOD_VEX_W_1_0F41_P_0_LEN_1,
	MOD_VEX_W_0_0F41_P_2_LEN_1, MOD_VEX_W_1_0F41_P_2_LEN_1,
	MOD_VEX_W_0_0F42_P_0_LEN_1, MOD_VEX_W_1_0F42_P_0_LEN_1,
	MOD_VEX_W_0_0F42_P_2_LEN_1, MOD_VEX_W_1_0F42_P_2_LEN_1,
	MOD_VEX_W_0_0F44_P_0_LEN_1, MOD_VEX_W_1_0F44_P_0_LEN_1,
	MOD_VEX_W_0_0F44_P_2_LEN_1, MOD_VEX_W_1_0F44_P_2_LEN_1,
	MOD_VEX_W_0_0F45_P_0_LEN_1, MOD_VEX_W_1_0F45_P_0_LEN_1,
	MOD_VEX_W_0_0F45_P_2_LEN_1, MOD_VEX_W_1_0F45_P_2_LEN_1,
	MOD_VEX_W_0_0F46_P_0_LEN_1, MOD_VEX_W_1_0F46_P_0_LEN_1,
	MOD_VEX_W_0_0F46_P_2_LEN_1, MOD_VEX_W_1_0F46_P_2_LEN_1,
	MOD_VEX_W_0_0F47_P_0_LEN_1, MOD_VEX_W_1_0F47_P_0_LEN_1,
	MOD_VEX_W_0_0F47_P_2_LEN_1, MOD_VEX_W_1_0F47_P_2_LEN_1,
	MOD_VEX_W_0_0F4A_P_0_LEN_1, MOD_VEX_W_1_0F4A_P_0_LEN_1,
	MOD_VEX_W_0_0F4A_P_2_LEN_1, MOD_VEX_W_1_0F4A_P_2_LEN_1,
	MOD_VEX_W_0_0F4B_P_0_LEN_1, MOD_VEX_W_1_0F4B_P_0_LEN_1,
	MOD_VEX_W_0_0F4B_P_2_LEN_1, MOD_VEX_W_0_0F91_P_0_LEN_0,
	MOD_VEX_W_1_0F91_P_0_LEN_0, MOD_VEX_W_0_0F91_P_2_LEN_0,
	MOD_VEX_W_1_0F91_P_2_LEN_0, MOD_VEX_W_0_0F92_P_0_LEN_0,
	MOD_VEX_W_0_0F92_P_2_LEN_0, MOD_VEX_W_0_0F92_P_3_LEN_0,
	MOD_VEX_W_1_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
	MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_W_0_0F93_P_3_LEN_0,
	MOD_VEX_W_1_0F93_P_3_LEN_0, MOD_VEX_W_0_0F98_P_0_LEN_0,
	MOD_VEX_W_1_0F98_P_0_LEN_0, MOD_VEX_W_0_0F98_P_2_LEN_0,
	MOD_VEX_W_1_0F98_P_2_LEN_0, MOD_VEX_W_0_0F99_P_0_LEN_0,
	MOD_VEX_W_1_0F99_P_0_LEN_0, MOD_VEX_W_0_0F99_P_2_LEN_0,
	MOD_VEX_W_1_0F99_P_2_LEN_0, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
	MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
	MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
	MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
	MOD_VEX_W_1_0F3A33_P_2_LEN_0.
	(vex_w_table): Replace terminals with MOD_TABLE entries for
	most of mask instructions.

gas/testsuite

	PR binutils/18257
	* gas/i386/disassem.s: Add mask instructions with invalid ModR/M byte.
	* gas/i386/x86-64-disassem.s: Likewise.
	* gas/i386/disassem.d: Updated.
	* gas/i386/x86-64-disassem.d: Likewise.
2015-08-21 14:48:05 +03:00
Alan Modra
919b75f7e2 Trailing space in opcodes/ generated files
HJ recently removed trailing space in binutils files, but unfortunately
they return when regenerating files in opcodes.  This fixes the regen
process.

	* cgen.sh: Trim trailing space from cgen output.
	* ia64-gen.c (print_dependency_table): Don't generate trailing space.
	(print_dis_table): Likewise.
	* opc2c.c (dump_lines): Likewise.
	(orig_filename): Warning fix.
	* ia64-asmtab.c: Regenerate.
2015-08-17 12:07:12 +09:30
Andre Vieira
4ab90a7a90 Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp.
opcodes * arm-dis.c (print_insn_arm): Disassembling for all targets V6
	and higher with ARM instruction set will now mark the 26-bit
	versions of teq,tst,cmn and cmp as UNPREDICTABLE.
	(arm_opcodes): Fix for unpredictable nop being recognized as a teq.

test    * gas/arm/nops.d: New.
	* gas/arm/nops.s: New.
	* gas/arm/inst.d: Changed expectation file for 26-bit  teq,
	tst, cmn and cmp.
2015-08-13 11:39:08 +01:00
Simon Dardis
40fc1451c6 [MIPS] Map 'move' to 'or'.
The MIPS assembly idiom 'move' now maps to the 'or' machine instruction. This
change affects microMIPS, MIPS32, MIPS64.

2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>

opcodes/

	* micromips-opc.c (micromips_opcodes): Re-order table so that move
	based on 'or' is first.
	* mips-opc.c (mips_builtin_opcodes): Ditto.

bfd/

	* elfxx-mips.c (STUB_MOVE): Change to use 'or' only.
	(mips_o32_exec_plt0_entry, mips_n32_exec_plt0_entry,
	mips_n64_exec_plt0_entry, micromips_insn32_o32_exec_plt0_entry):
	Update to use 'or' instead of 'addu/daddu'.
	(_bfd_mips_elf_finish_dynamic_symbol): Update usage of STUB_MOVE.
	(move_insns_32): Reorder table.

gas/

	* config/tc-mips.c (move_register): Change to use 'or' only.
	(s_cpload, s_cpsetup, s_cprestore, s_cpreturn): Update to
	use or for move.

gas/testsuite/

	* gas/mips/elf-rel23.d: Update test.
	* gas/mips/elf-rel23.d: Ditto.
	* gas/mips/elf-rel23a.d: Ditto.
	* gas/mips/elf-rel23b.d: Ditto.
	* gas/mips/elf_e_flags1.d: Ditto.
	* gas/mips/elf_e_flags2.d: Ditto.
	* gas/mips/elf_e_flags3.d: Ditto.
	* gas/mips/elf_e_flags4.d: Ditto.
	* gas/mips/loc-swap-dis.d: Ditto.
	* gas/mips/micromips-insn32.d: Ditto.
	* gas/mips/micromips-noinsn32.d: Ditto.
	* gas/mips/micromips-trap.d: Ditto.
	* gas/mips/micromips.d: Ditto.
	* gas/mips/mips-abi32-pic.d: Ditto.
	* gas/mips/mips-abi32.d: Ditto.
	* gas/mips/mips-gp32-fp32-pic.d: Ditto.
	* gas/mips/mips-gp32-fp32.d: Ditto.
	* gas/mips/mips-gp32-fp64-pic.d: Ditto.
	* gas/mips/mips-gp32-fp64.d: Ditto.
	* gas/mips/mips-gp64-fp32-pic.d: Ditto.
	* gas/mips/mips-gp64-fp32.d: Ditto.
	* gas/mips/mips-gp64-fp64-pic.d: Ditto.
	* gas/mips/mips-gp64-fp64.d: Ditto.
	* gas/mips/mipsr6@loc-swap-dis.d: Ditto.
	* gas/mips/tls-o32.d: Ditto.
	* gas/mips/uld2-eb.d: Ditto.
	* gas/mips/uld2-el.d: Ditto.
	* gas/mips/ulw2-eb-ilocks.d: Ditto.
	* gas/mips/ulw2-eb.d: Ditto.
	* gas/mips/ulw2-el-ilocks.d: Ditto.
	* gas/mips/ulw2-el.d: Ditto.
	* gas/mips/move.d: New test.
	* gas/mips/move.s: Ditto.
	* gas/mips/micromips32-move.d: Ditto.
	* gas/mips/micromips32-move.s: Ditto.
	* gas/mips/mips.exp: Run the new tests.

gold/

	* mips.cc (plt0_entry_o32, plt0_entry_n32, plt0_entry_n64,
	lazy_stub_normal_1, lazy_stub_normal_1_n64,
	lazy_stub_normal_2, lazy_stub_normal_2_n64, lazy_stub_big,
	lazy_stub_big_n64, lazy_stub_micromips32_normal_1_n64,
	lazy_stub_micromips32_normal_2_n64, lazy_stub_micromips32_big,
	lazy_stub_micromips32_big_n64): Update to use 'or' for move instead
	of 'addu/daddu'.

ld/testsuite/

	* ld-mips-elf/compressed-plt-1-n32-mips16.od: Update test.
	* ld-mips-elf/compressed-plt-1-n32-umips.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-mips16-got.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-mips16-only.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-mips16-word.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-mips16.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-se.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-umips-got.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-umips-word.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-umips.od: Ditto.
	* ld-mips-elf/jalx-2.dd: Ditto.
	* ld-mips-elf/mips16-pic-3.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-3a.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-3b.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-5b.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-6-n32.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-6-o32.dd: Ditto.
	* ld-mips-elf/stub-dynsym-1-10000.d: Ditto.
	* ld-mips-elf/stub-dynsym-1-2fe80.d: Ditto.
	* ld-mips-elf/stub-dynsym-1-7fff.d: Ditto.
	* ld-mips-elf/stub-dynsym-1-8000.d: Ditto.
	* ld-mips-elf/stub-dynsym-1-fff0.d: Ditto.
	* ld-mips-elf/tlsbin-o32.d: Ditto.
	* ld-mips-elf/tlsdyn-o32-1.d: Ditto.
	* ld-mips-elf/tlsdyn-o32-2.d: Ditto.
	* ld-mips-elf/tlsdyn-o32-3.d: Ditto.
	* ld-mips-elf/tlsdyn-o32.d: Ditto.
	* ld-mips-elf/tlslib-o32.d: Ditto.
2015-08-12 17:10:22 +01:00
H.J. Lu
43e65147c0 Remove trailing spaces in opcodes 2015-08-12 04:45:07 -07:00
Nick Clifton
922c5db5e7 Fix the disassembly of the AArch64 SIMD EXT instruction.
PR 18800
	* aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
	instruction.
2015-08-11 18:00:36 +01:00
Robert Suchanek
75fb7498c2 Add SIGRIE instruction for MIPS R6
opcodes/

	* mips-opc.c (mips_builtin_opcodes): Add "sigrie".

gas/testsuite/

	* gas/mips/r6.s: Add tests for "sigrie".
	* gas/mips/r6.d: Check for "sigrie".
	* gas/mips/r6-n32.d: Likewise.
	* gas/mips/r6-n64.d: Likewise.
2015-08-10 09:14:07 +01:00
Amit Pawar
36aed29d37 Remove CpuFMA4 support from CPU_ZNVER1_FLAGS.
opcodes/

	* i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
	* i386-init.h: Regenerated.
2015-08-07 07:31:51 -07:00
H.J. Lu
a8484f9612 Properly disassemble movnti in Intel mode
gas/testsuite/

	PR binutils/13571
	* gas/i386/i386.exp: Run i386-intel and x86_64-intel.
	* gas/i386/i386-intel.d: New file.
	* gas/i386/x86_64-intel.d: Likewise.

opcodes/

	PR binutils/13571
	* i386-dis.c (MOD_0FC3): New.
	(PREFIX_0FC3): Renamed to ...
	(PREFIX_MOD_0_0FC3): This.
	(dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
	(prefix_table): Replace Ma with Ev on movntiS.
	(mod_table): Add MOD_0FC3.
2015-07-30 04:17:02 -07:00
H.J. Lu
37a42ee9ad Regenerate configure files
bfd/

	* configure: Regenerated.

binutils/

	* configure: Regenerated.

gas/

	* configure: Regenerated.

gold/

	* configure: Regenerated.

gprof/

	* configure: Regenerated.

ld/

	* configure: Regenerated.

opcodes/

	* configure: Regenerated.
2015-07-27 07:56:32 -07:00
Alan Modra
070fe95d07 Fix ubsan signed integer overflow
IMO a fairly useless warning in this case, but technically correct.

	PR 18708
	* i386-dis.c (get64): Avoid signed integer overflow.
2015-07-23 12:52:46 +09:30
H.J. Lu
20c2a61587 Fix memory operand size for vcvtt?ps2u?qq instructions
When disassembling AVX512 vcvtt?ps2u?q instructions with data
broadcasting enabled, memory operand size should be DWORD.

gas/testsuite/

	PR binutils/18631
	* gas/i386avx512dq-intel.d: Replace "QWORD" with "DWORD" in
	vcvtt?ps2u?qq instructions disassembly regexes.
	Add disassembly regex for new test.
	* gas/i386/avx512dq.d: Likewise.
	* gas/i386/avx512dq_vl-intel.d: Likewise.
	* gas/i386/avx512dq_vl.d: Likewise.
	* gas/i386/x86-64-avx512dq-intel.d: Likewise.
	* gas/i386/x86-64-avx512dq.d: Likewise.
	* gas/i386/x86-64-avx512dq_vl-intel.d: Likewise.
	* gas/i386/x86-64-avx512dq_vl.d: Likewise.
	* gas/i386/avx512dq.s: Add new test for Intel syntax with memory
	operand and broadcasting enabled.
	* gas/i386/avx512dq_vl.s: Likewise.
	* gas/i386/x86-64-avx512dq.s: Likewise.
	* gas/i386/x86-64-avx512dq_vl.s: Likewise.

opcodes/

	PR binutils/18631
	* i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
	"EXEvexHalfBcstXmmq" for the second operand.
	(EVEX_W_0F79_P_2): Likewise.
	(EVEX_W_0F7A_P_2): Likewise.
	(EVEX_W_0F7B_P_2): Likewise.
2015-07-22 13:26:21 -07:00
Alessandro Marzocchi
6f1c214259 Updates the ARM disassembler's output of floating point constants to include the actual floating point value.
opcodes	* arm-dis.c (print_insn_coprocessor): Added support for quarter
	float bitfield format.
	(coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
	quarter float bitfield format.

tests	* gas/arm/vfpv3-const-conv.d: Update expected result due to change
	of comment for vmov reg,immediate with VFP coprocessor.
2015-07-16 16:43:16 +01:00
H.J. Lu
8a643cc36c Sync config/warnings.m4 with GCC
config/

	Sync with GCC
	2015-05-27  Jason Merrill  <jason@redhat.com>

	PR bootstrap/66304
	* warnings.m4 (ACX_PROG_CXX_WARNING_OPTS)
	(ACX_PROG_CXX_WARNINGS_ARE_ERRORS)
	(ACX_PROG_CXX_WARNING_ALMOST_PEDANTIC): New.
	(ACX_PROG_CC_WARNING_OPTS, ACX_PROG_CC_WARNING_ALMOST_PEDANTIC)
	(ACX_PROG_CC_WARNINGS_ARE_ERRORS): Push into C language context.

libdecnumber/

	* configure: Regenerated.

libiberty/

	* configure: Regenerated.

opcodes/

	* configure: Regenerated.
2015-07-14 08:39:12 -07:00
Alan Modra
40f77f827b Add missing changelog entries 2015-07-10 20:08:55 +09:30
Alan Modra
ef5a96d564 Remove ppc860, ppc750cl, ppc7450 insns from common ppc.
Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations.  I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8.  This
patch fixes that problem.

Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code.  ie. you might need to modify
makefiles to pass -m860 to gas.

include/opcode/
	* ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
opcodes/
	* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
	* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
	PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
gas/
	* config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
	* doc/c-ppc.texi (PowerPC-Opts): Likewise.
gas/testsuite/
	* gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
2015-07-03 10:57:14 +09:30
Sandra Loosemore
c8c8175b62 Opcodes and assembler support for Nios II R2
2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
	    Cesar Philippidis  <cesar@codesourcery.com>

	gas/
	* config/tc-nios2.c (nios2_min_align): New.
	(nop): Replace with....
	(nop_r1, nop_r2, nop_r2_cdx, nop32, nop16): New.
	(nios2_align): Handle alignment on 2-byte boundaries when CDX
	instructions may be present.
	(s_nios2_align): Adjust reference to nop.
	(CDXBRANCH, IS_CDXBRANCH): New.
	(CDX_UBRANCH_SUBTYPE, CDX_CBRANCH_SUBTYPE): New.
	(nios2_relax_subtype_size): Handle 2-byte CDX branches.
	(nios2_relax_frag): Likewise.
	(md_convert_frag): Handle R2 encodings.
	(nios2_check_overflow): Check that low-order bits are zero
	before applying rightshift from howto.
	(nios2_check_overflow): Correct negative overflow calculation.
	(nios2_diagnose_overflow): Handle signed_immed12_overflow.  Issue
	generic overflow messages for miscellaneous instruction formats.
	(md_apply_fix): Recognize new R2 relocations.  For pc_relative
	relocations, store fixup in *valP.
	(nios2_reglist_mask, nios2_reglist_dir): New.
	(nios2_parse_reglist): New.
	(nios2_parse_base_register): New.
	(nios2_assemble_expression): Handle constant expressions designated
	by BFD_RELOC_NONE.
	(nios2_assemble_reg3): New.
	(nios2_assemble_arg_c): Handle R2 instruction formats.
	(nios2_assemble_arg_d): Likewise.
	(nios2_assemble_arg_s): Likewise.
	(nios2_assemble_arg_t): Likewise.
	(nios2_assemble_arg_D): New.
	(nios2_assemble_arg_S): New.
	(nios2_assemble_arg_T): New.
	(nios2_assemble_arg_i): Handle R2 instruction formats.
	(nios2_assemble_arg_I): New.
	(nios2_assemble_arg_u): Handle R2 instruction formats.
	(nios2_assemble_arg_U): New.
	(nios2_assemble_arg_V): New.
	(nios2_assemble_arg_W): New.
	(nios2_assemble_arg_X): New.
	(nios2_assemble_arg_Y): New.
	(nios2_assemble_arg_o): Handle R2 instruction formats.
	(nios2_assemble_arg_O): New.
	(nios2_assemble_arg_P): New.
	(nios2_assemble_arg_j): Handle R2 instruction formats.
	(nios2_assemble_arg_k): New.
	(nios2_assemble_arg_l): Handle R2 instruction formats.
	(nios2_assemble_arg_m): Likewise.
	(nios2_assemble_arg_M): New.
	(nios2_assemble_arg_N): New.
	(nios2_assemble_arg_e): New.
	(nios2_assemble_arg_f): New.
	(nios2_assemble_arg_g): New.
	(nios2_assemble_arg_h): New.
	(nios2_assemble_arg_R): New.
	(nios2_assemble_arg_B): New.
	(nios2_assemble_args): Handle new argument letters.
	(nios2_consume_arg): Likewise.
	(nios2_translate_pseudo_insn): Avoid dereferencing null pointer
	in error message.
	(nios2_ps_insn_info_structs): Add nop.n.
	(output_ubranch): Handle CDX branches.
	(output_cbranch): Likewise.
	(output_call): Handle R2 encodings.
	(output_movia): Likewise.
	(md_begin): Initialize nios2_min_align.
	(md_assemble): Align to nios2_min_align.  Adjust nios2_min_align
	if a 16-bit instruction is seen.
	(nios2_cons_align): Use appropriate nop pattern.

	include/opcode/
	* nios2.h (enum iw_format_type): Add R2 formats.
	(enum overflow_type): Add signed_immed12_overflow and
	enumeration_overflow for R2.
	(struct nios2_opcode): Document new argument letters for R2.
	(REG_3BIT, REG_LDWM, REG_POP): Define.
	(includes): Include nios2r2.h.
	(nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
	(nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
	(nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
	(nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
	(nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
	(nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
	Declare.
	* nios2r2.h: New file.

	opcodes/
	* nios2-dis.c (nios2_extract_opcode): New.
	(nios2_disassembler_state): New.
	(nios2_find_opcode_hash): Use mach parameter to select correct
	disassembler state.
	(nios2_print_insn_arg): Extend to support new R2 argument letters
	and formats.
	(print_insn_nios2): Check for 16-bit instruction at end of memory.
	* nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
	(NIOS2_NUM_OPCODES): Rename to...
	(NIOS2_NUM_R1_OPCODES): This.
	(nios2_r2_opcodes): New.
	(NIOS2_NUM_R2_OPCODES): New.
	(nios2_num_r2_opcodes): New.
	(nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
	(nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
	(nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
	(nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
	(nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):	New.
2015-07-01 16:08:03 -07:00
Amit Pawar
9916071f8d Add support for monitorx/mwaitx instructions
gas/

	* config/tc-i386.c (cpu_arch): Add .mwaitx.
	(process_immext): Check operands for monitorx/mwaitx instructions.
	* doc/c-i386.texi: Document mwaitx.

gas/testsuite/

	* gas/i386/i386.exp: Add new mwaitx test cases.
	* gas/i386/mwaitx.s: New.
	* gas/i386/mwaitx-bdver4.d: New.
	* gas/i386/x86-64-mwaitx.s: New.
	* gas/i386/x86-64-mwaitx-bdver4.d: New.
	* gas/i386/mwaitx-reg.s: New.
	* gas/i386/mwaitx-reg.l: New.
	* gas/i386/x86-64-mwaitx-reg.l: New.
	* gas/i386/x86-64-mwaitx-reg.s: New.
	* gas/i386/arch-13.s: Updated.
	* gas/i386/arch-13.d: Updated.
	* gas/i386/arch-13-znver1.d: Updated.
	* gas/i386/x86-64-arch-3.s: Updated.
	* gas/i386/x86-64-arch-3.d: Updated.
	* gas/i386/x86-64-arch-3-znver1.d: Updated.

opcodes/

	* i386-dis.c (OP_Mwaitx): New.
	(rm_table): Add monitorx/mwaitx.
	* i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
	and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
	(operand_type_init): Add CpuMWAITX.
	* i386-opc.h (CpuMWAITX): New.
	(i386_cpu_flags): Add cpumwaitx.
	* i386-opc.tbl: Add monitorx and mwaitx.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2015-06-30 07:50:12 -07:00
Peter Bergner
7b9341139a PPC sync instruction accepts invalid and incompatible operands
ISA 2.07 added a new category called Elemental Memory Barriers that modifies
the sync instruction to accept an additional operand ESYNC.  Edmar added
support for this insruction varient here:

    https://sourceware.org/ml/binutils/2012-02/msg00221.html

Looking at this closer, I see that the insert_ls() function is misnamed
(since it's attached to the ESYNC operand, not the LS operand) but more
importantly, it is silently modifying the LS operand value behind the
users back when the LS operand is either invalid or is incompatible with
the new ESYNC operand.  The ISA 2.07 doc has an Assembler Note that clearly
states that assemblers that support the ESYNC operand should report all
invalid uses of LS and ESYNC.  This patch changes the assembler to
error out on invalid and incompatible operand usage.

opcodes/
	* ppc-opc.c (insert_ls): Test for invalid LS operands.
	(insert_esync): New function.
	(LS, WC): Use insert_ls.
	(ESYNC): Use insert_esync.

gas/testsuite/
	* gas/ppc/e6500.s <sync>: Fix invalid test.
	* gas/ppc/e6500.d: Likewise.
2015-06-22 14:55:24 -05:00
Nick Clifton
bdc4de1b24 Stop "objdump -d" from disassembling past a symbolic address.
include	* dis-asm.h (struct disassemble_info): Add stop_vma field.

binuti  * objdump.c (disassemble_bytes): Set the stop_vma field in the
	disassemble_info structure when disassembling code sections with
	-d.
	* doc/binutils.texi (objdump): Document the discrepancy between -d
	and -D.

opcodes	* dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
	requested region lies beyond it.
	* bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
	looking for 32-bit insns.
	* mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
	data.
	* sh-dis.c (print_insn_sh): Likewise.
	* tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
	blocks of instructions.
	* vax-dis.c (print_insn_vax): Check that the requested address
	does not clash with the stop_vma.

tests	* gas/arm/backslash-at.s: Add extra .byte directives so that the
	foo symbol does not appear to point half way through an
	instruction.
	* gas/arm/backslash-at.d: Update expected disassembly.
	* gas/i386/ilp32/x86-64-opcode-inval-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-opcode-inval.d: Likewise.
	* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
	* gas/i386/x86-64-opcode-inval.d: Likewise.
2015-06-22 16:53:27 +01:00
Peter Bergner
11a0cf2ec0 Allow for optional operands with non-zero default values.
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1.  It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case.  I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.

This fixes the rfebb issue.  I also fixed the mftb and mfcr instructions
so they use the same mechanism.  This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].

include/opcode/

	* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
	(ppc_optional_operand_value): New inline function.

opcodes/
	* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
	* ppc-opc.c (FXM4): Add non-zero optional value.
	(TBR): Likewise.
	(SXL): Likewise.
	(insert_fxm): Handle new default operand value.
	(extract_fxm): Likewise.
	(insert_tbr): Likewise.
	(extract_tbr): Likewise.

gas/
	* config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
	Allow for optional operands without insert functions.

gas/testsuite/
	* gas/ppc/power8.d: Fixup rfebb test results.
	* gas/ppc/a2.s: Fix invalid mfcr test.
	* gas/ppc/a2.d: Likewise.
2015-06-19 17:17:07 -05:00
Matthew Wahab
bdfa8b951b [AArch64] Support id_mmfr4 system register
2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
opcodes/
  * aarch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".

gas/testsuite
  * sysreg.d: Add id_mmfr4_el1, update expected output.
  * sysreg.s: Add id_mmfr4_el1.
2015-06-16 14:17:34 +01:00
Szabolcs Nagy
24b4cf66a6 Fixes a compile time warnng about left shifting a negative value.
* arm-dis.c (print_insn_coprocessor): Avoid negative shift.
2015-06-16 13:35:33 +01:00
Peter Bergner
99a2c56121 Remove unused MTMSRD_L macro and re-add accidentally deleted comment.
In the commit that added PowerPC Pair Singles, Ben accidentally removed
a comment and re-added an unused MTMSRD_L macro Alan had recently deleted.
This was probably just an oversite when he was refreshing his patch to
trunk.

opcodes/
	* ppc-opc.c: Add comment accidentally removed by old commit.
	(MTMSRD_L): Delete.
2015-06-12 15:06:07 -05:00
Peter Bergner
dc302c0061 Add hwsync extended mnemonic.
This commit adds a new extended menmonic for "sync 0" (same as "sync").
The ISA documentation doesn't explicitly mention hwsync as an extended
mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as
the operation that gets performed when the sync's L field is 0.
This is only enabled for POWER4 and later.

opcodes/
	* ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.

gas/testsuite/
	* gas/ppc/a2.d: Fixup test case due to new extended mnemonic.
	* gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests.
	* gas/ppc/power4.d: Likewise.
2015-06-04 20:27:03 -05:00
Nick Clifton
13be46a23c Fixes the check for emulated MSP430 instrucrtions that take no operands.
PR 18474
	* msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
2015-06-04 16:33:12 +01:00
Matthew Wahab
d6b4b13ed2 [ARM] Support for ARMv8.1 Adv.SIMD extension 2015-06-02 12:37:33 +01:00
Matthew Wahab
ddfded2f7b [ARM] Add support for ARMv8.1 PAN extension 2015-06-02 12:30:38 +01:00
Matthew Wahab
1af1dd51db [ARM] Rework CPU feature selection in the disassembler
include/opcode/
	* arm.h (ARM_FEATURE_ALL): New.

opcodes/
	* arm-dis.c (select_arm_features): Rework to avoid used of
	redefined macros.
2015-06-02 12:24:24 +01:00
Matthew Wahab
9e1f0fa7f3 [AArch64] Support for ARMv8.1a Adv.SIMD instructions
2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

gas/
  * config/tc-aarch64.c (aarch64_features): Add "rdma".
  * doc/c-aarch64.texi (AArch64 Extensions): Add "rdma".

gas/testsuite/
  * rdma-directive.d: New.
  * rdma.d: New.
  * rdma.s: New.

include/opcode/
  * aarch64.h (AARCH64_FEATURE_RDMA): New.

opcode/
  * aarch64-tbl.h (aarch64_feature_rdma): New.
  (RDMA): New.
  (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
  * aarch64-asm-2.c: Regenerate.
  * aarch64-dis-2.c: Regenerate.
  * aarch64-opc-2.c: Regenerate.
2015-06-02 12:20:00 +01:00
Matthew Wahab
290806fd94 [AArch64] Support for ARMv8.1a Limited Ordering Regions extension
2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
include/
  * aarch64.h (AARCH64_FEATURE_LOR): New.

opcodes/
  * aarch64-tbl.h (aarch64_feature_lor): New.
  (LOR): New.
  (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
  "stllrb", "stllrh".
  * aarch64-asm-2.c: Regenerate.
  * aarch64-dis-2.c: Regenerate.
  * aarch64-opc-2.c: Regenerate.

gas/
  * config/tc-aarch64.c (aarch64_features): Add "lor".
  * doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of
  architecture extensions.

gas/testsuite/
  * lor-directive.d: New.
  * lor.d: New.
  * lor.s: New.
2015-06-02 11:30:12 +01:00
Matthew Wahab
f21cce2cac [AArch64][libopcode] Add support for PAN architecture extension
The ARMv8.1 architecture introduced the Privileged Access Never extension. This
adds a processor state field PSTATE.PAN which can be accessed using the MRS/MSR
instructions.

This patch adds support for the PAN architecture feature and processor state
field to libopcode.

include/opcode
2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_PAN): New.
	(aarch64_sys_reg_supported_p): Declare.
	(aarch64_pstatefield_supported_p): Declare.

opcodes/
2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
	* aarch64-opc.c (F_ARCHEXT): New.
	(aarch64_sys_regs): Add "pan".
	(aarch64_sys_reg_supported_p): New.
	(aarch64_pstatefields): Add "pan".
	(aarch64_pstatefield_supported_p): New.
2015-06-01 16:00:28 +01:00
Jan Beulich
d194d186a7 x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s}
opcodes/
2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-tbl.h: Regenerate.
2015-06-01 11:40:28 +02:00
Jan Beulich
3a8547d2fb x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand order
As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so disassembler should produce output accordingly.

gas/testsuite/
2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* gas/i386/avx512f.s: Adjust operand order for Intel syntax
	vcvt{,u}si2ss.
	* gas/i386/x86-64-avx512f.s: Adjust operand order for Intel
	syntax vcvt{,u}si2s{d,s}.

opcodes/
2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (print_insn): Swap rounding mode specifier and
	general purpose register in Intel mode.
2015-06-01 09:51:28 +02:00
Jan Beulich
015c54d5a6 x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}
As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so gas should accept such input. As the brojen code got
released already we sadly will need to continue to also accept the
badly ordered operands.

gas/testsuite/
2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* gas/i386/avx512f-intel.d: Adjust expectations on operand order.
	* gas/i386/evex-lig256-intel.d: Likewise.
	* gas/i386/evex-lig512-intel.d: Likewise.
	* gas/i386/x86-64-avx512f-intel.d: Likewise.
	* gas/i386/x86-64-evex-lig256-intel.d: Likewise.
	* gas/i386/x86-64-evex-lig512-intel.d: Likewise.

opcodes/
2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	* i386-tbl.h: Regenerate.
2015-06-01 09:50:00 +02:00
H.J. Lu
071f0063b4 Remove Disp32 from AMD64 direct call/jmp
* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	* i386-init.h: Regenerated.
2015-05-18 04:17:12 -07:00
H.J. Lu
5db04b0965 Support AMD64/Intel ISAs in assembler/disassembler
AMD64 spec and Intel64 spec differ in direct unconditional branches in
64-bit mode.  AMD64 supports direct unconditional branches with 16-bit
offset via the data size prefix, which truncates RIP to 16 bits, while
the data size prefix is ignored by Intel64.

This patch adds -mamd64/-mintel64 option to x86-64 assembler and
-Mamd64/-Mintel64 option to x86-64 disassembler.  The most permissive
ISA, which is AMD64, is the default.

GDB can add an option, similar to

(gdb) help set disassembly-flavor
Set the disassembly flavor.
The valid values are "att" and "intel", and the default value is "att".

to select which ISA to disassemble.

binutils/

	PR binutis/18386
	* doc/binutils.texi: Document -Mamd64 and -Mintel64.

gas/

	PR binutis/18386
	* config/tc-i386.c (OPTION_MAMD64): New.
	(OPTION_MINTEL64): Likewise.
	(md_longopts): Add -mamd64 and -mintel64.
	(md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
	(md_show_usage): Add -mamd64 and -mintel64.
	* doc/c-i386.texi: Document -mamd64 and -mintel64.

gas/testsuite/

	PR binutis/18386
	* gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3.
	* gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump.
	* gas/i386/ilp32/x86-64-branch.d: Likewise.
	* gas/i386/x86-64-branch-2.d: New file.
	* gas/i386/x86-64-branch-2.s: Likewise.
	* gas/i386/x86-64-branch-3.l: Likewise.
	* gas/i386/x86-64-branch-3.s: Likewise.

ld/testsuite/

	PR binutis/18386
	* ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump.
	* ld-x86-64/tlspic.dd: Likewise.
	* ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to
	objdump for tlspic.dd and tlsgdesc.dd.

opcodes/

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2015-05-15 09:48:10 -07:00
Peter Bergner
4bc0608a8b Fix some PPC assembler errors.
Remove the wait instructions for server processors, since they were never
implemented.  Also add the extra operands added to the tlbie and slbia
instructions with ISA 2.06 and ISA 2.05 respectively.

binutils/
	* MAINTAINERS: Add myself as PPC maintainer.

opcodes/
        * ppc-opc.c (IH) New define.
        (powerpc_opcodes) <wait>: Do not enable for POWER7.
        <tlbie>: Add RS operand for POWER7.
        <slbia>: Add IH operand for POWER6.

gas/testsuite/
        * gas/ppc/power4.d: Add a slbia test.
        * gas/ppc/power4.s: Likewise.
        * gas/ppc/power6.d: Add slbia and tlbie tests.
        * gas/ppc/power6.s: Likewise.
        * gas/ppc/power7.d: Remove wait tests. Add a tlbie test.
        * gas/ppc/power7.s: Likewise.
2015-05-14 21:02:50 -05:00
H.J. Lu
31955f993d Add missing ChangeLog entries for PR binutis/18386 2015-05-13 04:33:45 -07:00
H.J. Lu
70cead0767 Remove Disp16|Disp32 from 64-bit direct branches
Disp16 and Disp32 aren't supported by direct branches in 64-bit mode.
This patch removes them from 64-bit direct branches.

	* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
	direct branch.
	(jmp): Likewise.
	* i386-tbl.h: Regenerated.
2015-05-11 14:20:37 -07:00
H.J. Lu
7b6d09fbc6 Add Intel MCU support to opcodes
* configure.ac: Support bfd_iamcu_arch.
	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	CPU_IAMCU_COMPAT_FLAGS.
	(cpu_flags): Add CpuIAMCU.
	* i386-opc.h (CpuIAMCU): New.
	(i386_cpu_flags): Add cpuiamcu.
	* configure: Regenerated.
	* i386-init.h: Likewise.
	* i386-tbl.h: Likewise.
2015-05-11 10:48:21 -07:00
H.J. Lu
a72d2af2c7 Ignore 0x66 prefix for call/jmp/jcc in 64-bit mode
The operand size prefix (0x66) is ignored for 32-bit PC-relative call,
jmp and jcc in 64-bit mode.

gas/testsuite/

	PR binutis/18386
	* gas/i386/i386.exp: Run x86-64-jump.
	* gas/i386/x86-64-branch.d: Updated.
	* gas/i386/ilp32/x86-64-branch.d: Likewise.
	* gas/i386/x86-64-branch.s: Add tests for the operand size prefix
	with call, jmp and jb.
	* gas/i386/x86-64-jump.d: New file.
	* gas/i386/x86-64-jump.s: Likewise.

ld/testsuite/

	PR binutis/18386
	* ld-x86-64/tlsgdesc.dd: Updated.
	* ld-x86-64/tlspic.dd: Likewise.

opcodes/

	PR binutis/18386
	* i386-dis.c (X86_64_E8): New.
	(X86_64_E9): Likewise.
	Update comments on 'T', 'U', 'V'.  Add comments for '^'.
	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	(mod_table): Replace {T|} with ^ on Jcall/Jmp.
	(putop): Handle '^'.
	(OP_J): Ignore the operand size prefix in 64-bit.  Don't check
	REX_W.
2015-05-09 06:44:29 -07:00
DJ Delorie
0952813b0b Make RL78 disassembler and simulator respect ISA for mul/div
[gas]
	* config/rl78-defs.h (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.
	* config/rl78-parse.y (ISA_G10): New.
	(ISA_G13): New.
	(ISA_G14): New.
	(MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them.
	* config/tc-rl78.c (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.

[gdb]
	* rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to
	rl78_decode_opcode

[include]
	* dis-asm.h (print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.
	* opcode/rl78.h (RL78_Dis_Isa): New.
	(rl78_decode_opcode): Add ISA parameter.

[opcodes]
	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

[sim]
	* rl78/cpu.c (g14_multiply): New.
	* rl78/cpu.h (g14_multiply): New.
	* rl78/load.c (rl78_load): Decode ISA completely.
	* rl78/main.c (main): Expand -M to include other ISAs.
	* rl78/rl78.c (decode_opcode): Decode based on ISA.
	* rl78/trace.c (rl78_disasm_fn): New.
	(sim_disasm_init): Reset it.
	(sim_disasm_one): Get correct disassembler for ISA.
2015-04-30 15:25:49 -04:00
Nick Clifton
f9d3ecaa78 Updated translations for various binutils components.
gold	* po/fi.po: Updated Finnish translation.

opcodes	* po/fr.po: Updated French translation.

gprof	* po/da.po: Update Danish translation.
2015-04-29 16:26:14 +01:00
Peter Bergner
4fff86c517 opcodes/
* ppc-opc.c (DCBT_EO): New define.
	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	<lharx>: Likewise.
	<stbcx.>: Likewise.
	<sthcx.>: Likewise.
	<waitrsv>: Do not enable for POWER7 and later.
	<waitimpl>: Likewise.
	<dcbt>: Default to the two operand form of the instruction for all
	"old" cpus.  For "new" cpus, use the operand ordering that matches
	whether the cpu is server or embedded.
	<dcbtst>: Likewise.

gas/testsuite/

	* gas/ppc/a2.s: Fixup test case due to dcbt/dcbtst embedded operand
	ordering change.
	* gas/ppc/a2.d: Likewise.
	* gas/ppc/476.d: Likewise.
	* gas/ppc/booke.s: Remove invalid 3 operand dcbt tests.
	* gas/ppc/booke.d: Likewise.
	* gas/ppc/power7.s: Remove lbarx, lharx, stbcx., sthcx., waitrsv
	and waitimpl tests.
	* gas/ppc/power7.d: Likewise.
2015-04-27 11:06:54 -05:00
Andreas Krebbel
3b78cfe103 S/390: Fixes for z13 instructions.
opcodes/
	* s390-opc.c: New instruction type VV0UU2.
	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	and WFC.

gas/testsuite/
	* gas/s390/zarch-z13.d: Fix tests for VFCE, VLDE, VFSQ, WFK, and
	WFC.
  	* gas/s390/zarch-z13.s: Likewise.
2015-04-27 10:29:16 +02:00
Jan Beulich
04d824a468 x86: disambiguate disassembly of certain AVX512 insns
Certain conversion operations as well as vfpclassp{d,s} are ambiguous
when the input operand is in memory and no broadcast is being used.
While in Intel mode this gets resolved by printing suitable operand
size modifiers, AT&T mode need mnemonic suffixes to be added.

gas/testsuite/
2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* gas/i386/avx512dq.d: Add 'z' suffix to vfpclassp{d,s} non-
	register, non-broadcast cases.
	* gas/i386/x86-64-avx512dq.d: Likewise.
	* gas/i386/avx512dq_vl.d: Add 'x' and 'y' suffixes to
	vcvt{,u}qq2ps and vfpclassp{d,s} non-register, non-broadcast
	cases.
	* gas/i386/x86-64-avx512dq_vl.d: Likewise.
	* gas/i386/avx512f_vl.d: Add 'x' and 'y' suffixes to
	vcvt{,t}pd2{,u}dq and vcvtpd2ps non-register, non-broadcast
	cases.
	* gas/i386/x86-64-avx512f_vl.d: Likewise.

opcodes/
2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	(vfpclasspd, vfpclassps): Add %XZ.
2015-04-23 16:42:40 +02:00
H.J. Lu
09708981e9 Remove the unused PREFIX_UD_XXX
Remove the unused PREFIX_UD_XXX.  Invalid opcodes should be handled by
prefix_table.

	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	(PREFIX_UD_REPZ): Likewise.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.
2015-04-15 16:00:36 -07:00