* config/tc-s390.c (s390_machine): New prototype.
(md_pseudo_table): New pseudo-op .machine.
(s390_opcode_hash): Initialize to NULL.
(s390_parse_cpu): New function.
(md_parse_option): Use s390_parse_cpu.
(s390_setup_opcodes): New function.
(md_begin): Use s390_setup_opcodes.
(s390_machine): New hook handling the new .machine pseudo.
* doc/c-s390.texi: Document the new pseudo op .machine.
2011-04-14 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/zarch-machine.s: New testcase.
* gas/s390/zarch-machine.d: New testcase output.
* gas/s390/s390.exp: Execute the new testcase.
* tic6x.h (R_C6000_JUMP_SPLOT, R_C6000_EHTYPE,
R_C6000_PCR_H16, R_C6000_PCR_L16): New relocs.
(SHN_TIC6X_SCOMMON): Define.
bfd/
* elf32-tic6x.h (struct elf32_tic6x_params): New.
(elf32_tic6x_setup): Declare.
* elf32-tic6x.c: Include <limits.h>.
(ELF_DYNAMIC_LINKER, DEFAULT_STACK_SIZE, PLT_ENTRY_SIZE): Define.
(struct elf32_tic6x_link_hash_table, struct elf32_link_hash_entry):
New structures.
(elf32_tic6x_link_hash_table, is_tic6x_elf): New macros.
(tic6x_elf_scom_section, tic6x_elf_scom_symbol,
tic6x_elf_scom_symbol_ptr): New static variables.
(elf32_tic6x_howto_table, elf32_tic6x_howto_table_rel,
elf32_tic6x_reloc_map): Add R_C6000_JUMP_SLOT, R_C6000_EHTYPE,
R_C6000_PCR_H16 and R_C6000_PCR_L16.
(elf32_tic6x_link_hash_newfunc, elf32_tic6x_link_hash_table_create,
elf32_tic6x_link_hash_table_free, elf32_tic6x_setup,
elf32_tic6x_using_dsbt, elf32_tic6x_install_rela,
elf32_tic6x_create_dynamic_sections, elf32_tic6x_make_got_dynreloc,
elf32_tic6x_finish_dynamic_symbol, elf32_tic6x_gc_sweep_hook,
elf32_tic6x_adjust_dynamic_symbol): New static functions.
(elf32_tic6x_relocate_section): For R_C6000_PCR_S21, convert branches
to weak symbols as required by the ABI.
Handle GOT and DSBT_INDEX relocs, and copy relocs to the output file
as needed when generating DSBT output.
(elf32_tic6x_check_relocs, elf32_tic6x_add_symbol_hook,
elf32_tic6x_symbol_processing, elf32_tic6x_section_from_bfd_section,
elf32_tic6x_allocate_dynrelocs, elf32_tic6x_size_dynamic_sections,
elf32_tic6x_always_size_sections, elf32_tic6x_modify_program_headers,
elf32_tic6x_finish_dynamic_sections, elf32_tic6x_plt_sym_val,
elf32_tic6x_copy_private_data, elf32_tic6x_link_omit_section_dynsym):
New static functions.
(ELF_MAXPAGESIZE): Define to 0x1000.
(bfd_elf32_bfd_copy_private_bfd_data,
bfd_elf32_bfd_link_hash_table_create,
bfd_elf32_bfd_link_hash_table_free, elf_backend_can_refcount,
elf_backend_want_got_plt, elf_backend_want_dynbss,
elf_backend_plt_readonly, elf_backend_got_header_size,
elf_backend_gc_sweep_hook, elf_backend_modify_program_headers,
elf_backend_create_dynamic_sections, elf_backend_adjust_dynamic_symbol,
elf_backend_check_relocs, elf_backend_add_symbol_hook,
elf_backend_symbol_processing, elf_backend_link_output_symbol_hook,
elf_backend_section_from_bfd_section,
elf_backend_finish_dynamic_symbol, elf_backend_always_size_sections,
elf32_tic6x_size_dynamic_sections, elf_backend_finish_dynamic_sections,
elf_backend_omit_section_dynsym, elf_backend_plt_sym_val): Define.
* bfd/reloc.c (BFD_RELOC_C6000_JUMP_SLOT, BFD_RELOC_C6000_EHTYPE,
BFD_RELOC_C6000_PCR_H16, BFD_RELOC_C6000_PCR_S16): Add.
* bfd/bfd-in2.h: Regenerate.
* bfd/libbfd.h: Regenerate.
* config.bfd: Accept tic6x-*-* instead of tic6x-*-elf.
gas/
* config/tc-tic6x.c (sbss_section, scom_section, scom_symbol): New
static variables.
(md_begin): Initialize them.
(s_tic6x_scomm): New static function.
(md_pseudo_table): Add "scomm".
(tc_gen_reloc): Really undo all adjustments made by
bfd_install_relocation.
* doc/c-tic6x.texi: Document the .scomm directive.
gas/testsuite/
* gas/tic6x/scomm-directive-1.s: New test.
* gas/tic6x/scomm-directive-1.d: New test.
* gas/tic6x/scomm-directive-2.s: New test.
* gas/tic6x/scomm-directive-2.d: New test.
* gas/tic6x/scomm-directive-3.s: New test.
* gas/tic6x/scomm-directive-3.d: New test.
* gas/tic6x/scomm-directive-4.s: New test.
* gas/tic6x/scomm-directive-4.d: New test.
* gas/tic6x/scomm-directive-5.s: New test.
* gas/tic6x/scomm-directive-5.d: New test.
* gas/tic6x/scomm-directive-6.s: New test.
* gas/tic6x/scomm-directive-6.d: New test.
* gas/tic6x/scomm-directive-7.s: New test.
* gas/tic6x/scomm-directive-7.d: New test.
* gas/tic6x/scomm-directive-8.s: New test.
* gas/tic6x/scomm-directive-8.d: New test.
ld/
* emulparams/elf32_tic6x_le.sh (BIG_OUTPUT_FORMAT, EXTRA_EM_FILE,
GENERATE_SHLIB_SCRIPT): New defines.
(TEXT_START_ADDR): Define differently depending on target.
(.got): Redefine to include "*(.dsbt)".
(SDATA_START_SYMBOLS): Remove, replace with
(OTHER_GOT_SYMBOLS): New.
(OTHER_BSS_SECTIONS): Define only for ELF targets.
* emultempl/tic6xdsbt.em: New file.
* gen-doc.texi: Set C6X.
* ld.texinfo: Likewise.
(Options specific to C6X uClinux targets): New section.
binutils/
* readelf.c (get_symbol_index_type): Handle SCOM for TIC6X.
(dump_relocations): Likewise.
binutils/testsuite/
* lib/binutils-common.exp (is_elf_format): Accept tic6x*-*-uclinux*.
ld/testsuite/
* ld-scripts/crossref.exp: Add CFLAGS for tic6x*-*-*.
* ld-elf/sec-to-seg.exp: Remove tic6x from list of targets defining
pagesize to 1.
* ld-tic6x/tic6x.exp: Add support for DSBT shared library/executable
linking tests.
* ld-tic6x/dsbt.ld: New linker script.
* ld-tic6x/dsbt-be.ld: New linker script.
* ld-tic6x/dsbt-overflow.ld: New linker script.
* ld-tic6x/dsbt-inrange.ld: New linker script.
* ld-tic6x/shlib-1.s: New test.
* ld-tic6x/shlib-2.s: New test.
* ld-tic6x/shlib-app-1r.s: New test.
* ld-tic6x/shlib-app-1.s: New test.
* ld-tic6x/shlib-1.sd: New test.
* ld-tic6x/shlib-1.dd: New test.
* ld-tic6x/shlib-app-1.rd: New test.
* ld-tic6x/shlib-app-1rb.rd: New test.
* ld-tic6x/shlib-app-1.sd: New test.
* ld-tic6x/static-app-1rb.od: New test.
* ld-tic6x/shlib-app-1.dd: New test.
* ld-tic6x/shlib-app-1rb.sd: New test.
* ld-tic6x/static-app-1b.od: New test.
* ld-tic6x/static-app-1r.od: New test.
* ld-tic6x/shlib-1rb.rd: New test.
* ld-tic6x/shlib-app-1rb.dd: New test.
* ld-tic6x/shlib-1rb.sd: New test.
* ld-tic6x/shlib-1rb.dd: New test.
* ld-tic6x/shlib-app-1b.od: New test.
* ld-tic6x/tic6x.exp: New test.
* ld-tic6x/static-app-1rb.rd: New test.
* ld-tic6x/shlib-app-1r.od: New test.
* ld-tic6x/static-app-1.od: New test.
* ld-tic6x/static-app-1b.rd: New test.
* ld-tic6x/static-app-1r.rd: New test.
* ld-tic6x/static-app-1rb.sd: New test.
* ld-tic6x/static-app-1b.sd: New test.
* ld-tic6x/static-app-1rb.dd: New test.
* ld-tic6x/static-app-1r.sd: New test.
* ld-tic6x/static-app-1b.dd: New test.
* ld-tic6x/shlib-1b.rd: New test.
* ld-tic6x/static-app-1r.dd: New test.
* ld-tic6x/shlib-app-1b.rd: New test.
* ld-tic6x/shlib-1r.rd: New test.
* ld-tic6x/shlib-app-1r.rd: New test.
* ld-tic6x/shlib-1b.sd: New test.
* ld-tic6x/static-app-1.rd: New test.
* ld-tic6x/shlib-app-1b.sd: New test.
* ld-tic6x/shlib-1r.sd: New test.
* ld-tic6x/shlib-1b.dd: New test.
* ld-tic6x/shlib-app-1r.sd: New test.
* ld-tic6x/shlib-app-1b.dd: New test.
* ld-tic6x/shlib-1r.dd: New test.
* ld-tic6x/static-app-1.sd: New test.
* ld-tic6x/shlib-app-1r.dd: New test.
* ld-tic6x/static-app-1.dd: New test.
* ld-tic6x/shlib-noindex.rd: New test.
* ld-tic6x/shlib-noindex.dd: New test.
* ld-tic6x/shlib-noindex.sd: New test.
* ld-tic6x/got-reloc-local-1.s: New test.
* ld-tic6x/got-reloc-local-2.s: New test.
* ld-tic6x/got-reloc-local-r.d: New test.
* ld-tic6x/got-reloc-global.s: New test.
* ld-tic6x/got-reloc-global-addend-1.d: New test.
* ld-tic6x/got-reloc-global-addend-1.s: New test.
* ld-tic6x/got-reloc-global-addend-2.d: New test.
* ld-tic6x/got-reloc-inrange.d: New test.
* ld-tic6x/got-reloc-overflow.d: New test.
* ld-tic6x/got-reloc-global-addend-2.s: New test.
* ld-tic6x/dsbt-index-error.d: New test.
* ld-tic6x/dsbt-index.d: New test.
* ld-tic6x/dsbt-index.s: New test.
* ld-tic6x/shlib-app-1.od: New test.
* ld-tic6x/shlib-app-1rb.od: New test.
* ld-tic6x/shlib-1.rd: New test.
* ld-tic6x/weak.d: New test.
* ld-tic6x/weak-be.d: New test.
* ld-tic6x/weak.s: New test.
* ld-tic6x/weak-data.d: New test.
* ld-tic6x/common.d: New test.
* ld-tic6x/common.ld: New test.
* ld-tic6x/common.s: New test.
The destination registers must be different with BYTEUNPACK insns,
otherwise the hardware throws up an exception. So reject them.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The destination registers must be different with BYTEOP16M insns,
otherwise the hardware throws up an exception. So reject them.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The destination registers must be different with BYTEOP16P insns,
otherwise the hardware throws up an exception. So reject them.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The 16bit acc add insn cannot assign the two results to the same dreg,
so make sure gas rejects attempts to use this insn variant.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The destination registers with vector add/sub insns must be different,
so make sure gas rejects attempt to write these.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current 16bit insn test doesn't actually cover all illegal insns
since it stops at 0xa000 instead of 0xc000. But rather than address
that, replace it with a test that covers all 16bit insns.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
While we were catching a few mismatches in vectorized dsp mult insns,
the error we displayed was misleading. Once we fix that up, we can
convert previously dead code into proper checking for destination
dreg matching.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The destination registers for SEARCH cannot be the same. Same rule
for the source registers for BITMUX.
Signed-off-by: Mike Frsyinger <vapier@gentoo.org>
gas/
2011-03-05 H.J. Lu <hongjiu.lu@intel.com>
* config/obj-elf.c (elf_frob_symbol): Mention symbol name in
non-constant .size expression.
gas/testsuite/
2011-03-05 H.J. Lu <hongjiu.lu@intel.com>
* gas/elf/bad-size.err: Updated.
gas/
2011-03-04 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (x86_cie_stack_alignment): New.
(md_begin): Set x86_cie_data_alignment if it isn't set. Set
x86_cie_stack_alignment.
(i386_target_format): Set x86_cie_data_alignment to -4 for x32.
(tc_x86_frame_initial_instructions): Use x86_cie_stack_alignment
instead of x86_cie_data_alignment on SP and RA.
gas/testsuite/
2011-03-04 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/ilp32/cfi/cfi-x86_64.d: Updated.
* mips-opc.c (mips_builtin_opcodes): Correct register use
annotation of "alnv.ps".
gas/testsuite/
* gas/mips/alnv_ps-swap.d: New test for ALNV.PS instruction
branch swapping.
* gas/mips/alnv_ps-swap.s: Source for the new test.
* gas/mips/mips.exp: Run the new test.
* config/tc-mips.c (append_insn): Disable branch relaxation for
DSP instructions.
gas/testsuite/
* gas/mips/relax-bposge.l: New test for DSP branch relaxation.
* gas/mips/relax-bposge.s: Source for the new test.
* gas/mips/mips.exp: Run the new test.
* config/tc-mips.c (RELAX_BRANCH_ENCODE): Encode the temporary
register to use.
(RELAX_BRANCH_UNCOND): Adjust accordingly.
(RELAX_BRANCH_LIKELY): Likewise.
(RELAX_BRANCH_LINK): Likewise.
(RELAX_BRANCH_TOOFAR): Likewise.
(RELAX_BRANCH_AT): New macro.
(append_insn): Encode the temporary register to use in standard
MIPS branch relaxation.
(relaxed_branch_length): Update according to changes to
RELAX_BRANCH_ENCODE.
(md_convert_frag): Use the encoded register as the temporary.
gas/testsuite/
* gas/mips/relax-at.d: New test for branch relaxation with .set
at.
* gas/mips/relax.s: Update to support the new test.
* gas/mips/relax.l: Update accordingly.
* gas/mips/relax.d: Update for multi-arch invocation.
* gas/mips/mips.exp: Run the new test. Adjust to run "relax"
across all applicable architectures.
* config/tc-mips.c (mips_fix_adjustable): On REL targets also
reject PC-relative relocations.
gas/testsuite/
* gas/mips/branch-misc-2.d: Adjust for relocation change.
* gas/mips/branch-misc-2pic.d: Likewise.
* gas/mips/branch-misc-4.d: New test for PC-relative relocation
overflow.
* gas/mips/branch-misc-4-64.d: Likewise.
* gas/mips/branch-misc-4.s: Source for the new tests.
* testsuite/gas/mips/mips.exp: Run the new tests.
The single cycle dual mac ABS insn was incorrectly decoding the mac1
part of the insn.
Once we fix the decode, update the gas tests to have the correct output.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When assigning to a register half, the mac0 part of the mult insn
was not decoding properly. It would always show a full dreg instead
of the dreg low half.
Once we fix the disassembler, we have to update a few of the gas
tests as their previous expected output was incorrect.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The BYTEOP2M insn was part of the initial Blackfin designs, but never made
it into any actual silicon. So punt support for it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
value when reporting the inability to write to the output file.
* config/tc-rx.c (rx_handle_align): Do not insert NOPs into align
frag that has a non-zero fill value.
* gas/all/align.d: Skip for the RX.
* gas/elf/group1a.d: Likewise.
* gas/elf/groupautoa.d: Likewise.
* gas/elf/elf.exp: Do not run section5 test for the RX port.
* gas/elf/section4.d: Likewise.
* gas/elf/section7.d: Likewise.
* gas/macros/semi.s: Fill with a non-zero pattern.
* gas/macros/semi.d: Expect non-zero fill value.
* gas/rx/bcnd.d: Update expected disassembly.
* gas/rx/bra.d: Likewise.
* gas/rx/macros.inc: Add reg1 macro.
* gas/rx/max.sm: Use reg1 macro to avoid generating illegal NOP
instruction.
* gas/rx/mov.sm: Likewise.
* gas/rx/max.d: Update expected disassembly.
* gas/rx/mov.d: Likewise.
* gas/rx/rx-asm-good.s: Use Renesas section names.
* gas/rx/rx-asm-good.d: Update expected disassembly.
2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/ilp32/lns/lns-common-1.d: Also expect .zdebug in
section name.
* gas/i386/ilp32/lns/lns-duplicate.d: Likewise.
* config/tc-hppa.c (pa_ip): Set doubleword carry/borrow bit when a
doubleword completer or doubleword condition is found in an add/sub
instruction. Reject match for 'A'/'S' only if there is no condition
and d bit is not set.
* gas/hppa/basic/add2.s: Add test for a simple doubleword carry
instruction.
* gas/hppa/basic/sub2.s: Add tests for simple word and doubleword
borrow instructions.
* gas/hppa/basic/basic.exp: Update regexps for above.
* opcode/hppa.h: Clear "d" bit in "add" and "sub" patterns.
2010-12-03 Mingming Sun <mingm.sun@gmail.com>
* mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
fixed point instructions.
gas/testsuite/
2010-12-03 Mingming Sun <mingm.sun@gmail.com>
* gas/mips/loongson-3a.s, gas/mips/loongson-3a.d: New test.
* gas/mips/mips.exp: Run it.
* config/tc-mips.c (file_ase_mips16): Adjust comment.
(append_insn): Update file_ase_mips16.
(mips_after_parse_args): Don't set file_ase_mips16 here.
gas/testsuite/
* gas/mips/elf_ase_mips16.d: Update test for new MIPS16 ASE flag
semantics.
* gas/mips/elf_ase_mips16-2.d: New test.
* gas/mips/nop.s: Source for the new test.
* gas/mips/mips.exp: Run the new test.
binutils/testsuite/
* lib/binutils-common.exp (regexp_diff): Implement inverse
matching, requested by `!'.
* config/tc-mips.c (macro) <ld_st>: Don't load a zero into an
auxiliary register when using a signed 16-bit constant offset.
gas/testsuite/
* gas/mips/ldstla-32.d: Update according to a 16-bit constant
offset optimization.
* gas/mips/ldstla-32-mips3.d: Likewise.
* gas/mips/ldstla-32-shared.d: Likewise.
* gas/mips/ldstla-32-mips3-shared.d: Likewise.
* symbols.c (S_FORCE_RELOC): Return true for indirect functions
even if !strict.
* expr.c (operand): Don't convert absolute symbols to constants
if S_FORCE_RELOC is true.
(expr): Only reduce subtractions between different symbols if
S_FORCE_RELOC is false for both of them.
* write.c (fixup_segment): Don't remove symbols if S_FORCE_RELOC
is true for them, regardless of their segment.
gas/testsuite/
* gas/i386/ifunc-2.s, gas/i386/ifunc-2.l: New test.
* gas/i386/ifunc-3.s, gas/i386/ifunc-3.d: Likeise.
* gas/i386/i386.exp: Run them.
* gas/config/tc-arm.c (arm_arch_v6m_only): New variable.
(aeabi_set_public_attributes): Ensure we only set the Operating System
Extension when we are on an M-profile core.
* gas/testsuite/gas/arm/pr12198-1.d: New test.
* gas/testsuite/gas/arm/pr12918-1.s: Likewise.
* gas/testsuite/gas/arm/pr12198-2.d: Likewise.
* gas/testsuite/gas/arm/pr12918-2.s: Likewise.
* include/opcode/arm.h (ARM_AEXT_V6M_ONLY): New define.
(ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
(ARM_ARCH_V6M_ONLY): New define.
* config/tc-mips.c (macro_build): Remove gas_assert from 'o' case.
Use a restricted gas_assert for 'i' and 'j'.
gas/testsuite/
* gas/mips/elf-rel28.s, gas/mips/elf-rel28-n32.d,
gas/mips/elf-rel28-n64.d: New test.
* gas/mips/mips.exp: Run it.
2010-10-25 H.J. Lu <hongjiu.lu@intel.com>
PR gas/12049
* gas/i386/i386.exp: Run relax-1 and relax-2 for all 32bit
targets. Run x86-64-relax-1.
* gas/i386/x86-64-relax-1.d: New.
* gas/i386/x86-64-relax-1.s: Likewise.
defined/declared (as appropriate) at the end of assembly, based
on the presence or not of the "forward" symbol.
* gas/mips/ld-forward.d: New test.
* gas/mips/mips1@ld-forward.d: Likewise. MIPS I version.
* gas/mips/r3000@ld-forward.d: Likewise, R3000 version.
* gas/mips/ecoff@ld-forward.d: Likewise, ECOFF version.
* gas/mips/r3900@ecoff@ld-forward.d: Likewise, R3900/ECOFF
version.
* gas/mips/mips2@ecoff@ld-forward.d: Likewise, MIPS II/ECOFF
version.
* gas/mips/mips32@ecoff@ld-forward.d: Likewise, MIPS32/ECOFF
version.
* gas/mips/mips32r2@ecoff@ld-forward.d: Likewise, MIPS32r2/ECOFF
version.
* gas/mips/ld-n32-forward.d: New test.
* gas/mips/ld-n64-forward.d: Likewise.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/ld.d: Remove "-march=r4000" and "-mmips:4000" from
gas/objdump options.
* gas/mips/ld-ilocks.d: Add "-32" to gas options.
* gas/mips/mips.exp: Run the two cases with run_dump_test_arches.
* config/obj-elf.c (elf_adjust_symtab): New. Move group section
processing here from elf_frob_file. Ensure that group signature
symbols have the name of the group.
(elf_frob_file): Move group section processing to
elf_adjust_symtab.
* config/obj-elf.h (elf_adjust_symtab): Declare.
(obj_adjust_symtab): Define.
* config/tc-arm.c (arm_adjust_symtab): Call elf_adjust_symtab.
2010-10-23 Mark Mitchell <mark@codesourcery.com>
* gas/elf/elf.exp: Add group0c test.
* gas/elf/group0c.d: New.
* gas/elf/group0a.d: Expect ".group" for the name of group
sections.
* gas/elf/group0b.d: Likewise.
* gas/elf/group1a.d: Likewise.
* gas/elf/group1b.d: Likewise.
* gas/elf/groupautoa.d: Likewise.
* gas/elf/groupautob.d: Likewise.
* gas/elf/section4.d: Likewise.
* gas/ia64/group-1.d: Likewise. Adjust hard-coded constants.
2010-10-22 Mark Mitchell <mark@codesourcery.com>
* binutils-all/group-5.d: Expect ".group" for the name of group
sections.
* binutils-all/strip-2.d: Likewise.
2010-10-23 Mark Mitchell <mark@codesourcery.com>
* ld-elf/group10.d: Expect ".group" for the name of group
sections.
* ld-elf/group2.d: Likewise.
* ld-elf/group7.d: Likewise.
* gas/arm/msr-reg-thumb.d: Skip for non-ELF based targets.
* gas/arm/vldr.d: Likewise.
* gas/arm/thumb2_ldmstm.d: Allow for extra NOPs at the end of the disassembly.
* gas/cfi/cfi.exp (cfi-arm-1): Only run for ELF based ARM targets.
explicitly. Clean up some regexps.
* gas/mips/ld-ilocks.d: Likewise. Add missing "$" prefixes to
the names of FP registers.
* gas/mips/ld-ilocks-addr32.d: Likewise.
* gas/mips/ld.s: Align sections to 4k, adjust padding.
* mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
macros before their corresponding MIPS III hardware instructions.
gas/
* config/tc-mips.c (macro)[M_LD_OB, M_SD_OB]: Handle 64-bit ABIs.
gas/testsuite/
* gas/mips/lineno.s: Convert to o32.
* gas/mips/lineno.d: Adjust patterns accordingly. Force the o32
ABI.
Make sure all illegal insns get assembled & decoded correctly.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The BYTEOP2M parser incorrectly calls BYTEOP2P to generate the opcode.
Once we've fixed that, it's easy to see that the disassembler also likes
to decode this insn incorrectly. So fix that and then add some tests.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The exact symbol addresses are not important to these tests. We only
care about the opcodes and the disassembly output. This makes adding
more insns to these tests easier.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
gas/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (_i386_insn): Add disp32_encoding.
(md_assemble): Don't call optimize_disp if disp32_encoding is
set.
(parse_insn): Support .d32 to force 32bit displacement.
(output_branch): Use BIG if disp32_encoding is set.
* doc/c-i386.texi: Document .d32 encoding suffix.
gas/testsuite/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/disp32.d: New.
* gas/i386/disp32.s: Likewise.
* gas/i386/x86-64-disp32.d: Likewise.
* gas/i386/x86-64-disp32.s: Likewise.
* gas/i386/i386.exp: Run disp32 and x86-64-disp32.
* s390-opc.c: Make the instruction masks for the load/store on
condition instructions to cover the condition code mask as well.
* s390-opc.txt: lgoc -> locg and stgoc -> stocg.
2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/zarch-z196.d: Adjust the load/store on condition
instructions.
* gas/s390/zarch-z196.s: Likewise.
* config/tc-tic6x.c (tic6x_try_encode): Correct encoding of fstg field
in SPKERNEL instructions.
opcodes/
* tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
in SPKERNEL instructions.
gas/testsuite/
* gas/tic6x/insns-c674x-sploop.d: Add two more sploop/spkernel tests.
* gas/tic6x/insns-c674x-sploop.s: Likewise.
* config/tc-mips.c (mips_fix_cn63xxp1): New variable.
(mips_ip): Add errata work around when mips_fix_cn63xxp1 set.
(OPTION_FIX_CN63XXP1, OPTION_NO_FIX_CN63XXP1): New enum options
enumerations.
(md_longopts): Add options for -mfix-cn63xxp1 and -mno-fix-cn63xxp1.
(md_parse_option): Handle OPTION_FIX_CN63XXP1 and
OPTION_NO_FIX_CN63XXP1.
(md_show_usage): Add documentation for -mfix-cn63xxp1.
* doc/c-mips.texi (-mfix-cn63xxp1, -mno-fix-cn63xxp1): Document
the new options.
2010-10-04 David Daney <ddaney@caviumnetworks.com>
* gas/mips/mips.exp (octeon-pref): Run the new test.
* gas/mips/octeon-pref.s: New test.
* gas/mips/octeon-pref.d: New expected results for the new test.
* gas/config/tc-arm.c (arm_ext_virt): New variable.
(arm_reg_type): Add REG_TYPE_RNB for banked registers.
(reg_entry): Allow registers to be larger than a byte.
(reg_alias): Fix type warning.
(parse_operands): Parse banked registers when appropriate.
(do_mrs): Add support for Virtualization Extensions.
(do_hvc): New function.
(do_t_mrs): Add support for Virtualization Extensions.
(do_t_msr): Likewise.
(do_t_hvc): New function.
(SPLRBANK): New define.
(reg_names): Add banked registers.
(insns): Add support for Virtualization Extensions.
(md_apply_fixup): Likewise.
(arm_cpus): -mcpu=cortex-a15 implies the Virtualization Extensions.
(arm_extensions): Add 'virt' extension.
(aeabi_set_public_attributes): Add support for Virtualization
Extensions.
* gas/doc/c-arm.texi: Document 'virt' extension.
* gas/testsuite/gas/arm/armv7-a+virt.d: New test.
* gas/testsuite/gas/arm/armv7-a+virt.s: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for Virtualization Extensions.
* gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d: New test.
* gas/testsuite/gas/arm/attr-march-armv7-a+virt.d: Likewise.
* include/opcode/arm.h (ARM_EXT_VIRT): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
(ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
Extensions.
* opcodes/arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
(thumb32_opcodes): Likewise.
(banked_regname): New function.
(print_insn_arm): Add Virtualization Extensions support.
(print_insn_thumb32): Likewise.
(do_div): New function.
(insns): Accept UDIV and SDIV in ARM state.
(arm_cpus): The cortex-a15 option has all current v7-A extensions.
(arm_extensions): Add 'idiv' extension.
(aeabi_set_public_attributes): Update Tag_DIV_use values for the
Integer Divide extension.
* gas/doc/c-arm.texi: Document the idiv extension.
* gas/testsuite/gas/arm/armv7-a+idiv.d: New test.
* gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension.
* gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test.
* include/opcode/arm.h (ARM_AEXT_ADIV): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
* opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
ARM state.
(arm_ext_m): Add support for OS extension.
(arm_ext_os): New variable.
(do_t_swi): In v6-M ensure we have the OS extension.
(arm_cpus): The cortex-m1 and cortex-m0 options have the OS
extension by default.
(arm_archs): Add armv6s-m.
(arm_extensions): Add 'os' extension.
(cpu_arch_ver): Add support for v6S-M.
* gas/doc/c-arm.texi: Document the OS Extension, and v6-m and v6s-m
architecture options.
* gas/testsuite/gas/arm/archv6s-m-bad.d: New test.
* gas/testsuite/gas/arm/archv6s-m-bad.l: Likewise.
* gas/testsuite/gas/arm/archv6s-m.d: Likewise.
* gas/testsuite/gas/arm/archv6s-m.s: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6-m+os.d: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6s-m.d: Likewise.
* include/opcode/arm.h (ARM_EXT_OS): New define.
(ARM_AEXT_V6SM): Likewise.
(ARM_ARCH_V6SM): Likewise.
Using "Register mismatch" everywhere can be a bit vague, so clarify
why exactly we're barfing on these unsupported insns.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some extended registers when given to the DBG/DBGCMPLX pseudo insns are
not encoded properly. So fix them, fix the display of them when being
disassembled, and add testcases.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT,
ASHIFT, or BXORSHIFT. So be specific when disassembling.
As fall out of this change, we need to update some assembler tests.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas/testsuite/gas/arm/attr-cpu-directive.d: Update test for change in canonical
CPU name.
* gas/testsuite/gas/arm/attr-mcpu.d: Likewise.
* ld/testsuite/ld-arm/attr-merge-6.attr: Update tests for change in canonical
CPU name.
* ld/testsuite/ld-arm/attr-merge-7.attr: Likewise.
* ld/testsuite/ld-arm/attr-merge-2.attr: Likewise.
* ld/testsuite/ld-arm/attr-merge-arch-2.attr: Likewise.
* config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead
of just RR.
2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
* gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand.
* gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv. Also
add disassembly for test added in copro.s
2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
* arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
