Commit graph

70 commits

Author SHA1 Message Date
Mike Frysinger
cc5add8c1c sim: bfin: lookup target strings when tracing system calls
Parsing target addresses is hard if not generally useless, so use the new
cb_get_string function to lookup the associated strings as well.  Now the
trace output is quickly useful instead of just marginally so.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-12-03 19:05:15 +00:00
Mike Frysinger
db2e4d67e7 sim: generate build dependencies on the fly
Lift the code that GDB is using to generate dependencies on the fly and
port it over to the sim.  Now people shouldn't have to manually maintain
these in their Makefile's.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-12-03 18:23:51 +00:00
Mike Frysinger
4399a56be2 sim: dv-cfi: check for log2 support in libm when enabled
The dv-cfi model uses log2() internally, so make sure we automatically
link in libm when required.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-19 21:28:27 +00:00
Mike Frysinger
9c082ca86e sim: rename common/aclocal.m4 to common/acinclude.m4
Automake likes to dump macros automatically used into the aclocal.m4
file, but the common/aclocal.m4 naming prevents that.  So rename it
to the more normal "acinclude.m4" so the aclocal tool can work.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-18 00:31:00 +00:00
Mike Frysinger
6ffe910a7e sim: move from common.m4 to SIM_AC_COMMON
Now that the sourceware tree generally requires autoconf-2.64, update
the sim tree to require that too.

This allows us to drop the long standing SIM_AC_COMMON/common.m4
workaround as autoconf 2.64+ seems to work for me.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-18 00:17:24 +00:00
Mike Frysinger
39c1f96aef sim: bfin: use store buffer for VIT_MAX insns
The VIT_MAX insns can be used in parallel, so we need to use the store
buffer so we don't clobber the output register before we get a chance
to do a memory store with it.

Reported-by: Kai Iskratsch <kai@stella.at>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-09-29 03:19:47 +00:00
Mike Frysinger
2419798b80 sim: start a unified sim_do_command
Since sim_do_command for many people simply calls sim_args_command, start
a unified version of it.  For people who handle their own options, they
could switch to this by using sim_add_option_table instead.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-05 19:06:38 +00:00
Mike Frysinger
a931db6a07 sim: bfin: implement stat_map for virtual environments (libgloss)
The stat syscalls cannot work without a stat map, so declare one that
matches libgloss for virtual environments.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-01 21:53:03 +00:00
Mike Frysinger
ce2486ab20 sim: bfin: pass up result2/errcode with libgloss syscalls
Now that the Blackfin libgloss code extracts the 2nd result and the
error code from the R1/R2 registers, have the sim fill them up.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-22 04:21:29 +00:00
Mike Frysinger
1f20b1457b sim: bfin: set ASTAT AV/AVS when shifting accumulators overflow
The LSHIFT/ASHIFT insns that work with accumulators lacked AV/AVS
handling in the ASTAT register, so add it to match the hardware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 22:03:10 +00:00
Mike Frysinger
b4876e0485 sim: bfin: do not touch ASTAT[V] when shifting accumulators
If we're shifting accumulators, we don't want to touch the V bit in
ASTAT, so add size checks to the ashiftrt/lshiftrt helpers.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 21:59:38 +00:00
Mike Frysinger
d5fcd950e4 sim: bfin: do not extend accumulator in LSHIFT insns
The logical shift insn does not sign extend before shifting, so
we shouldn't either.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 21:58:08 +00:00
Mike Frysinger
a56a195412 sim: bfin: tweak saturation handling with TFU/FU modes and MM bit
This too should have been squashed into an earlier change.  It covers
a few more cases in the V/VS saturation patch when working with TFU
and FU modes of dsp insns.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 21:22:50 +00:00
Mike Frysinger
90e13d65c1 sim: bfin: handle large shift values with accumulator shift insns
When the shift magnitude exceeds 32 bits, the values rotate around (since
the hardware is actually a barrel shifter).  So handle this edge case,
update the corresponding AV bit in ASTAT which was missing previously,
and tweak the AZ setting based on how the hardware behaves.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 20:59:54 +00:00
Mike Frysinger
99dcc4dc65 sim: bfin: handle odd shift values with shift insns
The shift magnitude is a 5-bit signed value.  When it is between 0 and
15, then we do the requested shift, but when it is outside of that, we
have to do the opposite.

That means we flip between lshift and ashiftrt to match the hardware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 20:59:24 +00:00
Mike Frysinger
a0a71a7f8b sim: bfin: fix M_IH saturation size
This reverts the previous commit and does it right.  This change got
lost in the shuffle of patches I have pending.

Basically the logic is to change the 32bit saturation (and then masked
to 16bits) to a proper 16bit saturation.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 20:10:57 +00:00
Mike Frysinger
388aa9fe20 sim: bfin: handle V/VS saturation in dsp mac insns
Some saturation cases with dsp mac insns were not setting the V flag.
So implement that part and split up the logic between the dual macs.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 20:04:32 +00:00
Mike Frysinger
f2a56d0ad7 sim: bfin: handle the MM flag in M_IU/M_TFU modes with dsp insns
Our handling of the M_IU/M_TFU modes are missing signed saturation when
the MM flag is set, so add it to match the hardware behavior.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 19:44:14 +00:00
Mike Frysinger
ef26d60eba sim: bfin: fix sign extension in dsp insns with MM flag
After testing the hardware with all the different dsp flags, the MM flag
triggers sign extension in all modes.  So drop the limited use of it, and
the local custom helper that was also extending unsigned values.  We also
can see that the flag checks in the mult/mac insns have the same behavior
with sign extending, so add a helper func to keep the logic the same in
both places.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 19:42:55 +00:00
Mike Frysinger
075a845a92 sim: bfin: fix dsp insns IH saturation/rounding behavior
When using the IH modifier, we need to first saturate the value before
rounding it, and then further saturate it a bit more.  This makes the
sim match the hardware behavior with these insns.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 19:24:57 +00:00
Mike Frysinger
b02cc5b9df sim: bfin: fix inverted changelog entry 2011-06-18 18:09:35 +00:00
Mike Frysinger
73aae8efb2 sim: bfin: fix accumulator edge case saturation
When the accumulator saturates, it needs to be greater than, but not
equal to, the largest unsigned value as this is what the hardware does.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 17:27:01 +00:00
Mike Frysinger
886ea33b69 sim: bfin: use freeargv for freeing argvs
Since the argv array was allocated with dupargv, it needs to be freed
with freeargv to avoid leaks.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 17:20:38 +00:00
Mike Frysinger
eb3243445a sim: bfin: add support for glued SIC interrupt lines
The BF537 family glues a bunch of peripherals into single interrupt lines
that run into the SIC.  To model this same behavior in the sim, we need to
use the glue-or device, and in order to use that, we need to tweak things
a bit in the mach code to allow declaring of these new devices.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-04 17:18:04 +00:00
Mike Frysinger
082e1c4a87 sim: bfin: push SIC mappings to device tree
The machs.c file is the best place for holding cpu-specific details, so
restructure the way the SIC manages its ports to do just that.  Now the
SIC's have a standard set of input pins and the different line routing
from peripherals is kept in the device tree only.  This better models
the hardware where the SIC doesn't care about the exact peripheral that
is sending it stuff, just which input pin it gets it on.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-04 17:11:19 +00:00
Mike Frysinger
36f3e98103 sim: bfin: dma: fix indentation 2011-06-03 05:03:31 +00:00
Mike Frysinger
ea1f7d4c8e sim: bfin: switch to new syscall trace level
Now that the common code supports the syscall trace level, change the
Blackfin code from using the event level to the syscall level.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-26 00:14:43 +00:00
Mike Frysinger
f2db709f4f sim: bfin: move model data into machs.h
Pull the model data (register addresses/sizes) out of the different model
files and into the machs.h header.  The models themselves don't care about
where they're mapped, only the mach code does.  This allows us to keep the
model headers from being included in the mach code which can cause issues
with model-specific names colliding.  Such as when a newer device model is
created, but with incompatible register names/layouts.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-25 12:54:19 +00:00
Mike Frysinger
c43aadcaa6 sim: bfin: add a performance monitor stub
No counters get updated, but there is enough here for software to
poke things and work.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-25 12:41:29 +00:00
Mike Frysinger
dfb61fb66f sim: bfin: add bf526-0.2/bf54x-0.4 rom regions
Add regions for the on-chip roms on some newer Blackfin parts.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-25 12:35:05 +00:00
Mike Frysinger
efac2223c4 sim: bfin: allow pushing of SP
The hardware respects this insn, and some code (like the on-chip bootrom)
uses it, so allow it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-14 16:00:37 +00:00
Mike Frysinger
28fe96b798 sim: bfin: implement loop back support in the UARTs
The UART has a LOOP_ENA bit in its MCR register where writes to the THR
go to the RBR.  Implement support for this mode.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-14 15:59:09 +00:00
Mike Frysinger
b44f3f638e sim: bfin: fix UART LSR read-only bit saturation
A few bits in the newer UART LSR register are not sticky, so make sure
we clear them when returning updated status rather than leaving them
always set.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-09 18:14:01 +00:00
Mike Frysinger
2613074f8f sim: bfin: constify dmac pmap arrays
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-27 21:29:03 +00:00
Mike Frysinger
054c055baf sim: gpio: add output support
Make all of the pins bidirectional, and support sending signals when
software drives the pins as outputs.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-26 05:47:14 +00:00
Mike Frysinger
5e0ba1a39e sim: gpio: update mask a/b signals better
When the mask a/b MMRs are written, the output signal might change levels
(as pins are [un]masked), so make sure we update the output level.

Further, make sure we handle edge ints correctly by first sending a high
signal followed by a low signal.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-26 05:46:02 +00:00
Mike Frysinger
0427acfba0 sim: bfin: use store buffer with more 32bit insns
A bunch of 32bit insns were not using the store buffer, so when they were
used in parallel insns, they would incorrectly clobber a register early.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-16 17:37:55 +00:00
Mike Frysinger
d2cfa400a1 sim: bfin: handle implicit DISALGNEXCPT with video insns
When most video related insns are used in parallel with Ireg loads, the
DISALGNEXCPT insn behavior is implicitly in effect.

Reported-by: Anton Shokurov <shokurov.anton.v@yandex.ru>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-15 01:21:21 +00:00
Mike Frysinger
e10d6db33d sim: bfin: respect the port level on signals to the SIC
The SIC latches ints from peripherals to the CEC, but the peripherals
need to be able to tell the SIC when to stop.  So use the incoming level
to figure out when to set the int bits and when to clear it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11 05:23:26 +00:00
Mike Frysinger
8aacdaf48d sim: bfin: add missing GPIO pin 15
Each GPIO block has 16 pins, and I only added 15 in the original
port list.  So add the missing 16th.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11 05:22:23 +00:00
Mike Frysinger
2b12772f43 sim: bfin: add OTP output port
This doesn't currently generate any interrupts (as there doesn't appear
to be any documentation to *when* it would even do so), but since the
HRM does say an interrupt line exists between the OTP and the SIC, add
one for completeness sake.  This will make a follow up patch easier.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-01 22:32:04 +00:00
Mike Frysinger
6294f8ea1e sim: bfin: regen configure to include new cfi device 2011-03-29 18:39:51 +00:00
Mike Frysinger
1a3af0bfc3 sim: bfin: fix sign extension with 16bit acc add insns
The current implementation attempts to handle the 16bit sign extension
itself.  Unfortunately, it gets it right in some cases.  So rather than
fix that logic, just drop it in favor of using 16bit signed casts.  Now
gcc will take care of getting the logic right.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-29 01:41:49 +00:00
Mike Frysinger
36aef94270 sim: bfin: handle saturation with RND12 sub insns
The current handling of the subtraction insn with the RND12 modifier
works when saturation isn't involved.  So add handling for this edge
case to match the hardware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-27 04:03:05 +00:00
Mike Frysinger
fcd1ee07d3 sim: bfin: add missing VS set with add/sub insns
The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the
V bit was also set.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-26 06:02:41 +00:00
Mike Frysinger
a31d4fd99d sim: bfin: add hw tracing to gpio/sic port events
Makes it a lot easier to find out what's going on with interrupt lines
if the ports have tracing output.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25 00:13:57 +00:00
Mike Frysinger
b72cc8e145 sim: bfin: fix GPIO logic bugs when processing events
We need the DIR bit cleared, not set, in order for the pin to be treated
as an input.

When looking up the data value, we need to shift the "level" value over by
"my_port" rather than "bit" as the latter has already been shifted over.
We also should normalize the "level" coming in from the outside worlds to
the set of {0,1} since those are the only values that matter to GPIOs.

We need the BOTH bit set, not cleared, in order for the pin to trigger
on both edges.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25 00:13:23 +00:00
Mike Frysinger
eaf863cd1e sim: bfin: fix clear/set/toggle GPIO handling
The clear/set/toggle MMRs aren't backed by "real" data; they implicitly
perform bit operations on the associated data register.  So when we go
to process writes to them, we need to adjust the pointer accordingly so
that the actual backing data is modified.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25 00:12:47 +00:00
Mike Frysinger
b16a1f4c4f sim: bfin: document SIC limitation
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:18:17 +00:00
Mike Frysinger
9922f80319 sim: bfin: fix inverted W1C logic
When I originally wrote the w1c helper funcs, I used it in a few places.
Then I forgot how it worked and when I later documented it, I described
the 3rd arg in the exact opposite way it is actually used.  This error
propagated to a bunch of devices registers that were not explicitly
tested (a bunch of the devices are stubs which merely exist to say "no
device is connected" to make device drivers happy).

So once the documentation is unscrewed, fix all of the broken call sites.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:17:14 +00:00