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old-cross-binutils/sim/bfin
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Mike Frysinger f2db709f4f sim: bfin: move model data into machs.h 
Pull the model data (register addresses/sizes) out of the different model
files and into the machs.h header.  The models themselves don't care about
where they're mapped, only the mach code does.  This allows us to keep the
model headers from being included in the mach code which can cause issues
with model-specific names colliding.  Such as when a newer device model is
created, but with incompatible register names/layouts.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-25 12:54:19 +00:00
..
bfroms sim: bfin: add bf526-0.2/bf54x-0.4 rom regions 2011-05-25 12:35:05 +00:00
aclocal.m4
bfin-sim.c sim: bfin: allow pushing of SP 2011-05-14 16:00:37 +00:00
bfin-sim.h
ChangeLog sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
config.in sim: bfin: check for kill/pread 2011-03-17 19:03:30 +00:00
configure sim: bfin: add a performance monitor stub 2011-05-25 12:41:29 +00:00
configure.ac sim: bfin: add a performance monitor stub 2011-05-25 12:41:29 +00:00
devices.c
devices.h sim: bfin: fix inverted W1C logic 2011-03-24 03:17:14 +00:00
dv-bfin_cec.c sim: bfin: fix inverted W1C logic 2011-03-24 03:17:14 +00:00
dv-bfin_cec.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_ctimer.c sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
dv-bfin_ctimer.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_dma.c sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
dv-bfin_dma.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_dmac.c sim: bfin: constify dmac pmap arrays 2011-04-27 21:29:03 +00:00
dv-bfin_dmac.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_ebiu_amc.c sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
dv-bfin_ebiu_amc.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_ebiu_ddrc.c sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
dv-bfin_ebiu_ddrc.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_ebiu_sdc.c sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
dv-bfin_ebiu_sdc.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_emac.c sim: bfin: fix inverted W1C logic 2011-03-24 03:17:14 +00:00
dv-bfin_emac.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_eppi.c sim: bfin: fix inverted W1C logic 2011-03-24 03:17:14 +00:00
dv-bfin_eppi.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_evt.c sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
dv-bfin_evt.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_gpio.c sim: gpio: add output support 2011-04-26 05:47:14 +00:00
dv-bfin_gpio.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_gptimer.c sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
dv-bfin_gptimer.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_jtag.c sim: bfin: fix inverted W1C logic 2011-03-24 03:17:14 +00:00
dv-bfin_jtag.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_mmu.c sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
dv-bfin_mmu.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_nfc.c sim: bfin: fix inverted W1C logic 2011-03-24 03:17:14 +00:00
dv-bfin_nfc.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_otp.c sim: bfin: add OTP output port 2011-04-01 22:32:04 +00:00
dv-bfin_otp.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_pfmon.c sim: bfin: add a performance monitor stub 2011-05-25 12:41:29 +00:00
dv-bfin_pfmon.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_pll.c sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
dv-bfin_pll.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_ppi.c sim: bfin: fix inverted W1C logic 2011-03-24 03:17:14 +00:00
dv-bfin_ppi.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_rtc.c sim: bfin: fix inverted W1C logic 2011-03-24 03:17:14 +00:00
dv-bfin_rtc.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_sic.c sim: bfin: respect the port level on signals to the SIC 2011-04-11 05:23:26 +00:00
dv-bfin_sic.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_spi.c sim: bfin: fix inverted W1C logic 2011-03-24 03:17:14 +00:00
dv-bfin_spi.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_trace.c sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
dv-bfin_trace.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_twi.c sim: bfin: fix inverted W1C logic 2011-03-24 03:17:14 +00:00
dv-bfin_twi.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_uart.c sim: bfin: implement loop back support in the UARTs 2011-05-14 15:59:09 +00:00
dv-bfin_uart.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_uart2.c sim: bfin: implement loop back support in the UARTs 2011-05-14 15:59:09 +00:00
dv-bfin_uart2.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_wdog.c sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
dv-bfin_wdog.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-bfin_wp.c sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
dv-bfin_wp.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
dv-eth_phy.c sim: bfin: fix brace style 2011-03-15 20:55:11 +00:00
gui.c sim: bfin: fix brace style 2011-03-15 20:44:11 +00:00
gui.h
insn_list.def
interp.c sim: bfin: check for kill/pread 2011-03-17 19:03:30 +00:00
linux-fixed-code.h sim: bfin: fix brace style 2011-03-15 20:44:11 +00:00
linux-fixed-code.s
linux-targ-map.h sim: bfin: fix brace style 2011-03-15 20:44:11 +00:00
machs.c sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
machs.h sim: bfin: move model data into machs.h 2011-05-25 12:54:19 +00:00
Makefile.in sim: bfin: add a performance monitor stub 2011-05-25 12:41:29 +00:00
proc_list.def
sim-main.h
tconfig.in
TODO sim: bfin: document SIC limitation 2011-03-24 03:18:17 +00:00