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sim: bfin: fix UART LSR read-only bit saturation

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A few bits in the newer UART LSR register are not sticky, so make sure
we clear them when returning updated status rather than leaving them
always set.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2011-05-09 18:14:01 +00:00
parent 91c1f14cb6
commit b44f3f638e
2 changed files with 6 additions and 0 deletions
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5
sim/bfin/ChangeLog
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@ -1,3 +1,8 @@
2011-05-09 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_uart2.c (bfin_uart_io_read_buffer): Clear DR/THRE/TEMT bits
from uart->lsr before setting them.
2011-04-27 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_dmac.c (bfin_dmac): Constify pmap array.

1
sim/bfin/dv-bfin_uart2.c
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@ -151,6 +151,7 @@ bfin_uart_io_read_buffer (struct hw *me, void *dest,
bfin_uart_reschedule (me);
break;
case mmr_offset(lsr):
uart->lsr &= ~(DR | THRE | TEMT);
uart->lsr |= bfin_uart_get_status (me);
case mmr_offset(thr):
case mmr_offset(msr):