1999-05-03 07:29:11 +00:00
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/* tc-i386.h -- Header file for tc-i386.c
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2001-03-08 23:24:26 +00:00
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Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
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2004-03-12 10:14:29 +00:00
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2001, 2002, 2003, 2004
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2001-03-08 23:24:26 +00:00
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Free Software Foundation, Inc.
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1999-05-03 07:29:11 +00:00
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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2005-05-05 09:13:19 +00:00
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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1999-05-03 07:29:11 +00:00
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#ifndef TC_I386
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#define TC_I386 1
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2003-08-14 08:05:44 +00:00
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#ifndef BFD_ASSEMBLER
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#error So, do you know what you are doing?
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#endif
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1999-05-03 07:29:11 +00:00
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struct fix;
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#define TARGET_BYTES_BIG_ENDIAN 0
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#define TARGET_ARCH bfd_arch_i386
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2001-01-13 23:37:57 +00:00
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#define TARGET_MACH (i386_mach ())
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2004-10-01 08:38:35 +00:00
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extern unsigned long i386_mach (void);
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1999-05-03 07:29:11 +00:00
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2001-02-19 06:40:29 +00:00
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#ifdef TE_FreeBSD
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#define AOUT_TARGET_FORMAT "a.out-i386-freebsd"
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#endif
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1999-05-03 07:29:11 +00:00
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#ifdef TE_NetBSD
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2000-01-26 22:48:31 +00:00
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#define AOUT_TARGET_FORMAT "a.out-i386-netbsd"
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1999-05-03 07:29:11 +00:00
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#endif
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#ifdef TE_386BSD
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2000-01-26 22:48:31 +00:00
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#define AOUT_TARGET_FORMAT "a.out-i386-bsd"
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1999-05-03 07:29:11 +00:00
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#endif
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#ifdef TE_LINUX
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2000-01-26 22:48:31 +00:00
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#define AOUT_TARGET_FORMAT "a.out-i386-linux"
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1999-05-03 07:29:11 +00:00
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#endif
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#ifdef TE_Mach
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2000-01-26 22:48:31 +00:00
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#define AOUT_TARGET_FORMAT "a.out-mach3"
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1999-05-03 07:29:11 +00:00
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#endif
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#ifdef TE_DYNIX
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2000-01-26 22:48:31 +00:00
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#define AOUT_TARGET_FORMAT "a.out-i386-dynix"
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1999-05-03 07:29:11 +00:00
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#endif
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2000-01-26 22:48:31 +00:00
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#ifndef AOUT_TARGET_FORMAT
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#define AOUT_TARGET_FORMAT "a.out-i386"
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1999-05-03 07:29:11 +00:00
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#endif
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2002-09-17 02:24:40 +00:00
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#ifdef TE_FreeBSD
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#define ELF_TARGET_FORMAT "elf32-i386-freebsd"
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2005-05-05 14:37:27 +00:00
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#elif defined (TE_VXWORKS)
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#define ELF_TARGET_FORMAT "elf32-i386-vxworks"
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2002-09-17 02:24:40 +00:00
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#endif
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2005-05-05 14:37:27 +00:00
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2002-09-17 02:24:40 +00:00
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#ifndef ELF_TARGET_FORMAT
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#define ELF_TARGET_FORMAT "elf32-i386"
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#endif
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* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
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#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
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|| defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
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2000-01-26 22:48:31 +00:00
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extern const char *i386_target_format PARAMS ((void));
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#define TARGET_FORMAT i386_target_format ()
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#else
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1999-05-03 07:29:11 +00:00
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#ifdef OBJ_ELF
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2002-09-17 02:24:40 +00:00
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#define TARGET_FORMAT ELF_TARGET_FORMAT
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1999-05-03 07:29:11 +00:00
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#endif
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2000-01-26 22:48:31 +00:00
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#ifdef OBJ_AOUT
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#define TARGET_FORMAT AOUT_TARGET_FORMAT
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1999-05-03 07:29:11 +00:00
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#endif
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#endif
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2001-11-15 13:19:46 +00:00
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#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
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#define md_end i386_elf_emit_arch_note
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extern void i386_elf_emit_arch_note PARAMS ((void));
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#endif
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2002-05-23 08:08:48 +00:00
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#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
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2002-08-09 12:37:41 +00:00
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#define LOCAL_LABELS_FB 1
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1999-05-03 07:29:11 +00:00
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extern const char extra_symbol_chars[];
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#define tc_symbol_chars extra_symbol_chars
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#define MAX_OPERANDS 3 /* max operands per insn */
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#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
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#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */
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/* Prefixes will be emitted in the order defined below.
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WAIT_PREFIX must be the first prefix since FWAIT is really is an
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2000-09-16 00:56:47 +00:00
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instruction, and so must come before any prefixes. */
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1999-05-03 07:29:11 +00:00
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#define WAIT_PREFIX 0
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#define LOCKREP_PREFIX 1
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#define ADDR_PREFIX 2
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#define DATA_PREFIX 3
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#define SEG_PREFIX 4
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* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
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#define REX_PREFIX 5 /* must come last. */
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#define MAX_PREFIXES 6 /* max prefixes per opcode */
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1999-05-03 07:29:11 +00:00
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/* we define the syntax here (modulo base,index,scale syntax) */
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#define REGISTER_PREFIX '%'
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#define IMMEDIATE_PREFIX '$'
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#define ABSOLUTE_PREFIX '*'
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#define TWO_BYTE_OPCODE_ESCAPE 0x0f
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#define NOP_OPCODE (char) 0x90
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/* register numbers */
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#define EBP_REG_NUM 5
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#define ESP_REG_NUM 4
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/* modrm_byte.regmem for twobyte escape */
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#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
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/* index_base_byte.index for no index register addressing */
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#define NO_INDEX_REGISTER ESP_REG_NUM
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/* index_base_byte.base for no base register addressing */
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#define NO_BASE_REGISTER EBP_REG_NUM
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#define NO_BASE_REGISTER_16 6
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/* these are the instruction mnemonic suffixes. */
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#define WORD_MNEM_SUFFIX 'w'
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#define BYTE_MNEM_SUFFIX 'b'
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#define SHORT_MNEM_SUFFIX 's'
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#define LONG_MNEM_SUFFIX 'l'
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* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
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#define QWORD_MNEM_SUFFIX 'q'
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1999-05-03 07:29:11 +00:00
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/* Intel Syntax */
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#define LONG_DOUBLE_MNEM_SUFFIX 'x'
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/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
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#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
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#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
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#define END_OF_INSN '\0'
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typedef struct
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{
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/* instruction name sans width suffix ("mov" for movl insns) */
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char *name;
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/* how many operands */
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unsigned int operands;
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/* base_opcode is the fundamental opcode byte without optional
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prefix(es). */
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unsigned int base_opcode;
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/* extension_opcode is the 3 bit extension for group <n> insns.
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This field is also used to store the 8-bit opcode suffix for the
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AMD 3DNow! instructions.
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If this template has no extension opcode (the usual case) use None */
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unsigned int extension_opcode;
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2000-09-16 00:56:47 +00:00
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#define None 0xffff /* If no extension_opcode is possible. */
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1999-05-03 07:29:11 +00:00
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2000-05-13 09:26:23 +00:00
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/* cpu feature flags */
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unsigned int cpu_flags;
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#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */
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#define Cpu186 0x2 /* i186 or better required */
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#define Cpu286 0x4 /* i286 or better required */
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#define Cpu386 0x8 /* i386 or better required */
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#define Cpu486 0x10 /* i486 or better required */
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#define Cpu586 0x20 /* i585 or better required */
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#define Cpu686 0x40 /* i686 or better required */
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2001-01-03 15:36:26 +00:00
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#define CpuP4 0x80 /* Pentium4 or better required */
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#define CpuK6 0x100 /* AMD K6 or better required*/
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#define CpuAthlon 0x200 /* AMD Athlon or better required*/
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#define CpuSledgehammer 0x400 /* Sledgehammer or better required */
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#define CpuMMX 0x800 /* MMX support required */
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2004-11-23 07:55:12 +00:00
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#define CpuMMX2 0x1000 /* extended MMX support (with SSE or 3DNow!Ext) required */
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#define CpuSSE 0x2000 /* Streaming SIMD extensions required */
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#define CpuSSE2 0x4000 /* Streaming SIMD extensions 2 required */
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|
|
#define Cpu3dnow 0x8000 /* 3dnow! support required */
|
|
|
|
#define Cpu3dnowA 0x10000 /* 3dnow!Extensions support required */
|
2005-07-06 19:11:01 +00:00
|
|
|
#define CpuSSE3 0x20000 /* Streaming SIMD extensions 3 required */
|
|
|
|
#define CpuPNI CpuSSE3 /* Prescott New Instructions required */
|
2004-11-23 07:55:12 +00:00
|
|
|
#define CpuPadLock 0x40000 /* VIA PadLock required */
|
2005-07-05 07:16:54 +00:00
|
|
|
#define CpuSVME 0x80000 /* AMD Secure Virtual Machine Ext-s required */
|
2005-07-15 13:49:53 +00:00
|
|
|
#define CpuVMX 0x100000 /* VMX Instructions required */
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
|
|
|
|
|
|
|
/* These flags are set by gas depending on the flag_code. */
|
|
|
|
#define Cpu64 0x4000000 /* 64bit support required */
|
|
|
|
#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
|
|
|
|
|
|
|
|
/* The default value for unknown CPUs - enable all features to avoid problems. */
|
2005-07-05 07:16:54 +00:00
|
|
|
#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
|
2005-07-15 13:49:53 +00:00
|
|
|
|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
|
2005-07-05 07:16:54 +00:00
|
|
|
|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME)
|
2000-05-13 09:26:23 +00:00
|
|
|
|
1999-05-03 07:29:11 +00:00
|
|
|
/* the bits in opcode_modifier are used to generate the final opcode from
|
|
|
|
the base_opcode. These bits also are used to detect alternate forms of
|
|
|
|
the same instruction */
|
|
|
|
unsigned int opcode_modifier;
|
|
|
|
|
|
|
|
/* opcode_modifier bits: */
|
|
|
|
#define W 0x1 /* set if operands can be words or dwords
|
|
|
|
encoded the canonical way */
|
|
|
|
#define D 0x2 /* D = 0 if Reg --> Regmem;
|
|
|
|
D = 1 if Regmem --> Reg: MUST BE 0x2 */
|
|
|
|
#define Modrm 0x4
|
|
|
|
#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
|
|
|
|
#define ShortForm 0x10 /* register is in low 3 bits of opcode */
|
|
|
|
#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
|
2000-09-16 00:56:47 +00:00
|
|
|
#define Jump 0x40 /* special case for jump insns. */
|
1999-05-03 07:29:11 +00:00
|
|
|
#define JumpDword 0x80 /* call and jump */
|
|
|
|
#define JumpByte 0x100 /* loop and jecxz */
|
|
|
|
#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
|
|
|
|
#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
|
|
|
|
#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
|
2000-09-16 00:56:47 +00:00
|
|
|
#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
|
1999-05-03 07:29:11 +00:00
|
|
|
#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
|
|
|
|
#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
|
|
|
#define Size64 0x8000 /* needs size prefix if in 16-bit mode */
|
|
|
|
#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
|
|
|
|
#define DefaultSize 0x20000 /* default insn size depends on mode */
|
|
|
|
#define No_bSuf 0x40000 /* b suffix on instruction illegal */
|
|
|
|
#define No_wSuf 0x80000 /* w suffix on instruction illegal */
|
|
|
|
#define No_lSuf 0x100000 /* l suffix on instruction illegal */
|
|
|
|
#define No_sSuf 0x200000 /* s suffix on instruction illegal */
|
|
|
|
#define No_qSuf 0x400000 /* q suffix on instruction illegal */
|
|
|
|
#define No_xSuf 0x800000 /* x suffix on instruction illegal */
|
|
|
|
#define FWait 0x1000000 /* instruction needs FWAIT */
|
|
|
|
#define IsString 0x2000000 /* quick test for string instructions */
|
|
|
|
#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
|
|
|
|
#define IsPrefix 0x8000000 /* opcode is a prefix */
|
|
|
|
#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
|
|
|
|
#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
|
|
|
|
#define Rex64 0x40000000 /* instruction require Rex64 prefix. */
|
|
|
|
#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
|
1999-05-03 07:29:11 +00:00
|
|
|
|
|
|
|
/* operand_types[i] describes the type of operand i. This is made
|
|
|
|
by OR'ing together all of the possible type masks. (e.g.
|
|
|
|
'operand_types[i] = Reg|Imm' specifies that operand i can be
|
2000-05-13 09:26:23 +00:00
|
|
|
either a register or an immediate operand. */
|
1999-05-03 07:29:11 +00:00
|
|
|
unsigned int operand_types[3];
|
2000-05-13 09:26:23 +00:00
|
|
|
|
|
|
|
/* operand_types[i] bits */
|
|
|
|
/* register */
|
|
|
|
#define Reg8 0x1 /* 8 bit reg */
|
|
|
|
#define Reg16 0x2 /* 16 bit reg */
|
|
|
|
#define Reg32 0x4 /* 32 bit reg */
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
|
|
|
#define Reg64 0x8 /* 64 bit reg */
|
2000-05-13 09:26:23 +00:00
|
|
|
/* immediate */
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
|
|
|
#define Imm8 0x10 /* 8 bit immediate */
|
|
|
|
#define Imm8S 0x20 /* 8 bit immediate sign extended */
|
|
|
|
#define Imm16 0x40 /* 16 bit immediate */
|
|
|
|
#define Imm32 0x80 /* 32 bit immediate */
|
|
|
|
#define Imm32S 0x100 /* 32 bit immediate sign extended */
|
|
|
|
#define Imm64 0x200 /* 64 bit immediate */
|
|
|
|
#define Imm1 0x400 /* 1 bit immediate */
|
2000-05-13 09:26:23 +00:00
|
|
|
/* memory */
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
|
|
|
#define BaseIndex 0x800
|
2000-05-13 09:26:23 +00:00
|
|
|
/* Disp8,16,32 are used in different ways, depending on the
|
|
|
|
instruction. For jumps, they specify the size of the PC relative
|
|
|
|
displacement, for baseindex type instructions, they specify the
|
|
|
|
size of the offset relative to the base register, and for memory
|
|
|
|
offset instructions such as `mov 1234,%al' they specify the size of
|
|
|
|
the offset relative to the segment base. */
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
|
|
|
#define Disp8 0x1000 /* 8 bit displacement */
|
|
|
|
#define Disp16 0x2000 /* 16 bit displacement */
|
|
|
|
#define Disp32 0x4000 /* 32 bit displacement */
|
|
|
|
#define Disp32S 0x8000 /* 32 bit signed displacement */
|
|
|
|
#define Disp64 0x10000 /* 64 bit displacement */
|
2000-05-13 09:26:23 +00:00
|
|
|
/* specials */
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
|
|
|
#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
|
|
|
|
#define ShiftCount 0x40000 /* register to hold shift cound = cl */
|
|
|
|
#define Control 0x80000 /* Control register */
|
|
|
|
#define Debug 0x100000 /* Debug register */
|
|
|
|
#define Test 0x200000 /* Test register */
|
|
|
|
#define FloatReg 0x400000 /* Float register */
|
|
|
|
#define FloatAcc 0x800000 /* Float stack top %st(0) */
|
|
|
|
#define SReg2 0x1000000 /* 2 bit segment register */
|
|
|
|
#define SReg3 0x2000000 /* 3 bit segment register */
|
|
|
|
#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
|
|
|
|
#define JumpAbsolute 0x8000000
|
|
|
|
#define RegMMX 0x10000000 /* MMX register */
|
|
|
|
#define RegXMM 0x20000000 /* XMM registers in PIII */
|
|
|
|
#define EsSeg 0x40000000 /* String insn operand with fixed es segment */
|
|
|
|
|
2000-05-13 09:26:23 +00:00
|
|
|
/* InvMem is for instructions with a modrm byte that only allow a
|
|
|
|
general register encoding in the i.tm.mode and i.tm.regmem fields,
|
|
|
|
eg. control reg moves. They really ought to support a memory form,
|
|
|
|
but don't, so we add an InvMem flag to the register operand to
|
|
|
|
indicate that it should be encoded in the i.tm.regmem field. */
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
|
|
|
#define InvMem 0x80000000
|
2000-05-13 09:26:23 +00:00
|
|
|
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
|
|
|
#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
|
|
|
|
#define WordReg (Reg16|Reg32|Reg64)
|
2000-05-13 09:26:23 +00:00
|
|
|
#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
|
|
|
#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
|
|
|
|
#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
|
|
|
|
#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
|
|
|
|
#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
|
2000-05-13 09:26:23 +00:00
|
|
|
/* The following aliases are defined because the opcode table
|
|
|
|
carefully specifies the allowed memory types for each instruction.
|
|
|
|
At the moment we can only tell a memory reference size by the
|
|
|
|
instruction suffix, so there's not much point in defining Mem8,
|
|
|
|
Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
|
|
|
|
the suffix directly to check memory operands. */
|
|
|
|
#define LLongMem AnyMem /* 64 bits (or more) */
|
|
|
|
#define LongMem AnyMem /* 32 bit memory ref */
|
|
|
|
#define ShortMem AnyMem /* 16 bit memory ref */
|
|
|
|
#define WordMem AnyMem /* 16 or 32 bit memory ref */
|
|
|
|
#define ByteMem AnyMem /* 8 bit memory ref */
|
1999-05-03 07:29:11 +00:00
|
|
|
}
|
|
|
|
template;
|
|
|
|
|
|
|
|
/*
|
|
|
|
'templates' is for grouping together 'template' structures for opcodes
|
|
|
|
of the same name. This is only used for storing the insns in the grand
|
|
|
|
ole hash table of insns.
|
|
|
|
The templates themselves start at START and range up to (but not including)
|
|
|
|
END.
|
|
|
|
*/
|
|
|
|
typedef struct
|
2000-05-13 09:26:23 +00:00
|
|
|
{
|
|
|
|
const template *start;
|
|
|
|
const template *end;
|
|
|
|
}
|
|
|
|
templates;
|
1999-05-03 07:29:11 +00:00
|
|
|
|
|
|
|
/* these are for register name --> number & type hash lookup */
|
|
|
|
typedef struct
|
2000-05-13 09:26:23 +00:00
|
|
|
{
|
|
|
|
char *reg_name;
|
|
|
|
unsigned int reg_type;
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
|
|
|
unsigned int reg_flags;
|
|
|
|
#define RegRex 0x1 /* Extended register. */
|
|
|
|
#define RegRex64 0x2 /* Extended 8 bit register. */
|
2000-05-13 09:26:23 +00:00
|
|
|
unsigned int reg_num;
|
|
|
|
}
|
1999-05-03 07:29:11 +00:00
|
|
|
reg_entry;
|
|
|
|
|
|
|
|
typedef struct
|
2000-05-13 09:26:23 +00:00
|
|
|
{
|
|
|
|
char *seg_name;
|
|
|
|
unsigned int seg_prefix;
|
|
|
|
}
|
1999-05-03 07:29:11 +00:00
|
|
|
seg_entry;
|
|
|
|
|
2000-09-16 00:56:47 +00:00
|
|
|
/* 386 operand encoding bytes: see 386 book for details of this. */
|
1999-05-03 07:29:11 +00:00
|
|
|
typedef struct
|
2000-05-13 09:26:23 +00:00
|
|
|
{
|
|
|
|
unsigned int regmem; /* codes register or memory operand */
|
|
|
|
unsigned int reg; /* codes register operand (or extended opcode) */
|
|
|
|
unsigned int mode; /* how to interpret regmem & reg */
|
|
|
|
}
|
1999-05-03 07:29:11 +00:00
|
|
|
modrm_byte;
|
|
|
|
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
|
|
|
/* x86-64 extension prefix. */
|
2002-03-09 05:36:51 +00:00
|
|
|
typedef int rex_byte;
|
|
|
|
#define REX_OPCODE 0x40
|
|
|
|
|
|
|
|
/* Indicates 64 bit operand size. */
|
|
|
|
#define REX_MODE64 8
|
|
|
|
/* High extension to reg field of modrm byte. */
|
|
|
|
#define REX_EXTX 4
|
|
|
|
/* High extension to SIB index field. */
|
|
|
|
#define REX_EXTY 2
|
|
|
|
/* High extension to base field of modrm or SIB, or reg field of opcode. */
|
|
|
|
#define REX_EXTZ 1
|
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
|
|
|
|
2000-09-16 00:56:47 +00:00
|
|
|
/* 386 opcode byte to code indirect addressing. */
|
1999-05-03 07:29:11 +00:00
|
|
|
typedef struct
|
2000-05-13 09:26:23 +00:00
|
|
|
{
|
|
|
|
unsigned base;
|
|
|
|
unsigned index;
|
|
|
|
unsigned scale;
|
|
|
|
}
|
1999-05-03 07:29:11 +00:00
|
|
|
sib_byte;
|
|
|
|
|
2000-05-13 09:26:23 +00:00
|
|
|
/* x86 arch names and features */
|
|
|
|
typedef struct
|
|
|
|
{
|
|
|
|
const char *name; /* arch name */
|
|
|
|
unsigned int flags; /* cpu feature flags */
|
|
|
|
}
|
|
|
|
arch_entry;
|
|
|
|
|
1999-05-03 07:29:11 +00:00
|
|
|
/* The name of the global offset table generated by the compiler. Allow
|
2000-09-16 00:56:47 +00:00
|
|
|
this to be overridden if need be. */
|
1999-05-03 07:29:11 +00:00
|
|
|
#ifndef GLOBAL_OFFSET_TABLE_NAME
|
|
|
|
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
|
|
|
|
#endif
|
|
|
|
|
2005-07-18 15:24:41 +00:00
|
|
|
#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT)
|
2002-08-09 12:37:41 +00:00
|
|
|
#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
|
|
|
|
extern void x86_cons PARAMS ((expressionS *, int));
|
|
|
|
|
|
|
|
#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
|
|
|
|
extern void x86_cons_fix_new
|
|
|
|
PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
|
2004-04-20 12:17:16 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef TE_PE
|
|
|
|
#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_pe_cons_fix_new(FRAG, OFF, LEN, EXP)
|
|
|
|
extern void x86_pe_cons_fix_new
|
|
|
|
PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
|
2002-08-09 12:37:41 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
|
|
|
|
|
|
|
|
#define NO_RELOC BFD_RELOC_NONE
|
|
|
|
|
1999-05-03 07:29:11 +00:00
|
|
|
void i386_validate_fix PARAMS ((struct fix *));
|
2002-09-05 00:01:18 +00:00
|
|
|
#define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
|
2002-08-09 12:37:41 +00:00
|
|
|
|
|
|
|
#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
|
|
|
|
extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
|
|
|
|
|
gas:
* cgen.c, cgen.h, tc.h, write.c, config/obj-coff.c
* config/tc-a29k.c, config/tc-alpha.c, config/tc-alpha.h
* config/tc-arc.c, config/tc-arc.h, config/tc-arm.c
* config/tc-arm.h, config/tc-avr.c, config/tc-avr.h
* config/tc-cris.c, config/tc-crx.c, config/tc-d10v.c
* config/tc-d10v.h, config/tc-d30v.c, config/tc-d30v.h
* config/tc-dlx.c, config/tc-dlx.h, config/tc-fr30.h
* config/tc-frv.c, config/tc-frv.h, config/tc-h8300.c
* config/tc-h8500.c, config/tc-hppa.c, config/tc-hppa.h
* config/tc-i370.c, config/tc-i370.h, config/tc-i386.c
* config/tc-i386.h, config/tc-i860.c, config/tc-i860.h
* config/tc-i960.c, config/tc-i960.h, config/tc-ia64.c
* config/tc-ip2k.c, config/tc-ip2k.h, config/tc-iq2000.c
* config/tc-iq2000.h, config/tc-m32r.c, config/tc-m32r.h
* config/tc-m68hc11.c, config/tc-m68hc11.h, config/tc-m68k.c
* config/tc-m68k.h, config/tc-m88k.c, config/tc-maxq.c
* config/tc-mcore.c, config/tc-mcore.h, config/tc-mips.c
* config/tc-mips.h, config/tc-mmix.c, config/tc-mn10200.c
* config/tc-mn10300.c, config/tc-msp430.c, config/tc-ns32k.c
* config/tc-openrisc.h, config/tc-or32.c, config/tc-or32.h
* config/tc-pdp11.c, config/tc-pj.c, config/tc-pj.h
* config/tc-ppc.c, config/tc-ppc.h, config/tc-s390.c
* config/tc-s390.h, config/tc-sh64.c, config/tc-sh.c
* config/tc-sh.h, config/tc-sparc.c, config/tc-sparc.h
* config/tc-tahoe.c, config/tc-tic30.c, config/tc-tic4x.c
* config/tc-tic54x.c, config/tc-tic80.c, config/tc-v850.c
* config/tc-v850.h, config/tc-vax.c, config/tc-vax.h
* config/tc-w65.c, config/tc-xstormy16.c, config/tc-xstormy16.h
* config/tc-xtensa.c, config/tc-z8k.c:
Replace all instances of the string "_apply_fix3" with
"_apply_fix".
* po/POTFILES.in, po/gas.pot: Regenerate.
bfd:
* coff-i386.c: Change md_apply_fix3 to md_apply_fix in comment.
cgen:
* doc/porting.texi: Change all mention of md_apply_fix3 and
gas_cgen_md_apply_fix3 to md_apply_fix and gas_cgen_md_apply_fix
respectively.
2005-06-07 17:54:22 +00:00
|
|
|
/* Values passed to md_apply_fix don't include the symbol value. */
|
2002-09-05 00:01:18 +00:00
|
|
|
#define MD_APPLY_SYM_VALUE(FIX) 0
|
2002-10-15 02:20:53 +00:00
|
|
|
|
|
|
|
/* ELF wants external syms kept, as does PE COFF. */
|
2003-01-23 12:51:05 +00:00
|
|
|
#if defined (TE_PE) && defined (STRICT_PE_FORMAT)
|
|
|
|
#define EXTERN_FORCE_RELOC \
|
2002-10-15 02:20:53 +00:00
|
|
|
(OUTPUT_FLAVOR == bfd_target_elf_flavour \
|
|
|
|
|| OUTPUT_FLAVOR == bfd_target_coff_flavour)
|
|
|
|
#else
|
|
|
|
#define EXTERN_FORCE_RELOC \
|
|
|
|
(OUTPUT_FLAVOR == bfd_target_elf_flavour)
|
1999-05-03 07:29:11 +00:00
|
|
|
#endif
|
|
|
|
|
2002-09-05 00:01:18 +00:00
|
|
|
/* This expression evaluates to true if the relocation is for a local
|
|
|
|
object for which we still want to do the relocation at runtime.
|
|
|
|
False if we are willing to perform this relocation while building
|
|
|
|
the .o file. GOTOFF does not need to be checked here because it is
|
|
|
|
not pcrel. I am not sure if some of the others are ever used with
|
2002-08-09 12:37:41 +00:00
|
|
|
pcrel, but it is easier to be safe than sorry. */
|
|
|
|
|
2002-09-05 00:01:18 +00:00
|
|
|
#define TC_FORCE_RELOCATION_LOCAL(FIX) \
|
|
|
|
(!(FIX)->fx_pcrel \
|
|
|
|
|| (FIX)->fx_plt \
|
|
|
|
|| (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \
|
|
|
|
|| (FIX)->fx_r_type == BFD_RELOC_386_GOT32 \
|
|
|
|
|| (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \
|
|
|
|
|| TC_FORCE_RELOCATION (FIX))
|
2002-08-09 12:37:41 +00:00
|
|
|
|
1999-05-03 07:29:11 +00:00
|
|
|
#define md_operand(x)
|
|
|
|
|
|
|
|
extern const struct relax_type md_relax_table[];
|
|
|
|
#define TC_GENERIC_RELAX_TABLE md_relax_table
|
|
|
|
|
2003-06-10 06:46:34 +00:00
|
|
|
extern int optimize_align_code;
|
|
|
|
|
1999-05-03 07:29:11 +00:00
|
|
|
#define md_do_align(n, fill, len, max, around) \
|
2003-06-10 06:46:34 +00:00
|
|
|
if ((n) \
|
|
|
|
&& !need_pass_2 \
|
|
|
|
&& optimize_align_code \
|
|
|
|
&& (!(fill) \
|
|
|
|
|| ((char)*(fill) == (char)0x90 && (len) == 1)) \
|
1999-06-12 16:49:51 +00:00
|
|
|
&& subseg_text_p (now_seg)) \
|
1999-05-03 07:29:11 +00:00
|
|
|
{ \
|
2000-12-28 10:07:56 +00:00
|
|
|
frag_align_code ((n), (max)); \
|
1999-05-03 07:29:11 +00:00
|
|
|
goto around; \
|
|
|
|
}
|
|
|
|
|
2000-12-28 10:07:56 +00:00
|
|
|
#define MAX_MEM_FOR_RS_ALIGN_CODE 15
|
|
|
|
|
1999-05-03 07:29:11 +00:00
|
|
|
extern void i386_align_code PARAMS ((fragS *, int));
|
|
|
|
|
|
|
|
#define HANDLE_ALIGN(fragP) \
|
|
|
|
if (fragP->fr_type == rs_align_code) \
|
|
|
|
i386_align_code (fragP, (fragP->fr_next->fr_address \
|
|
|
|
- fragP->fr_address \
|
|
|
|
- fragP->fr_fix));
|
|
|
|
|
|
|
|
void i386_print_statistics PARAMS ((FILE *));
|
|
|
|
#define tc_print_statistics i386_print_statistics
|
|
|
|
|
|
|
|
#define md_number_to_chars number_to_chars_littleendian
|
|
|
|
|
|
|
|
#ifdef SCO_ELF
|
|
|
|
#define tc_init_after_args() sco_id ()
|
|
|
|
extern void sco_id PARAMS ((void));
|
|
|
|
#endif
|
|
|
|
|
2003-05-20 07:58:07 +00:00
|
|
|
/* We want .cfi_* pseudo-ops for generating unwind info. */
|
2003-05-27 16:52:49 +00:00
|
|
|
#define TARGET_USE_CFIPOP 1
|
2003-05-20 07:58:07 +00:00
|
|
|
|
2003-05-27 16:52:49 +00:00
|
|
|
extern unsigned int x86_dwarf2_return_column;
|
|
|
|
#define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column
|
|
|
|
|
|
|
|
extern int x86_cie_data_alignment;
|
|
|
|
#define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
|
2003-05-20 07:58:07 +00:00
|
|
|
|
|
|
|
#define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
|
2003-05-27 16:52:49 +00:00
|
|
|
extern int tc_x86_regname_to_dw2regnum PARAMS ((const char *regname));
|
2003-05-20 07:58:07 +00:00
|
|
|
|
|
|
|
#define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
|
|
|
|
extern void tc_x86_frame_initial_instructions PARAMS ((void));
|
|
|
|
|
2004-10-08 13:55:11 +00:00
|
|
|
#define md_elf_section_type(str,len) i386_elf_section_type (str, len)
|
|
|
|
extern int i386_elf_section_type PARAMS ((const char *, size_t len));
|
|
|
|
|
2004-10-18 12:32:13 +00:00
|
|
|
#ifdef TE_PE
|
|
|
|
|
|
|
|
#define O_secrel O_md1
|
|
|
|
|
|
|
|
#define TC_DWARF2_EMIT_OFFSET tc_pe_dwarf2_emit_offset
|
|
|
|
void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
|
|
|
|
|
|
|
|
#endif /* TE_PE */
|
|
|
|
|
2002-08-09 12:37:41 +00:00
|
|
|
#endif /* TC_I386 */
|