030843d7f8
SWXC1MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1, MULT, MULTU, BEQZ, ...MTHI, MFHI instructions. Trace nullified instruction.
680 lines
15 KiB
Text
680 lines
15 KiB
Text
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// Integer Instructions
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// --------------------
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//
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// MulAcc is the Multiply Accumulator.
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// This register is mapped on the the HI and LO registers.
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// Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
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// Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
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:function:::unsigned64:MulAcc:
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{
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unsigned64 result = U8_4 (HI, LO);
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return result;
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}
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:function:::void:SET_MulAcc:unsigned64 value
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{
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*AL4_8 (&HI) = VH4_8 (value);
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*AL4_8 (&LO) = VL4_8 (value);
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}
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:function:::signed64:SignedMultiply:signed32 l, signed32 r
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{
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signed64 result = (signed64) l * (signed64) r;
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return result;
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}
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:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
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{
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unsigned64 result = (unsigned64) l * (unsigned64) r;
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return result;
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}
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:function:::unsigned64:Low32Bits:unsigned64 value
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{
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unsigned64 result = VL4_8 (value);
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return result;
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}
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:function:::unsigned64:High32Bits:unsigned64 value
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{
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unsigned64 result = VH4_8 (value);
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return result;
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}
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// Multiply and Move LO.
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000000,5.RS,5.RT,5.RD,00001,011000::::MUL
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"mul r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply and Move LO.
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000000,5.RS,5.RT,5.RD,00001,011001::::MULU
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"mulu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Multiply and Move HI.
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000000,5.RS,5.RT,5.RD,01001,011000::::MULHI
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"mulhi r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply and Move HI.
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000000,5.RS,5.RT,5.RD,01001,011001::::MULHIU
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"mulhiu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Negate and Move LO.
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000000,5.RS,5.RT,5.RD,00011,011000::::MULS
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"muls r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Negate and Move LO.
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000000,5.RS,5.RT,5.RD,00011,011001::::MULSU
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"mulsu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Negate and Move HI.
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000000,5.RS,5.RT,5.RD,01011,011000::::MULSHI
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"mulshi r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Negate and Move HI.
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000000,5.RS,5.RT,5.RD,01011,011001::::MULSHIU
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"mulshiu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Accumulate and Move LO.
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000000,5.RS,5.RT,5.RD,00101,011000::::MACC
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"macc r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Accumulate and Move LO.
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000000,5.RS,5.RT,5.RD,00101,011001::::MACCU
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"maccu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Accumulate and Move HI.
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000000,5.RS,5.RT,5.RD,01101,011000::::MACCHI
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"macchi r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Accumulate and Move HI.
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000000,5.RS,5.RT,5.RD,01101,011001::::MACCHIU
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"macchiu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Negate, Accumulate and Move LO.
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000000,5.RS,5.RT,5.RD,00111,011000::::MSAC
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"msac r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Negate, Accumulate and Move LO.
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000000,5.RS,5.RT,5.RD,00111,011001::::MSACU
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"msacu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Negate, Accumulate and Move HI.
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000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI
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"msachi r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Negate, Accumulate and Move HI.
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000000,5.RS,5.RT,5.RD,01111,011001::::MSACHIU
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"msachiu r<RD>, r<RS>, r<RT>"
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*vr5400:
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{
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SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Rotate Right.
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000000,00001,5.RT,5.RD,5.SHIFT,000010::::ROR
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"ror r<RD>, r<RT>, <SHIFT>"
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*vr5400:
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{
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int s = SHIFT;
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GPR[RD] = ROTR32 (GPR[RT], s);
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}
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// Rotate Right Variable.
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000000,5.RS,5.RT,5.RD,00001,000110::::RORV
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"rorv r<RD>, r<RT>, <RS>"
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*vr5400:
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{
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int s = MASKED (GPR[RS], 4, 0);
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GPR[RD] = ROTR32 (GPR[RT], s);
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}
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// Double Rotate Right.
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000000,00001,5.RT,5.RD,5.SHIFT,111010::::DROR
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"dror r<RD>, r<RT>, <SHIFT>"
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*vr5400:
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{
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int s = SHIFT;
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GPR[RD] = ROTR64 (GPR[RT], s);
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}
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// Double Rotate Right Plus 32.
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000000,00001,5.RT,5.RD,5.SHIFT,111110::::DROR32
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"dror32 r<RD>, r<RT>, <SHIFT>"
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*vr5400:
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{
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int s = SHIFT + 32;
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GPR[RD] = ROTR64 (GPR[RT], s);
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}
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// Double Rotate Right Variable.
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000000,5.RS,5.RT,5.RD,00001,010110::::DRORV
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"drorv r<RD>, r<RT>, <RS>"
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*vr5400:
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{
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int s = MASKED (GPR[RS], 5, 0);
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GPR[RD] = ROTR64 (GPR[RT], s);
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}
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// Media Instructions
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// ------------------
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// Note: Vector unit in R5400 supports only octal byte format.
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// Note: The sel field is deduced by special handling of the "vt"
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// operand.
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// If vt is:
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// of the form $vt[0], then sel is 0000
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// of the form $vt[1], then sel is 0001
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// of the form $vt[2], then sel is 0010
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// of the form $vt[3], then sel is 0011
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// of the form $vt[4], then sel is 0100
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// of the form $vt[5], then sel is 0101
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// of the form $vt[6], then sel is 0110
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// of the form $vt[7], then sel is 0111
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// Normal register specifier, then sel is 1011
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// Constant, then sel is 1111
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//
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// VecAcc is the Vector Accumulator.
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// This accumulator is organized as 8X24 bit (192 bit) register.
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// This accumulator holds only signed values.
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:function:::signed:vr:int fpr, int byte
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{
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signed8 b = V1_8 (value_fpr (sd, cia, fpr, fmt_long), byte);
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return b;
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}
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:function:::void:set_vr:int fpr, int byte, signed value
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{
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abort ();
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}
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:function:::signed:VecAcc:int byte
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{
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abort ();
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return 0;
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}
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:function:::void:set_VecAcc:int byte, signed value
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{
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abort ();
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}
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:function:::int:cc:int i
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{
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abort ();
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return 0;
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}
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:function:::void:set_cc:int i, int value
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{
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abort ();
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}
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:function:::signed:Min:signed l, signed r
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{
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if (l < r)
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return l;
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else
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return r;
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}
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:function:::signed:Max:signed l, signed r
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{
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if (l < r)
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return r;
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else
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return l;
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}
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:function:::signed:Compare:signed l, signed r
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{
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abort ();
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return 0;
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}
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:function:::signed:Clamp:signed l
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{
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abort ();
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return 0;
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}
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:function:::signed:Round:signed l
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{
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abort ();
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return 0;
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}
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:function:::void:ByteAlign:int vd, int imm, int vs, int vt
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{
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abort ();
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}
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:function:::signed:One_of:int vs, int vt
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{
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abort ();
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return 0;
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}
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:function:::unsigned:do_select:int i, int sel, int vt
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{
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if (sel < 8)
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return vr (SD_, vt, sel);
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else if (sel == 0x13)
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return vr (SD_, vt, i);
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else if (sel == 0x1f)
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return vt;
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else
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semantic_illegal (sd, cia);
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return 0;
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}
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:%s::::VT:int sel, int vt
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{
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static char buf[20];
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if (sel < 8)
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sprintf (buf, "v%d[%d]", vt, sel);
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else if (sel == 0x13)
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sprintf (buf, "v%d", vt);
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else if (sel == 0x1f)
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sprintf (buf, "%d", vt);
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else
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sprintf (buf, "(invalid)");
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return buf;
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}
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// Vector Add.
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010010,4.SEL,0,5.VT,5.VS,5.VD,001011::::ADD.OB
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"add.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, vr (SD_, VS, i) + do_select (SD_, i, SEL, VT));
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}
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// Vector Align.
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010010,00,3.IMM,5.VT,5.VS,5.VD,011000::::ALNI.OB
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"alni.ob v<VD>, v<VS>, v<VT>, <IMM>"
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*vr5400:
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{
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ByteAlign (SD_, VD, IMM, VS, VT);
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}
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// Vector And.
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010010,4.SEL,0,5.VT,5.VS,5.VD,001100::::AND.OB
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"and.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, vr (SD_, VS, i) & do_select (SD_, i, SEL, VT));
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}
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// Vector Compare Equal.
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010010,4.SEL,0,5.VT,5.VS,00000,000001::::C.EQ.OB
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"c.eq.ob v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_cc (SD_, i, Compare (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
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}
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// Vector Compare Less Than or Equal.
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010010,4.SEL,0,5.VT,5.VS,00000,000101::::C.LE.OB
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"c.le.ob v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_cc (SD_, i, Compare (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
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}
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// Vector Compare Less Than.
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010010,4.SEL,0,5.VT,5.VS,00000,000100::::C.LT.OB
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"c.lt.ob v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_cc (SD_, i, Compare (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
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}
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// Vector Maximum.
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010010,4.SEL,0,5.VT,5.VS,5.VD,000111::::MAX.OB
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"max.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, Max (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
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}
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// Vector Minimum.
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010010,4.SEL,0,5.VT,5.VS,5.VD,000110::::MIN.OB
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"min.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, Min (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
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}
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// Vector Multiply.
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010010,4.SEL,0,5.VT,5.VS,5.VD,110000::::MUL.OB
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"mul.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
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}
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// Vector Multiply, Accumulate.
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010010,4.SEL,0,5.VT,5.VS,00000,110011::::MULA.OB
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"mula.ob v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_VecAcc (SD_, i, VecAcc (SD_, i) + vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
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}
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// Vector Multiply, Load Accumulator.
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010010,4.SEL,0,5.VT,5.VS,10000,110011::::MULL.OB
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"mull.ob v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_VecAcc (SD_, i, 0 + vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
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}
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// Vector Multiply, Negate, Accumulate.
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010010,4.SEL,0,5.VT,5.VS,00000,110010::::MULS.OB
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"muls.ob v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_VecAcc (SD_, i, VecAcc (SD_, i) - vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
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}
|
|
|
|
// Vector Multiply, Negate, Load Accumulator.
|
|
010010,4.SEL,0,5.VT,5.VS,10000,110010::::MULSL.OB
|
|
"mulsl.ob v<VS>, %s<VT#SEL,VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_VecAcc (SD_, i, 0 - vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
|
|
}
|
|
|
|
// Vector NOr.
|
|
010010,4.SEL,0,5.VT,5.VS,5.VD,001111::::NOR.OB
|
|
"nor.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, ! (vr (SD_, VS, i) | do_select (SD_, i, SEL, VT)));
|
|
}
|
|
|
|
// Vector Or.
|
|
010010,4.SEL,0,5.VT,5.VS,5.VD,001110::::OR.OB
|
|
"or.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, vr (SD_, VS, i) | do_select (SD_, i, SEL, VT));
|
|
}
|
|
|
|
// Vector Pick False.
|
|
010010,4.SEL,0,5.VT,5.VS,5.VD,000010::::PICKF.OB
|
|
"pickf.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, cc (SD_, i) ? do_select (SD_, i, SEL, VT) : vr (SD_, VS, i));
|
|
}
|
|
|
|
// Vector Pick True.
|
|
010010,4.SEL,0,5.VT,5.VS,5.VD,000011::::PICKT.OB
|
|
"pickt.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, cc (SD_, i) ? vr (SD_, VS, i) : do_select (SD_, i, SEL, VT));
|
|
}
|
|
|
|
// Vector Read Accumulator High.
|
|
010010,1000,0,00000,00000,5.VD,111111::::RACH.OB
|
|
"rach.ob v<VD>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, EXTRACTED (VecAcc (SD_, i), 23, 16));
|
|
}
|
|
|
|
// Vector Read Accumulator Low.
|
|
010010,0000,0,00000,00000,5.VD,111111::::RACL.OB
|
|
"racl.ob v<VD>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, EXTRACTED (VecAcc (SD_, i), 7, 0));
|
|
}
|
|
|
|
// Vector Read Accumulator Middle.
|
|
010010,0100,0,00000,00000,5.VD,111111::::RACM.OB
|
|
"racm.ob v<VD>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, EXTRACTED (VecAcc (SD_, i), 15, 8));
|
|
}
|
|
|
|
// Vector Scale, Round and Clamp Accumulator.
|
|
010010,4.SEL,0,5.VT,00000,5.VD,100000::::RZU.OB
|
|
"rzu.ob v<VD>, %s<VT#SEL,VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, Clamp (SD_, Round (SD_, VecAcc (SD_, i) >> do_select (SD_, i, SEL, VT))));
|
|
}
|
|
|
|
// Vector Element Shuffle.
|
|
010010,0110,0,5.VT,5.VS,5.VD,011111::::SHFL.MIXH.OB
|
|
"shfl.mixh.ob v<VD>, v<VS>, <VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, One_of (SD_, VS, VT));
|
|
}
|
|
|
|
// Vector Element Shuffle.
|
|
010010,0111,0,5.VT,5.VS,5.VD,011111::::SHFL.MIXL.OB
|
|
"shfl.mixl.ob v<VD>, v<VS>, <VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, One_of (SD_, VS, VT));
|
|
}
|
|
|
|
// Vector Element Shuffle.
|
|
010010,0100,0,5.VT,5.VS,5.VD,011111::::SHFL.PACH.OB
|
|
"shfl.pach.ob v<VD>, v<VS>, <VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, One_of (SD_, VS, VT));
|
|
}
|
|
|
|
// Vector Element Shuffle.
|
|
010010,0101,0,5.VT,5.VS,5.VD,011111::::SHFL.PACL.OB
|
|
"shfl.pacl.ob v<VD>, v<VS>, <VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, One_of (SD_, VS, VT));
|
|
}
|
|
|
|
// Vector Shift Left Logical.
|
|
010010,4.SEL,0,5.VT,5.VS,5.VD,010000::::SLL.OB
|
|
"sll.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, vr (SD_, VS, i) << do_select (SD_, i, SEL, VT));
|
|
}
|
|
|
|
// Vector Shift Right Logical.
|
|
010010,4.SEL,0,5.VT,5.VS,5.VD,010010::::SRL.OB
|
|
"srl.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, vr (SD_, VS, i) >> do_select (SD_, i, SEL, VT));
|
|
}
|
|
|
|
// Vector Subtract.
|
|
010010,4.SEL,0,5.VT,5.VS,5.VD,001010::::SUB.OB
|
|
"sub.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, vr (SD_, VS, i) - do_select (SD_, i, SEL, VT));
|
|
}
|
|
|
|
// Vector Write Accumulator High.
|
|
010010,1000,0,00000,5.VS,00000,111110::::WACH.OB
|
|
"wach.ob v<VS>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
/* High8 */ set_VecAcc (SD_, i, (vr (SD_, VS, i) << 16) | MASKED (VecAcc (SD_, i), 15, 0));
|
|
}
|
|
|
|
// Vector Write Accumulator Low.
|
|
010010,0000,0,5.VT,5.VS,00000,111110::::WACL.OB
|
|
"wacl.ob v<VS>, <VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_VecAcc (SD_, i, (EXTEND8 (vr (SD_, VS, i)) << 8) | vr (SD_, VT, i));
|
|
}
|
|
|
|
// Vector XOr.
|
|
010010,4.SEL,0,5.VT,5.VS,5.VD,001101::::XOR.OB
|
|
"xor.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
|
*vr5400:
|
|
{
|
|
int i;
|
|
for (i = 0; i < 8; i++)
|
|
set_vr (SD_, VD, i, vr (SD_, VS, i) ^ do_select (SD_, i, SEL, VT));
|
|
}
|