aa49c64f3e
* simops.c (OP_4201): For "rac", sign extend 56 bit value before it is shifted. * d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using SIGNED64 macro.
127 lines
1.4 KiB
OpenEdge ABL
127 lines
1.4 KiB
OpenEdge ABL
.macro start
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.text
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.align 2
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.globl _start
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_start:
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.endm
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.macro exit47
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ldi r6, 1
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ldi r2, 47
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trap 15
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.endm
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.macro exit0
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ldi r6, 1
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ldi r2, 0
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trap 15
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.endm
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.macro load reg val
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ldi \reg, #\val
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.endm
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.macro load2w reg hi lo
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ld2w \reg, @(1f,r0)
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.data
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.align 2
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1: .short \hi
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.short \lo
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.text
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.endm
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.macro check exit reg val
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cmpeqi \reg, #\val
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brf0t 1f
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0: ldi r6, 1
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ldi r2, \exit
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trap 15
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1:
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.endm
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.macro check2w2 exit reg hi lo
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st2w \reg, @(1f,r0)
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ld r2, @(1f, r0)
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cmpeqi r2, #\hi
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brf0f 0f
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ld r2, @(1f + 2, r0)
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cmpeqi r2, #\lo
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brf0f 0f
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bra 2f
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0: ldi r6, 1
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ldi r2, \exit
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trap 15
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.data
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.align 2
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1: .long 0
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.text
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2:
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.endm
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.macro loadacc2 acc guard hi lo
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ldi r2, #\lo
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mvtaclo r2, \acc
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ldi r2, #\hi
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mvtachi r2, \acc
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ldi r2, #\guard
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mvtacg r2, \acc
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.endm
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.macro checkacc2 exit acc guard hi lo
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ldi r2, #\guard
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mvfacg r3, \acc
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cmpeq r2, r3
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brf0f 0f
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ldi r2, #\hi
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mvfachi r3, \acc
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cmpeq r2, r3
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brf0f 0f
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ldi r2, #\lo
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mvfaclo r3, \acc
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cmpeq r2, r3
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brf0f 0f
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bra 4f
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0: ldi r6, 1
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ldi r2, \exit
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trap 15
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4:
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.endm
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.macro loadpsw2 val
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ldi r2, #\val
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mvtc r2, cr0
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.endm
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.macro checkpsw2 exit val
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mvfc r2, cr0
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cmpeqi r2, #\val
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brf0t 1f
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ldi r6, 1
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ldi r2, \exit
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trap 15
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1:
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.endm
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.macro hello
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;; 4:write (1, string, strlen (string))
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ldi r6, 4
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ldi r2, 1
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ldi r3, 1f
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ldi r4, 2f-1f-1
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trap 15
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.section .rodata
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1: .string "Hello World!\n"
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2: .align 2
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.text
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.endm
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