old-cross-binutils/sim/mips
Frank Ch. Eigler b879096335 * Support for sky hardware interrupts. The sky-dma cannot trigger
interrupts properly yet (jlemke TODO).
Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 	to allay warnings.
	(interrupt_event): Made non-static.
start-sanitize-tx3904
	* dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 	interchange of configuration values for external vs. internal
 	clock dividers.
end-sanitize-tx3904
start-sanitize-sky
	* sky-device.c (sky_signal_interrupt): New function to generate
	interrupt event.
	* sky-device.h: Declare it.
	* sky-dma.c (check_int1): Call it.
	* sky-pke.c (pke_begin_interrupt_stall): Call it.
end-sanitize-sky
1998-06-10 17:07:10 +00:00
..
.Sanitize * Updated several files to place all sky specific runtime options 1998-06-10 17:07:09 +00:00
acconfig.h * configure: Regenerated to track ../common/aclocal.m4 changes. 1998-04-26 22:03:55 +00:00
ChangeLog * Support for sky hardware interrupts. The sky-dma cannot trigger 1998-06-10 17:07:10 +00:00
config.in
configure * Early check-in of tx3904 timer sim implementation for ECC. 1998-06-04 12:43:45 +00:00
configure.in * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips 1998-06-09 15:42:04 +00:00
dv-tx3904cpu.c * Updates to tx3904 peripheral simulations for ECC. 1998-06-09 16:54:09 +00:00
dv-tx3904irc.c * Early check-in of tx3904 timer sim implementation for ECC. 1998-06-04 12:43:45 +00:00
dv-tx3904tmr.c * Typo fix for tx3904tmr use of configuration parameters. 1998-06-10 08:58:42 +00:00
gencode.c * Handle 10 and 20-bit versions of Break instruction. Move handling 1998-06-09 16:54:08 +00:00
interp.c * Support for sky hardware interrupts. The sky-dma cannot trigger 1998-06-10 17:07:10 +00:00
m16.dc
m16.igen Debug tx19 built from igen sources. 1998-04-15 07:23:28 +00:00
m16run.c Implement 32 bit MIPS16 instructions listed in m16.igen. 1998-04-14 14:34:48 +00:00
Makefile.in Implement 32 bit MIPS16 instructions listed in m16.igen. 1998-04-14 14:34:48 +00:00
mdmx.igen
mips.dc
mips.igen * Handle 10 and 20-bit versions of Break instruction. Move handling 1998-06-09 16:54:08 +00:00
README.Cygnus
sim-main.c * SYSCALL now uses exception vector. 1998-06-02 19:53:36 +00:00
sim-main.h * Handle 10 and 20-bit versions of Break instruction. Move handling 1998-06-09 16:54:08 +00:00
sky-pke.c * Support for sky hardware interrupts. The sky-dma cannot trigger 1998-06-10 17:07:10 +00:00
sky-pke.h * Initial support for "sim list vif[01]" 1998-05-24 13:06:09 +00:00
tconfig.in
tx.igen
vr4320.igen
vr5400.igen

This directory contains two very different simulators:

	o	gencode (old)

		Gencode.c outputs a single monolithic file that is
		#included by interp.c

	o	igen (new)

		The *.igen files are used as inputs to ../igen/igen.
		A number of separate, fairly modula files, are created.

The new simulator has a number of advantages:

	o	builtin support for multi-simming (single simulator
		image supporting a number of different instruction
		set architectures).

	o	Easier maintenance. The input files are not confused
		by an intermixing with the generator code.

gencode continues to exist so that old architectures can be emulated.
*.igen should be used when adding new architectures or adding
instructions to an existing ISA.

Known bugs?

A mips16 simulator cannot be built using igen.  A custom mips16
engine.c needs to be written.

In mips.igen, the semantics for many of the instructions were created
using code generated by gencode.  Those semantic segments could be
greatly simplified.


----

Old README.Cygnus ...

> README.Cygnus
-------------------------------------------------------------------------------

The following are the main reasons for constructing the simulator as a
generator:

1) Avoid large fixed decode source file, with lots of #ifs controlling
   the compilation. i.e. keep the source cleaner, smaller and easier
   to parse.

2) Allow optimum code to be created, without run-time checks on
   instruction types. Ensure that the simulator engine only includes
   code for the architecture being targetted. e.g. This avoids
   run-time checks on ISA conformance, aswell as increasing
   throughput.

3) Allow updates to the instruction sets to be added quickly. Having a
   table means that the information is together, and is easier to
   manipulate. Having the table generate the engine, rather than the
   run-time parse the table gives higher performance at simulation
   time.

4) Keep all the similar simulation code together. i.e. have a single
   place where, for example, the addition code is held. This ensures that
   updates to the simulation are not spread over a large flat source
   file maintained by the developer.

-------------------------------------------------------------------------------

To keep the simulator simple (and to avoid the slight chance of
mis-matched files) the manifests describing an engine, and the
simulator engine itself, are held in the same source file.

This means that the engine must be included twice, with the first pass
controlled by the SIM_MANIFESTS definition.

-------------------------------------------------------------------------------
> EOF README.Cygnus