8acc9f485b
Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
136 lines
4.5 KiB
C
136 lines
4.5 KiB
C
/* Blackfin Core Event Controller (CEC) model.
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Copyright (C) 2010-2013 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef DV_BFIN_CEC_H
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#define DV_BFIN_CEC_H
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#include "sim-main.h"
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/* 0xFFE02100 ... 0xFFE02110 */
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#define BFIN_COREMMR_EVT_OVERRIDE (BFIN_COREMMR_CEC_BASE + (4 * 0))
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#define BFIN_COREMMR_IMASK (BFIN_COREMMR_CEC_BASE + (4 * 1))
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#define BFIN_COREMMR_IPEND (BFIN_COREMMR_CEC_BASE + (4 * 2))
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#define BFIN_COREMMR_ILAT (BFIN_COREMMR_CEC_BASE + (4 * 3))
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#define BFIN_COREMMR_IPRIO (BFIN_COREMMR_CEC_BASE + (4 * 4))
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#define IVG_EMU 0
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#define IVG_RST 1
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#define IVG_NMI 2
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#define IVG_EVX 3
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#define IVG_IRPTEN 4 /* Global is Reserved */
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#define IVG_IVHW 5
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#define IVG_IVTMR 6
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#define IVG7 7
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#define IVG8 8
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#define IVG9 9
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#define IVG10 10
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#define IVG11 11
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#define IVG12 12
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#define IVG13 13
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#define IVG14 14
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#define IVG15 15
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#define IVG_USER 16 /* Not real; for internal use */
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#define IVG_EMU_B (1 << IVG_EMU)
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#define IVG_RST_B (1 << IVG_RST)
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#define IVG_NMI_B (1 << IVG_NMI)
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#define IVG_EVX_B (1 << IVG_EVX)
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#define IVG_IRPTEN_B (1 << IVG_IRPTEN)
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#define IVG_IVHW_B (1 << IVG_IVHW)
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#define IVG_IVTMR_B (1 << IVG_IVTMR)
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#define IVG7_B (1 << IVG7)
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#define IVG8_B (1 << IVG8)
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#define IVG9_B (1 << IVG9)
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#define IVG10_B (1 << IVG10)
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#define IVG11_B (1 << IVG11)
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#define IVG12_B (1 << IVG12)
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#define IVG13_B (1 << IVG13)
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#define IVG14_B (1 << IVG14)
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#define IVG15_B (1 << IVG15)
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#define IVG_UNMASKABLE_B \
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(IVG_EMU_B | IVG_RST_B | IVG_NMI_B | IVG_EVX_B | IVG_IRPTEN_B)
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#define IVG_MASKABLE_B \
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(IVG_IVHW_B | IVG_IVTMR_B | IVG7_B | IVG8_B | IVG9_B | \
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IVG10_B | IVG11_B | IVG12_B | IVG13_B | IVG14_B | IVG15_B)
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#define VEC_SYS 0x0
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#define VEC_EXCPT01 0x1
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#define VEC_EXCPT02 0x2
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#define VEC_EXCPT03 0x3
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#define VEC_EXCPT04 0x4
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#define VEC_EXCPT05 0x5
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#define VEC_EXCPT06 0x6
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#define VEC_EXCPT07 0x7
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#define VEC_EXCPT08 0x8
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#define VEC_EXCPT09 0x9
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#define VEC_EXCPT10 0xa
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#define VEC_EXCPT11 0xb
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#define VEC_EXCPT12 0xc
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#define VEC_EXCPT13 0xd
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#define VEC_EXCPT14 0xe
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#define VEC_EXCPT15 0xf
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#define VEC_STEP 0x10 /* single step */
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#define VEC_OVFLOW 0x11 /* trace buffer overflow */
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#define VEC_UNDEF_I 0x21 /* undefined instruction */
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#define VEC_ILGAL_I 0x22 /* illegal instruction combo (multi-issue) */
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#define VEC_CPLB_VL 0x23 /* DCPLB protection violation */
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#define VEC_MISALI_D 0x24 /* unaligned data access */
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#define VEC_UNCOV 0x25 /* unrecoverable event (double fault) */
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#define VEC_CPLB_M 0x26 /* DCPLB miss */
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#define VEC_CPLB_MHIT 0x27 /* multiple DCPLB hit */
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#define VEC_WATCH 0x28 /* watchpoint match */
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#define VEC_ISTRU_VL 0x29 /* ADSP-BF535 only */
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#define VEC_MISALI_I 0x2a /* unaligned instruction access */
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#define VEC_CPLB_I_VL 0x2b /* ICPLB protection violation */
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#define VEC_CPLB_I_M 0x2c /* ICPLB miss */
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#define VEC_CPLB_I_MHIT 0x2d /* multiple ICPLB hit */
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#define VEC_ILL_RES 0x2e /* illegal supervisor resource */
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/*
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* The hardware reserves 63+ for future use - we use it to tell our
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* normal exception handling code we have a hardware error
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*/
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#define VEC_HWERR 63
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#define VEC_SIM_BASE 64
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#define VEC_SIM_HLT (VEC_SIM_BASE + 1)
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#define VEC_SIM_ABORT (VEC_SIM_BASE + 2)
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#define VEC_SIM_TRAP (VEC_SIM_BASE + 3)
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#define VEC_SIM_DBGA (VEC_SIM_BASE + 4)
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extern void cec_exception (SIM_CPU *, int vec_excp);
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#define HWERR_SYSTEM_MMR 0x02
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#define HWERR_EXTERN_ADDR 0x03
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#define HWERR_PERF_FLOW 0x12
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#define HWERR_RAISE_5 0x18
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extern void cec_hwerr (SIM_CPU *, int hwerr);
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extern void cec_latch (SIM_CPU *, int ivg);
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extern void cec_return (SIM_CPU *, int ivg);
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extern int cec_get_ivg (SIM_CPU *);
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extern bool cec_is_supervisor_mode (SIM_CPU *);
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extern bool cec_is_user_mode (SIM_CPU *);
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extern void cec_require_supervisor (SIM_CPU *);
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extern bu32 cec_cli (SIM_CPU *);
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extern void cec_sti (SIM_CPU *, bu32 ints);
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extern void cec_push_reti (SIM_CPU *);
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extern void cec_pop_reti (SIM_CPU *);
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#endif
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